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Cadence ® Parasitic Simulation User Guide

Product Version 5.0December 2002


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© 1999-2002 Cadence Design Systems, Inc. All rights reserved.Printed in the United States of America.

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Cadence Parasitic Simulation User Guide

December 2002 3 Product Version 5.0

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Typographic and Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1Diva Flow: Simulating Analog Circuits with Parasitics . . . . . . . . 11Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Preparing Cell Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Preparing Technology Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Adding Component Description Format (CDF) Simulation Information . . . . . . . . . . . 13

Creating Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Creating Extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Extracting Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Creating ConcICe Views from Extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Comparing Schematic and Extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Building an analog_extracted View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Creating and Using a Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Probing Parasitic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Backannotating Parasitic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2Diva Flow: Simulating Mixed-Signal Circuits with Parasitics 33Estimating Delays (Pre-Layout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Setting Up for Pre-Layout Delay Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Simulating a Design with Pre-Layout Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Calculating Delays (Post-Layout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Preparing for Post-Layout Mixed-Signal Parasitic Simulation . . . . . . . . . . . . . . . . . . . 46Creating mixed_extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Modifying the Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Contents


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Setting the Mixed-Signal Simulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Simulating a Design (Post-Layout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Probing Parasitic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3Diva Flow: Working Through an Extended Design Example 71Simulating with Schematic Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Conguring and Partitioning the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Modifying the Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Choosing an Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Generating a Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Plotting Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Alternate Waveform Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Saving the Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Simulating with Analog Parasitics and Estimated Digital Delays . . . . . . . . . . . . . . . . . . . 88Extracting Analog Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Setting Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Estimating Digital Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Simulating with Analog and Digital Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Cell Library Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Creating a Mixed Extracted View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Building a Mixed Extracted View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Whole Design Approach to Mixed-Signal Parasitic Simulation . . . . . . . . . . . . . . . . . 126Comparing Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

4Assura Flow: Simulating Analog Circuits with Parasitics . . . 131Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Preparing Cell Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Preparing Technology Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Creating Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Creating Extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Comparing Views using LVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134


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Building an av_extracted View using RCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Building an av_analog_extracted View using MSPS (Optional) . . . . . . . . . . . . . . . . 140

Creating and Using a Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Probing Parasitic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149Backannotating Parasitic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

ALVS Form Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Diva . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Assura . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Schematic and Layout Format Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160


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Preface

This manual describes how you can use Cadence ® tools to investigate the effect of parasiticson your circuits. The guidance here is designed for users who are already familiar with circuitdesign, simulation, and layout.

The information is divided into four chapters. Chapter’s 1-3 are based on the Diva physicalverication ow and Chapter 4 on the Assura ™ ow.

Chapter 1, “Diva Flow: Simulating Analog Circuits with Parasitics” describes the ow andtools for analog circuits. If your design contains only analog circuits, and you use the Divaphysical verication tool to extract parasitics, use the information in Chapter 1.

Chapter 2, “Diva Flow: Simulating Mixed-Signal Circuits with Parasitics,” describes the owused for digital or mixed-signal designs. Taking digital elements into account leads to a owthat includes using the Cadence timing analyzer. If your design is digital or mixed-signal, youcan skip Chapter 1 and go directly to Chapter 2.

Chapter 3, “Diva Flow: Working Through an Extended Design Example” is a tutorial thatguides you through a series of examples illustrating the information in Chapter’s 1 and 2.

Chapter 4, “Assura Flow: Simulating Analog Circuits with Parasitics” describes the ow andtools for analog circuits. If your design contains only analog circuits, and you use the Assuraphysical verication tool to extract parasitics, use the information in Chapter 4.

This preface discusses the following:

Related Documents on page 7

Typographic and Syntax Conventions on page 8

Related Documents

Running a simulation with parasitics requires knowledge of several Cadence tools, which aredescribed in the following documents.

Cadence Analog Circuit Design Environment User Guide

Component Description Format User Guide

http://%24anasimhelp.pdf/http://%24anasimhelp.pdf/http://%24cdfuser.pdf/http://%24cdfuser.pdf/http://%24anasimhelp.pdf/


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Cadence Parasitic Simulation User GuidePreface


ConcICe Help

Assura Diva Verification Reference

Cadence Hierarchy Editor User Guide

Pearl Timing Analyzer User Guide

SDF Annotator User Guide

Technology File and Display Resource File User Guide

Assura Physical Verification User Guide

Assura Physical Verification Developer Guide

Typographic and Syntax Conventions

This section describes typographic and syntax conventions used in this manual.

text Indicates text you must type exactly as it is presented.

z_argument Indicates text that you must replace with an appropriateargument. The prex (in this case, z _ ) indicates the data typethe argument can accept. Do not type the data type orunderscore.

[ ] Denotes optional arguments. When used with vertical bars, theyenclose a list of choices from which you can choose one.

{ } Used with vertical bars and encloses a list of choices from whichyou must choose one.

| Separates a choice of options.

… Indicates that you can repeat the previous argument.

=> Precedes the values returned by a Cadence ® SKILL languagefunction.

/ Separates the possible values that can be returned by aCadence SKILL language function.

text Indicates names of manuals, menu commands, form buttons,and form elds.

http://%24concice.pdf/http://%24concice.pdf/http://%24divaref.pdf/http://%24divaref.pdf/http://%24hiereditor.pdf/http://%24hiereditor.pdf/http://%24pearluser.pdf/http://%24pearluser.pdf/http://%24techfileuser.pdf/http://%24techfileuser.pdf/http://%24techfileuser.pdf/http://%24pearluser.pdf/http://%24hiereditor.pdf/http://%24divaref.pdf/http://%24concice.pdf/


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Important

The language requires many characters not included in the preceding list. You musttype these characters exactly as they are shown in the syntax.


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1Diva Flow: Simulating Analog Circuitswith Parasitics

This chapter describes how you can use Cadence ® tools to investigate the effect of parasiticson analog circuits. By accounting for the effect of parasitics, you can improve the accuracy of

your circuit simulations. If your design includes digital or mixed-signal circuits, skip thischapter and go to Chapter 2, “Diva Flow: Simulating Mixed-Signal Circuits with Parasitics.”

Click a topic below for more information.

“Overview” on page 11

“Preparing Cell Libraries” on page 13

“Creating Designs” on page 16

“Creating Extracted Views” on page 17

“Creating and Using a Conguration” on page 24“Simulating the Design” on page 29

“Probing Parasitic Values” on page 30

Overview

Simulating an analog circuit with parasitics requires these steps.

1. Preparing cell libraries

2. Creating an analog_extracted view of your design

In this step, the tool calculates parasitics from information in the layout view of yourcircuit.


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Cadence Parasitic Simulation User GuideDiva Flow: Simulating Analog Circuits with Parasitics


The following ow diagram illustrates the substeps in creating an analog_extracted viewusing the Assura ™ Diva ® physical verication tool. The substeps for the Assura RCnetwork reducer are shown with dotted lines because they are optional.

3. Creating a conguration for your design

4. Simulating the design with parasitics included

After a successful simulation, you can select terminals and device pins on the schematic anduse plot commands to display the results in a waveform window. The resulting waveforms canbe used with all Cadence analog design environment (ADE) calculation and analysis tools.

layout View

Extractor

extracted View

Rules File

LVS

map les

Build_Analog

analog_extractedView

Assura RC network reducer

concICe View

Diva Physical Verication


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Preparing Cell Libraries

Before you can follow the ow outlined in this chapter, you need to provide the following viewsand component description format (CDF) information for analog primitives and parasitic cells.

The analogLib library contains examples of analog primitives and parasitic cells that youcan copy to create your cell library.

Preparing Technology Files

To prepare a library for parasitic extraction,

1. Describe the technology layers.

For details about the technology layers, refer to the Technology File and Display Resource File User Guide .

2. Add or modify the verication rules used by the Diva processes DRC, Extract, and LVS.

Refer to the Assura Diva Verification Reference for details about creating vericationand extraction rules.

Adding Component Description Format (CDF) Simulation Information

Refer to the Component Description Format User Guide for more details about the stepsin this section.

To netlist primitives correctly, you must verify the auLvs CDF parameters for each primitive.

1. Start the Cadence software by typing icfb & at the command prompt.

Analog primitives must have Parasitic cells (such as presistors andpcapacitors) must have

symbol cellview symbol cellview

layout cellview or extraction rules that theextractor will recognize

auLvs cellview for analog primitives

Model matching the simulator you use CDF simulation information for auLvs

auLvs cellview that provides parametervalues used by LVS

CDF component parameters for resistance(r) and capacitance (c)

http://%24techfileuser.pdf/http://%24techfileuser.pdf/http://%24divaref.pdf/http://%24cdfuser.pdf/http://%24divaref.pdf/http://%24techfileuser.pdf/http://%24techfileuser.pdf/


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For more information about the options you can use with the command to start thesoftware, refer to the Cadence Design Framework II User Guide .

2. In the command interpreter window (CIW), choose Tools – CDF – Edit .The Edit Component CDF form appears.

3. In the upper portion of the form, choose Cell for CDF Selection and Base for CDF Type .

You must edit the base-level CDF for changes to be effective.

4. Fill in the Library Name and Cell Name elds, or click the Browse button to select thecell.

The Edit Component CDF form expands to display additional information.

5. In the Simulator Information area of the expanded Edit Component CDF form, click onEdit .

http://%24dfhelp.pdf/http://%24dfhelp.pdf/


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The Edit Simulation Information form appears, displaying existing CDF information aboutauLvs netlisting.

6. Select auLvs in the Choose Simulator drop-down list box.

7. Ensure that the netlistProcedure eld species ansLvsCompPr im . This is theinternal auLvs procedure for netlisting primitives.

8. In the instParameters eld, specify the parameters you want in the netlist.

A component can have several parameters, such as temperature coefcients, that do notapply to LVS netlist comparison. Your LVS comparison rules tell LVS how to handle suchparameters.

If model is included in the instParameters eld, auLvs uses the value of the modelproperty in the instance instead of the value of componentName in the netlist.

9. In the componentName eld, type the component name you want included in thenetlist.

This optional eld allows you to use a common name in the netlist for different cells. Forexample, 3-terminal cellviews (with programmable bulk nodes) and 4-terminal cellviews


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(with a bulk node as a pin) that have distinct names like nmos3 and nmos4 can benetlisted with the same component name like nmos .

The component names pcapacitor , presistor , pinductor , and pdiode are usedfor parasitic devices. All these devices are removed from the netlist before layout versusschematic (LVS) runs but are used in simulation and backannotation. For presistors andpinductors, the nets are shorted together.

10. In the termOrder eld, type the names of the device terminals as they appear in thesymbol cellview.

This is the order in which the terminals are netlisted.

11. If termOrder uses programmable nodes, type the names of the terminals indeviceTerminals .

The input is the same as for termOrder , but programmable nodes are replaced bynames in this eld.

12. For existing designs that use older databases, use propMapping to change the nameof an instance parameter.

This allows instParameter names that use lowercase letters to be mapped to LVS rulesthat are dened in uppercase letters.

Note: Do not use this feature for new designs.

13. In the Permute Rule eld, specify the LVS permute rule used to dene equivalent pins.

14. Click OK on the Edit Simulation Information form and Apply on the Edit Component CDFform to accept your changes.

Note: The CDF parseAsNumber property distinguishes strings from numbers in numericparameters. String parameters without the parseAsNumber property set to true arenetlisted as strings beginning and ending with “\”. This feature is not compatible with releasesbefore 4.4.2.

Creating Designs

If you intend to extract parasitic components from the layout view and run a simulation withparasitics, use the following guidelines to avoid problems as you plan your design.

Devices with the componentName parameter set to pcapacitor , presistor , pinductor ,and pdiode are automatically removed from the netlist. Do not use these names for yourcomponents.

Nets are shorted together for LVS on presistors and pinductors.


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Do not use the LVS permuteDevice parameter to match groups of components in aseries because that makes it impossible to determine which device is which for waveformprobing.

Creating Extracted Views

You use the Diva physical verication tool to extract parasitics from the layout view of a block.Then you use LVS to compare the extracted view to the schematic view to identify areas thatare not consistent between the views. After a successful LVS run, you create ananalog_extracted view of the design.

Extracting Parasitics

To extract parasitics from the layout view of a cell or block,

1. Be sure that the environment variable CDS_Netlisting_Mode is set to Analog .

2. Choose Verify – Extract from the layout cellview of the cell.


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The Extractor form appears.

3. Choose flat for Extract Method .

You need to use at extraction because parasitic capacitance values can vary betweendifferent instances of the same cell. Each cell, therefore, must be extracted.

4. (Optional) Choose Join Nets With Same Name .

This ensures that nets with the same name are joined automatically.

5. To select the types of parasitics you want extracted, click Set Switches .


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The Set Switches form appears. The parasitics displayed vary, depending on theextraction rules le dened for your design. In some cases, you do not need to make anyselection.

To select more than one item, click on your rst selection, then hold down the Controlkey and make the rest of your selections.

6. When you have specied the parasitics you want, click OK .

The Extractor form reappears with the parasitics you selected in the Switch Names eld.

7. Click OK or Apply to create the extracted views.

A message in the command interpreter window (CIW) tells you when the extractionprocess is complete.

Creating ConcICe Views from Extracted Views

The Assura RC network reducer reduces networks with a large amount of parasitic resistanceand capacitance data into smaller, electrically equivalent networks that you can more easily


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use with analysis tools. If you decide to use concICe views, the ow described in this chaptercan accommodate them. However, you should be aware of the following.

In a concICe view, all cross-coupling capacitors between analog nets are grounded.When you use a concICe view in the ow, you can probe interconnects in the layout viewonly at the terminals.

For detailed information on creating concICe views from extracted views, see the ConclCe Help .

Comparing Schematic and Extracted Views

To compare the schematic view with the extracted view created earlier, follow these steps. (Tocompare the schematic view with a concICe view, follow the same steps but substitute theconcICe view for the extracted view.)

1. From a window displaying the extracted view, choose Verify – LVS .

http://%24concice.pdf/


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The LVS form appears. For a detailed description of the elds and buttons, seeAppendix A, “LVS Form Field Descriptions.”


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2. Depending on which views are open, use one of the following procedures to identify theschematic and extracted views that you want to compare.

3. Enter the names of the rules le and rules library for the Diva LVS rules.

4. Click the Run button near the bottom of the form to begin the comparison.

5. When the comparison nishes, click Info .

If both the schematic and extractedviews are open If only the extracted view is open

1. Click the Sel by Cursor buttonbelow the schematic detail, thenclick the cursor in the openschematic view.

2. Do the same for the extracted view.

1. Click the Sel by Cursor buttonbelow the extracted detail, then clickthe cursor in the open extractedview.

2. Click the Browse button below theschematic detail and select the

schematic view.

Click here.


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The Display Run Information form appears.

6. Click Log File .

Scroll through the log le to the netlist comparison section near the end of the le. Thissection identies any mismatches between the two les. Each error is described in thesections following the comparison results.

Not all mismatches are fatal. Look over the comparison results to determine if you needto correct one of the les and redo the extraction and comparison or if you can proceed

with the views as they are.7. Choose File – Close Window in the log le window.

8. Click Cancel in the Display Run Information form.

9. Correct any problems in the schematic or extracted views.

10. If necessary, rerun the comparison.

Building an analog_extracted View

When the comparison between schematic and extracted views is acceptable, you need toselect the parasitics to use for simulation. You also need to build the analog_extracted view.

1. In the LVS form, click on Build Analog .

Click here


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The Build Analog Extracted View form appears.

2. Select one of the following choices to specify the analog parasitics that you want to usefor simulation.

3. Click OK to accept your settings and build the analog_extracted view.

Creating and Using a Conguration

This section explains how to set up a conguration so that the simulator runs with theanalog_extracted view created in the previous step. The steps given here for using theHierarchy Editor to create a conguration are abbreviated. For complete information, see the

Select If you want to

Include All Simulate with all the parasitics that have been extracted.

Set From Schematic Select parasitics to include in the simulation by placingspecial symbols (spresistor, spcapacitor, spinductor,and spcapacitor2) on nets in the schematic view. Thespcapacitor2 device is used to include parasitics in thesimulation that appear between two specied nets. Ifyou add or remove symbols from the schematic, clickCheck and Save to save the modied view.

The parasitics you select by placing these symbols

(which are provided in sbaLib ) are the only onesincluded in the simulation.

If you choose Set From Schematic and click OK without identifying any nets on the schematic, theExtracted Parasitics Selective Annotation form asks youto conrm your choice.

None Simulate with none of the parasitics.


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Cadence Hierarchy Editor User Guide . If your design already has a conguration, skip toStep 13 .

To create a conguration for your design,1. From the CIW, choose File – New – Cellview .

The Create New File form appears.

2. Choose the library for the new le.

3. Type the name of the cell for which you want to create the conguration.

The top-level cell for your design is usually the appropriate cell to use.

4. If you do not want to use config as the view name, type the name you want into theView Name eld.

5. Choose Hierarchy-Editor from the Tool drop-down list box.

6. Ensure that the Library path file eld correctly species the cds.lib le that containsthe paths to your libraries.

7. Click OK .

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The New Conguration form appears.

8. Click on the Use Template button located at the bottom of the form.

The Use Template form appears.

9. Select a template that is compatible with the simulator you are running from the Name drop-down list box.


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10. Click OK in the Use Template form.

The New Conguration form redisplays with default data for the Top Cell and Global

Bindings sections. This allows you to modify a typical view list and stop list, rather thancreating them from scratch.

Templates exist for each of the simulators. (To create templates that provide defaults forthese fields, see the Cadence Hierarchy Editor User Guide. )

11. In the Top Cell section, enter the library, cell name, and schematic cellview from whichto build the conguration.

Be sure to specify schematic for the view type because the conguration is built fromthe original schematic of your design.

12. Click OK .

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The Hierarchy Editor window displays your data.

The Hierarchy Editor window congures the design by using a default View List andStop List in the Global Bindings section. You need to modify these lists for your design.


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13. Use one of the following methods to specify the analog_extracted view for the cells orblocks for which you want parasitics simulated.

14. Choose View – Update to recongure the design to reect your changes.

The Update Sync-up form appears.

15. Click OK .

16. Choose File – Save to save the conguration with your changes.

17. Choose File – Exit to close the Hierarchy Editor.

Simulating the Design

To run the simulation,1. In the CIW, choose Tools – Analog Environment – Simulation .

The Analog Design Environment Simulation window appears.

2. Choose Setup – Design .

The Choosing Design form appears.

To specify views for individual blocks To specify views for multiple blocks

1. In the Instance Binding section ofthe Hierarchy Editor window,position the cursor in the View To Use column of the appropriateblock.

Note: If the Instance Binding section is not visible in the window,choose View – Instance Table to

display this section.2. Press the right mouse key to display

a list of commands.

3. Choose Select View to display thelist of views for this block.

4. Choose analog_extracted as theview for this block.

➤ In the Global Bindings section ofthe Hierarchy Editor window, addanalog_extracted as the rstview in the View List text eld.

This ensures that theanalog_extracted view is theselected view for every cell that hasan analog_extracted view.


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3. Choose the library and cell name of your design.

4. Choose config from the View Name drop-down list box.

5. Click OK .

This view supplies conguration as well as schematic information.

6. In the Analog Design Environment Simulation window, choose your simulator, modelpath, environment variables, analyses, and simulator options.

7. Choose Simulation – Run .

When complete, the schematic appears so that you can select outputs and probe thedesign.

8. Choose Outputs – Set from Schematic .9. Click on terminals in the schematic or in the layout views of the blocks where parasitics

were extracted, to select outputs.

Note: The only places where connections on different views are guaranteed to match are oncomponent terminals.

Probing Parasitic Values

By probing the schematic or extracted view, you can examine the instances of parasiticcomponents. To probe parasitic values, follow these steps.

1. In the LVS form, click the Parasitic Probe button.

The Parasitic Probing form appears.

2. In the Max list size eld, specify how many parasitic instances to display.

3. Sort parasitics by resistance or capacitance by selecting R or C .


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4. Click the appropriate button to specify which parasitics should be collected.

❑ Click Whole Net and then click on a net in the schematic or extracted view to display

an ordered list of all the parasitics on the net. The largest resistances orcapacitances appear at the top of the list.

❑ Click Point to Point and then click on two pins or instance pins in the schematic orextracted view to collect all the parasitics between two points.

If the points are on the same net, both resistances and capacitances are collected.If the points are on different nets, only capacitances are collected.

❑ Click Net to Net and then click on two nets in the schematic or extracted view tocollect parasitic capacitances between two different nets.

A list of the collected parasitic instances appears. Select an instance from this list tohighlight the component symbol associated with this parasitic on the extracted view.

Backannotating Parasitic Values1. Click the Backannotate button on the LVS form to backannotate the resistances and

capacitances to the schematic.

The Parasitic Backannotation form appears.

2. Select the font size and label offsets that you want and click the Add Parasitics button.

Resistance and capacitance labels appear on the schematic view. To see them, youmight need to zoom in on a portion of the schematic. Note that the new informationdisplayed on the schematic is for viewing only. Using the Add Parasitics button does notinclude the parasitics in the schematic.

3. Click the Remove Parasitics button to remove these labels.

4. Choose Print All to write all of the parasitics to a le.


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The Print All Parasitics form appears.

5. Click the appropriate Sort Parasitics by button.

Select R for a list sorted by resistance. Select C for a list sorted by capacitance.

6. Specify the lename for the printed listing.


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2Diva Flow: Simulating Mixed-SignalCircuits with Parasitics

The information in this chapter describes how you can use Cadence ® tools to investigate theeffect of parasitics on mixed-signal circuits. By accounting for the effect of parasitics, you can

improve the accuracy of your circuit simulations. If your design includes only analog circuits,go to Chapter 1, “Diva Flow: Simulating Analog Circuits with Parasitics” instead.

Click a topic below for more information.

“Overview” on page 34

“Estimating Delays (Pre-Layout)” on page 34

❑ “Setting Up for Pre-Layout Delay Estimation” on page 35

❑ “Simulating a Design with Pre-Layout Estimation” on page 43

“Calculating Delays (Post-Layout)” on page 43❑ “Preparing for Post-Layout Mixed-Signal Parasitic Simulation” on page 46

❑ “Creating mixed_extracted Views” on page 51

❑ “Modifying the Conguration” on page 61

❑ “Setting the Mixed-Signal Simulation Options” on page 62

❑ “Simulating a Design (Post-Layout)” on page 64

“Probing Parasitic Values” on page 65


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Cadence Parasitic Simulation User GuideDiva Flow: Simulating Mixed-Signal Circuits with Parasitics


Overview

The ows in this chapter describe two ways to calculate delays for mixed-signal circuits.

You can estimate delays before layout by using timing library format (TLF) and fan-in andfan-out information.

You can use layout information to determine delays with increased accuracy.

The pre-layout ow is discussed in “Estimating Delays (Pre-Layout).” For information on usinglayout information to calculate delays, see “Calculating Delays (Post-Layout)” on page 43 .

Before following any of the ows in this chapter, be sure that the environment variableCDS_Netlisting_Mode is set to Analog . To ensure that all the tools for the ow are

available, start your session with the command icfb .For more information about the options you can use with the command to start the software,refer to the Cadence Design Framework II User Guide .

Estimating Delays (Pre-Layout)

Even without layout information, you can obtain useful delay estimates of digital partitions byfollowing the pre-layout mixed-signal parasitic simulation (MSPS) ow illustrated in Figure 2-1on page 35 . The gure illustrates how Cadence timing analyzer operates on the digital netlist

to produce a standard delay format (SDF) le. The MSPS ow then annotates the SDF le tothe top-level cell instance.

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Figure 2-1 Pre-Layout Simulation Flow

Setting Up for Pre-Layout Delay Estimation

To specify that delays are to be estimated, set up the Mixed Signal Options form as describedin the following steps.

1. Choose Simulation – Options – Mixed Signal in the Analog Design EnvironmentSimulation window.

Top Level

Mixed-Signal Netlister

Analog Netlist

Cadence timing analyzer

SPECTRE ®

Digital Netlist

SDF

Conguration View

VERILOG ® .VMXIPC

pearl.cmd

gcfConstraints.gcf

compiled TLF


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The Mixed Signal Options form appears.

2. If necessary, set the DC Interval and Max DC Iterations elds.

For information on these elds, see the Cadence Mixed-Signal Circuit Design Environment User Guide .

3. Turn on the Estimate (Pre-Layout) button.

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The form expands as shown below:

4. Edit the delay calculator les as necessary.

For guidance, see “Preparing the pearl.cmd and gcfConstraints.gcf Files” on page 37 .

5. Ensure that you have a correctly set up the SDF annotator le ( sdf.cfg ).

For more information, see “Editing the SDF Annotator File” on page 42 .

Preparing the pearl.cmd and gcfConstraints.gcf Files

The Cadence timing analyzer requires two control les: pearl.cmd andgcfConstraints.gcf . The pearl.cmd le is the command initialization le for theCadence timing analyzer. The gcfConstraints.gcf le species the boundary andoperating conditions for the analysis and lists the compiled timing library format (CTLF) le tobe used. You can do either of the following:

Provide these les in one of the locations listed in “Locations Searched for the pearl.cmdand gcfConstraints.gcf Files” on page 38

If you provide the les, clicking on the Command and Constraints buttons opens theles for editing.

Create these les from templates by clicking on the Command and Constraints buttons

If the les do not exist, clicking the buttons copies templates to your run directory andopens the copies for editing.

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Locations Searched for the pearl.cmd and gcfConstraints.gcf Files

The Cadence timing analyzer searches for the pearl.cmd and gcfConstraints.gcf les

in the following locations, which are searched in the order given.1. The run directory

For example, if the simulation directory is $HOME/simulation , the run directory is$HOME/simulation/ topLevelCellName / simulatorName / viewName /

netlist/digital

2. Your working directory (where you start icfb or icms )

3. Your home directory ($HOME)

4. Your installation path ( $CDS_INST_DIR/tools/dfII/etc/tools/mmsimenv )

Editing the pearl.cmd and gcfConstraints.gcf Files

You can change the contents of the gcfConstraints.gcf and pearl.cmd les asnecessary.


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1. To change the gcfConstraints.gcf le, click the Constraints button in the MixedSignal Options form. Your default text editor opens, displaying the contents of the le. Forexample, the le might contain information like this.

Important

Change the design name to the name of your top-level design. Ensure that the pathto the compiled timing library format (CTLF) les is specied with one of thefollowing.

❑ An absolute path

❑ A relative path dened with respect to the run directory

For more information about the run directory, see “Locations Searched for the pearl.cmdand gcfConstraints.gcf Files” on page 38 .

Do not use a tilde (~) to specify the path.

When you nish editing the le, save it.

2. To change the contents of the pearl.cmd le, click the Command button in the MixedSignal Options form.

(GCF(HEADER(VERSION "1.2")

(DESIGN "ccadc")(TIME_SCALE 1.0E-09)

)(GLOBALS

(GLOBALS_SUBSET ENVIRONMENT(OPERATING_CONDITIONS "" 1.00 3.13 100.00)(EXTENSION "CTLF_FILES" ("./timing.ctlf"))

(VOLTAGE_THRESHOLD 10.0 90.0))

)(CELL()

(SUBSET TIMING(ENVIRONMENT

(INPUT_SLEW 1.60 1.60))

))

)

Change this to the name of your top-level design.

Specify the path to the compiled CTLFle here.

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The Command Options form appears.

The Command Options form allows you to change the options that are listed in thefollowing table.

Option Default Meaning

Power Node VDD The name of the power node. You must specify thisvalue for cells with tie-high connections.

Ground Node VSS The name of the ground node. You must specify thisvalue for cells with tie-low connections.


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Library Corner

all One of all , min , typ , or max indicating the type ofdelays the Cadence timing analyzer uses forcalculating total delay. The Library Corner choicealso applies to PVT values that are dened as triplets.

SDF les report delays as triplets; for example,(1.999:2.685:3.244). If you specify al l , the output is inthe min:typ:max triplet format, otherwise all threevalues in the triplet are the same. For example, if youspecify max , the output for this example is(3.244:3.244:3.244).

Slew Mode all One of al l , min , typ , or max indicating the type of riseand fall times (slew rates) that the Cadence timinganalyzer uses.

Wireload Library

Blank A timing library format (TLF) library name dened withthe TLF Library statement. The netlister searches for awireload model only in this library.

If you do not specify a library, the netlister searches allthe TLF libraries until it nds a wireload model with thespecied name or group.

Wireload

Group and Value

Blank A group of wireload models specied with a

Wireload_By_ xxx statement in the TLF library,where x xx is Area , Cell_Count , Gate_Count , orTransistor_Count . The value species the blockarea, cell count, gate count, or transistor count. Formore information, see the Pearl Timing Analyzer User Guide

Wireload Name

Blank The name of a wireload model specied with aWireload or Wireload_By_ xxx statement in theTLF library.

Wireload

Topology

balanced One of none , cap , best , worst , balanced , or star .

For use only with RC estimation, this option describesthe topology of the estimated nets.

SDF Timing Scale

ns Either ns (nanoseconds) or ps (picoseconds). The unitof time the Cadence timing analyzer uses whenreporting delay values.


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Editing the SDF Annotator File

The simulator uses the sdf.cfg le to control the SDF annotation. An existing sdf.cfg lethat you want the simulator to use must be located in one of the following locations, which aresearched in the following order. These are the same locations searched for the pearl.cmdand gcfConstraints.gcf les.

1. The run directory

For example, if the simulation directory is $HOME/simulation , the run directory is$HOME/simulation/ topLevelCellName / simulatorName / viewName /

netlist/digital

2. Your working directory (where you start icfb or icms )

3. Your home directory ($HOME)

4. Your installation path ( $CDS_INST_DIR/tools/dfII/etc/tools/mmsimenv )

To edit the sdf.cfg le, or to copy a template so that you can create a new sdf.cfg le,

1. Click Config on the Mixed Signal Options form.

SDF Precision

4 for ns units; 0 forps units

The number of digits the Cadence timing analyzerprints after the decimal point.

Report Boundary Nets

Notselected

A button telling the Cadence timing analyzer tocalculate the interconnect delays for nets connecting toprimary I/O pins (ports) at the boundary of the designblock. If you select this button, the Cadence timinganalyzer reports boundary net delays in the SDF le.

SDF Edge Specifier

Notselected

A button telling the Cadence timing analyzer to writeSDF IOPATH statements with edge speciers on theinput signal when both inverting and non-invertingpaths exist between two pins.



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The SDF Annotator Cong File form appears.

2. Change the values as necessary. If you need guidance, see the SDF Annotator User Guide .

Simulating a Design with Pre-Layout EstimationAfter you set up the mixed-signal simulation options, you are ready to simulate. Follow thestandard mixed-signal simulation process.

Calculating Delays (Post-Layout)

Simulating a mixed-signal design with parasitics calculated from layout information involvesthe following major steps:

1. Preparing cell libraries2. Creating a mixed_extracted view of your design

3. Creating or modifying a conguration for the design so that mixed_extracted views areused for the mixed-signal simulation

4. Using one of the mixed-signal simulators to simulate the congured schematic withparasitics included


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Figure 2-2 shows the ow for steps 2 and 3 in graphical format. The Assura ™ RC networkreducer steps are shown with dotted lines because they are optional.


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Figure 2-2 Post-Layout Simulation Flow

layout View

Extractor

extracted View

LVS

Build_Mixed

cong View

cong View

mixed_extracted SPFView

.simrc File

map les

Assura ™ RC network reducer

concice View

Rules FileDiva Physical Verication


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Digital parasitics are calculated by the Cadence timing analyzer or can be imported from anexternal calculator. The SDF le created by the Cadence timing analyzer is annotated to thenetlist at simulation time.

Preparing for Post-Layout Mixed-Signal Parasitic Simulation

Before you can run a post-layout mixed-signal parasitic simulation, you must ensure that thenecessary preliminary steps are complete. The following sections describe the tasks.

“Preparing Libraries for Post-Layout Mixed-Signal Parasitic Simulation” on page 47

“Preparing Layout Views for Analog and Digital Cells” on page 49

“Updating View and Stop Lists for LVS” on page 50

gcfConstraints.gcf

MS Netlister

Analog Netlist Digital Netlist

SPECTRE ® VERILOG ® .VMXIPC

Top Levelcong View SPF

Cadence timing analyzer

SDF

External SDF

pearl.cmd

compiled TLF

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“Preparing to Create the top.spf File” on page 51

Preparing Libraries for Post-Layout Mixed-Signal Parasitic Simulation

Ensure that the cells and primitives that you plan to use in a post-layout parasitic simulationhave the following required views and information.

The following sections describe how to prepare some of this information.

Creating an msps View for a Digital Primitive

Each digital primitive must have an msps stopping view, which is required for layout versusschematic (LVS).

To create msps views,

1. In the CIW, choose Tools – Mixed Signal Environment – Prepare Library for MSPS.

Analog cells must have Analog primitives must have

schematic view simulation stopping view

symbol view auLvs view (the default stopping view forauLvs)

layout view (with ivCellType ="graphic" for analog layouts with pins)

CDF simulation information

Digital cells must have Digital primitives must have

symbol view msps view

logic view (verilog, for example) CDF simulation information for LVS

schematic view if you are using the Cadence timing analyzer,an entry in a compiled timing library format

(CTLF) lelayout view (with ivCellType = “graphic” forhierarchical digital blocks)

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The Create msps views & auLvs CDF simInfo form appears.

2. Select the primitives for which you want to create msps views. As described below, youcan either select the primitives manually or select primitives that have certain speciedviews.

Selecting Primitives Manually

To select primitives manually,

1. Choose cells from the Not in the Selected Lis t list box, and click the right-arrow buttonto add them to the In the Selected List list box.

If you want to, you can highlight and move multiple entries.

2. To create an msps view for each cell in the In the Selected List list box, click OK orApply and then click Yes in the create msps views conrmation form.


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Selecting Primitives with Specied Views

To select primitives that have specied views,

1. Click Select Cells.

The Select Cell Views form appears.

2. Change the View Choice List eld as necessary.

The views specied in the View Must Lis t eld and the View Choice List eld becomethe selection criteria for digital primitives. To be selected, a cell must have all the viewsspecied in the View Must Lis t eld and at least one of the views specied in the View Choice List eld.

For example, assume that View Must List contains layout and symbol and that View Choice List contains behavioral and auLvs . Then any cell that has a layout view, a

symbol view, and either a behavioral view or an auLvs view meets the search criteria.3. Click OK or Apply .

The search results appear in the In the Selected Lis t list box on the Create msps views& auLvs CDF simInfo form.

4. In the Create msps views & auLvs CDF simInfo form, click OK or Apply to create anmsps view for each cell in In the Selected List .

5. Conrm your actions by clicking Yes in the create msps views conrmation dialog box.

6. If any of the selected cells have existing auLvs CDF siminfo, the create auLvs Siminfoconrmation dialog box asks you to conrm the overwrite.

Preparing Layout Views for Analog and Digital Cells

In macro mode, the extractor treats any cell with pins as a macro cell and stops expanding it.If a block is an analog block or a hierarchical digital block and requires further expansion, you


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need to add the property ivCellType = "graphic" to the layout master of the block.With this property set, the extractor expands the cell even though pins exist.

You can set the ivCellType property at the instance level or for multiple cells in themacroCellFile . Refer to the Assura Diva Verification Reference for details on eitherof these methods.

For example, the following procedure sets the ivCellType property at the instance level fora cell. With this method, every instance of this cell in the design has the same setting.

1. Open in edit mode the layout view of the instance you want expanded to the transistorlevel.

2. From the Layout window, choose Design – Properties .

The Edit Cellview Properties form appears.3. Click Add .

The Add Property form appears.

4. Type ivCelltype in the Name eld.

5. Set the Type drop-down list box to String .

6. Type graphic in the Value eld.

7. Click OK to add the new property and its value.

Updating View and Stop Lists for LVS

The .simrc le contains the view lists and stop lists for Assura Diva ® LVS. For mixed-signalparasitic simulation, you must update these lists with the msps view before you run LVS.

To update the lists,

1. Open the .simrc le using any editor.

2. Add or update the following variable denitions in the .simrc le so that the msps view

appears at the beginning of each list. For example, after you update the le, thedenitions might look like this:

lvsSchematicViewList ='( "msps" "auLvs""schematic" "symbol")

lvsSchematicStopList ='( "msps" "auLvs")

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lvsLayoutViewList ='( "msps" "auLvs""extracted")

lvsLayoutStopList ='( "msps" "auLvs")

For standard settings for these variables, refer to the Assura Diva Verification Reference .

3. Save the .simrc le.

Preparing to Create the top.spf File

The Cadence timing analyzer uses a standard parasitic format (SPF) le called top.spf ,

which contains the parasitic information for your design. In preparation for creating this le,you must ensure that the property names for resistance and capacitance are set to r and c .

➤ In the CDF Simulation Information section of the presistor or pcapacitor component,specify the resistance and capacitance parameter names as r and c .

Creating mixed_extracted Views

For mixed-signal blocks, the extraction process consists of

1. Verifying consistent pin direction in schematic and layout views

2. Extracting parasitics and creating extracted views

3. (Optional) Creating concice views

4. Comparing the schematic and extracted (or concice) views

5. Creating mixed_extracted views and (optional) using the Cadence timing analyzer togenerate delay calculation les

The mixed_extracted views and the optional SDF les become input to the simulation of thetop-level design.

You can run the extraction process on selected blocks within the design or on the entiredesign.

Verifying Consistent Pin Direction

To verify that pin directions on the schematic and layout views are consistent,

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1. From a window displaying the layout or extracted view, choose Verify – MSPS Check Pins .

The MSPS Check Pins form appears.

2. Click OK .

The CIW displays a list of any discrepancies. Fix them before you extract the parasitics.

Extracting Parasitics and Creating Extracted Views

To extract parasitics and create extracted views,

1. From a window displaying a layout view of the cell, choose Verify – Extract .


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The Extractor form appears.

2. Choose macro cell for Extract Method .

This allows the digital cells to be extracted at the macro level.

Be sure that any analog blocks have the ivCellType property set to graphic . Thisensures that the analog blocks are attened. For more information, see “PreparingLayout Views for Analog and Digital Cells” on page 49 .

3. (Optional) Choose Join Nets With Same Name .

This ensures that nets with the same name are joined automatically.4. Click Set Switches to select the type of parasitics you want extracted.

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The Set Switches form appears. The parasitics displayed vary, depending on theextraction rules le dened for your design. In some cases, you do not need to make anyselection.

To select more than one item, click on your rst selection, then hold down the Controlkey and click on the rest of your selections.

5. Click OK .

The Extractor form reappears with the parasitics you selected in the Switch Names eld.

6. Click OK or Apply to create the extracted views.

A message in the CIW tells you when the extraction process is complete.

Creating Concice Views from Extracted Views

The Assura RC network reducer reduces networks with a large amount of parasitic resistanceand capacitance data into smaller, electrically equivalent networks that you can more easily


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use with analysis tools. If you decide to use concice views, the ow described in this chaptercan accommodate them. However, you should be aware of the following.

In a concice view, all cross-coupling capacitors between analog nets are grounded.When you use a concice view in the ow, you can probe interconnects in the layout viewonly at the terminals.

For detailed information on creating concice views from extracted views, see the ConcICe Help .

Comparing Schematic and Extracted Views

To compare the schematic view with the extracted view created earlier, follow these steps. (To

compare the schematic view with a concice view, follow the same steps but substitute theconcice view for the extracted view.)

1. From a window displaying the extracted view, choose Verify – LVS .

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The LVS form appears. For a detailed description of the elds and buttons, seeAppendix A, “LVS Form Field Descriptions.”


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2. Depending on which views are open, use one of the following procedures to identify theschematic and extracted views that you want to compare.

3. Fill in the names of the rules le and rules library for the Diva LVS rules.

4. Click the Run button near the bottom of the form to begin the comparison.

5. When the comparison nishes, click Info .

The Display Run Information dialog box appears.

6. Click Log File .Scroll through the log le to the netlist comparison section near the end of the le. Thissection identies any mismatches between the two les. Each error is described in thesections following the comparison results.

Not all mismatches are fatal. Look over the comparison results to determine if you needto correct one of the les and redo the extraction and comparison, or if you can proceedwith the views as they are.

If both the schematic and extractedviews are open If only the extracted view is open

1. Click the Sel by Cursor buttonbelow the schematic detail, thenclick the cursor in the openschematic view.

2. Do the same for the extracted view.

1. Click the Sel by Cursor buttonbelow the extracted detail, then clickthe cursor in the open extractedview.

2. Click the Browse button below theschematic detail and select the

schematic view.

Click here.


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7. Choose File – Close Window in the log le window.

8. Click Cancel in the Display Run Information dialog box.

9. Correct any problems in the schematic or extracted views.

10. If necessary, rerun the comparison and compare the results.

Building a Mixed_Extracted View

When the comparison between schematic and extracted views is acceptable, you need toselect the parasitics to use for simulation. You also need to build the mixed_extracted view.

1. In the LVS form, click Build Mixed .

The Build Mixed Extracted View form appears.

2. Verify that the Library , Cell , and View elds correctly specify the conguration view thatyou want to use.

If your design does not have a conguration view associated with it, refer to the Cadence Hierarchy Editor User Guide and create a conguration.

Note: The msps view, used as the digital stopping view for LVS, is also used as theinternal stopping view for SPF generation when the build mixed process runs. Be sure

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the conguration stopping view stops at digital cells that have an msps view.

3. Select one of the following options to specify the analog parasitics that you want to use

for simulation.

4. Ensure that the pearl.cmd and gcfConstraints.gcf les are ready and availablein one of the following locations, which are searched in the order given.

❑ The run directory

❑ Your working directory (where you start icfb or icms )

❑ Your home directory

❑ Your installation path ( $CDS_INST_DIR/tools/dfII/etc/tools/mmsimenv )

For guidance on using the Command and Constraints buttons to view or change these

les, see “Preparing the pearl.cmd and gcfConstraints.gcf Files” on page 37 . When theles are ready, turn on the Calculate button in the Digital Delays section.

Select If you want to

Include All Simulate with all the parasitics that have been extracted

Set From Schematic Select parasitics to include in the simulation by placingspecial symbols (spresistors and spcapacitors) on netsin the schematic view.

The parasitics you select are the only ones included inthe simulation.

The special symbols are available in the sbaLib library.

If you choose Set From Schematic and click OK without identifying any nets on the schematic, theAnalog Parasitics Selective Annotation form asks you toconrm your choice.

None Simulate with none of the parasitics

library_path / cell / view /mixed_extracted/layout_msb

http://-/?-http://-/?-


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If you click OK without editing the pearl.cmd and gcfConstraints.gcf les orwithout ensuring that the les are available in the searched directories, the DelayCalculator Option Files dialog box appears.

5. Click Yes if you want to use the default templates for the option les.

6. To build the mixed_extracted view, click OK in the Build Mixed Extracted View form.

The build mixed process removes all digital parasitics and places them in the SPF le. TheCadence timing analyzer uses the SPF le to calculate the delays and generate an SDF le.The mixed_extracted view contains analog parasitics and analog and digital instances fornetlisting and simulation.

The build mixed process creates or places the following les in the layout_msb directory.

Filename Description

msbCheckFile Timestamp le specifying the SPF creation time

msbEnableFlag Zero-length le that indicates the Cadence timinganalyzer is on, and enables sdfAnnotate

pearl.cmd Command initialization le for the Cadence timinganalyzer

gcfConstraints.gcf File that denes constraints, operating conditions, and

compiled timing library format (CTLF) les used by theCadence timing analyzer

top.spf Detailed SPF le with digital parasitics

top.tmp.sdf SDF le generated by the Cadence timing analyzerdelay calculation


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Modifying the Conguration

To use parasitic simulation, you must specify mixed_extracted as the View To Use for eachcell in your top-level design for which you want the extracted parasitics simulated. To specifymixed_extracted as the View To Use, you modify the conguration for your top-level design.

If your design does not have a conguration, refer to the Cadence Hierarchy Editor User Guide to create one.

To modify a conguration,

1. Open the Hierarchy Editor and specify the conguration for your top-level design.

2. Use one of the following methods to specify the mixed_extracted view for the cells orblocks for which you want parasitics simulated.

3. Choose View – Update to recongure the design to reect your changes.

4. To save the conguration with your changes, choose File – Save .

annotate.com File that contains a $sdf_annotate command with thelocation of the top.sdf le

runPearl.log Error and log le

To specify views for individual blocks To specify views for multiple blocks

1. In the Instance Binding section ofthe Hierarchy Editor window,position the cursor in the View To Use column of the appropriateblock.

2. Press the right mouse key to displaya list of commands.

3. Choose Select View to display thelist of views for this block.

4. Select mixed_extracted as theview for this block to update theView Found and View To Use elds.

1. Addmixed_extract ed as therst view in the Global Bindings View List text eld. This ensuresthat the mixed_extracted view is theselected view for every cell that hasa mixed_extracted view.

Filename Description

http://%24hiereditor.pdf/


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5. To close the Hierarchy Editor, choose File – Exit .

Partitioning is done automatically by comparing the Global Bindings Stop List eld and the

Analog and Digital Stop View Sets.

Setting the Mixed-Signal Simulation Options

To set up the Mixed Signal Options form for post-layout delay calculations,

1. Choose Simulation – Options – Mixed Signal in the Analog Design EnvironmentSimulation window.

The Mixed Signal Options form appears.

2. If necessary, set the DC Interval and Max DC Iterations .

For information on these elds, see Cadence Mixed-Signal Circuit Design Environment User Guide .

3. Click the Use Existing (Layout) radio button.

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The form expands to allow you to use SDF les created during the build mixed processand to import SDF les.

4. To use the SDF les created during the build mixed process, turn on the SDF From Mixed Extracted View button.

5. To import SDF les created by a different tool, turn on the Import SDF Files button andll in the associated elds.

❑ In the File eld, type the path to and lename of the SDF le that you want to import.The name you enter must be a legal Verilog ® language name.

❑ In the Scope eld, type the hierarchical scope of the instance for which the delayle is to be annotated during simulation. For example, you might type something likeI1/I3 to indicate an instance one level down in the hierarchy.

6. If you want to import more SDF les, click the Import More button and ll in the Import

SDF Files form as described in “Importing Additional SDF Files” on page 64 .

http://-/?-http://-/?-


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Importing Additional SDF Files

The Mixed Signal Options form provides space for you to enter the name of one SDF le to

be imported. If you want to import more than one SDF le, click the Import More button toopen the Import SDF Files form.

To use the form,1. Type a number from 2 to 10 in the Number of Additional Files To Import eld.

The form expands to accommodate the information that you want to enter.

2. For each additional le, type the name of the SDF le to be imported.

3. For each additional le, type the hierarchical scope of the instance for which the delayle is to be annotated during simulation.

Simulating a Design (Post-Layout)

After you set up the conguration for the parasitic cells, you are ready to simulate thecongured schematic using one of the mixed-signal simulators. Follow the standard mixed-signal simulation process.


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Probing Parasitic Values

Although it is not required, you might want to probe the instances of parasitic components.

To probe parasitic values in the schematic or extracted views,

1. In the LVS form, click the Parasitic Probe button.

The Parasitic Probing form appears.

2. In the Max list size eld, specify how many parasitic instances to display.

3. Sort parasitics by resistance or capacitance by selecting R or C .

4. Click the appropriate button to specify the parasitics to be collected.

❑ Click Whole Net and then click on a net in the schematic or extracted view to displayan ordered list of all the parasitics on the net. The largest resistances orcapacitances appear at the top of the list.

❑ Click Point to Point and then click on two pins or instance pins in the schematic orextracted view to collect all the parasitics between two points.

❑ If the points are on the same net, both resistances and capacitances are collected.If the points are on different nets, only capacitances are collected.

❑ Click Net to Net and then click on two nets in the schematic or extracted view tocollect parasitic capacitances between two different nets.


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A list of the collected parasitic instances appears.

Select an instance from this list to highlight the component symbol associated with thisparasitic on the extracted view.

5. To backannotate the resistances and capacitances to the schematic view, click theBackannotate button on the LVS form.

The Parasitic Backannotation form appears.

6. Select the font size and label placement that you want and click the Add Parasitics button.


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Resistance and capacitance labels appear on the schematic view. To see them, youmight need to zoom in on a portion of the schematic. The new information displayed onthe schematic is for viewing only. Using the Add Parasitics button does not include theparasitics in the schematic.

7. To remove these labels, click the Remove Parasitics button.

8. To write all of the lumped parasitics to a le, click Print All .

The Print All Parasitics form appears:

9. Click the appropriate Sort parasitics by button.

Select R for a list sorted by resistance. Select C for a list sorted by capacitance.

10. Specify the lename for the printed listing.

Even though you are simulating from the mixed_extracted view of the design, you can probesignals from the schematic view. This is called out-of-context probing. You can also probe themixed_extracted view directly for analog and mixed nets.

Important

When you probe different types of signals (analog, digital, or mixed), keep in mindwhich nets really exist in the mixed_extracted view. Probing a net or a terminal at alevel of the schematic that does not have a simulation waveform causes a probingerror.

Because analog components are at in the mixed_extracted view, you cannot probe netsconnected to terminals of hierarchical analog blocks. You must descend to the transistorlevel of the schematic to probe these nets. It is only at the transistor level that the programcan map terminals from the schematic to the mixed_extracted view.


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To probe a signal, click on the wire at a point close to the terminal. The probe automatically jumps to the closest terminal on that net. An X appears on the selected terminal as shown inthe following gure.

You can select several terminals on the same net. Each selected terminal is marked with adifferent color X. The associated waveform displays in the same color as the X on theschematic.

You can select and probe only real geometries from a mixed_extracted view. For example, ifthe metal layer is broken up into resistors, the geometries do not have connectivity. In thiscase, you need to probe the metal layer at contacts and vias.

If you are unable to select a geometry on the mixed_extracted view, the layer might be invalid.Set valid layers from the Edit menu of the LSW form.

If you probe a net that cannot be mapped to a terminal in the mixed_extracted view, warnings

similar to the following appear:*WARNING* Could not obtain the external name

*WARNING* Unable to map net 'VBG'

*Warning* no valid full path name for net "VBG", selection not taken


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You can probe mixed-nets connected to terminals of hierarchical analog blocks near thedigital terminal, but not near analog terminals, as shown in the following gure.

The D2A and A2D elements are attached to the digital components in the netlist. The outputof the D2A element or the input of the A2D element, therefore, is a valid analog net in theextracted view.

Because digital parasitics are removed from the mixed_extracted view, digital nets can beprobed anywhere and do not have to be associated with terminals. An X is placed in themiddle of the net indicating its selection.

D2A A2D

Do not probe here.

Probe here.

In the netlistIn the netlist

Analog Block

Analog Block

Actual nets being probed


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3Diva Flow: Working Through an ExtendedDesign Example

The three sections of this design example provide an overview of the front-to-back mixed-signal simulation ow for the Cadence ® Analog Design Environment (ADE) 5.0. The circuit

used throughout this design example is a counter-controlled A/D converter (ccadc). Thecircuit simulator used is spectreVerilog. For more information on mixed-signal simulation,refer to the Cadence Mixed-Signal Circuit Design Environment User Guide .

The three sections of this example are

“Simulating with Schematic Data” on page 72

“Simulating with Analog Parasitics and Estimated Digital Delays” on page 88

“Simulating with Analog and Digital Parasitics” on page 114

Before you can follow the steps in these sections, you need to prepare the libraries and startthe tools that are used.

1. Copy the mixed-signal design example les to your home directory by typing thefollowing at the command prompt:cp -r your_inst_dir /tools/dfII/samples/artist/mixSig/msps

2. Change directories ( cd ) to msps .

3. Extract the sample mixed-signal library les for use in this design example. Type thefollowing at the command prompt:tar xvf mixSigLib.t

4. To start the Cadence software and enter the mixed-signal simulation environment, typethe following at the command prompt:icfb &

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Cadence Parasitic Simulation User GuideDiva Flow: Working Through an Extended Design Example


The command interpreter window (CIW) appears.

Note: If the icfb command does not work, contact your Cadence system administrator forassistance.

Simulating with Schematic Data

In this section, you run a simulation using mixed-signal hierarchical netlisting (MHNL) andschematic data only (no layout data). The tasks to perform are summarized here, and thesteps to complete them follow.

Conguring and partitioning the design

Simulating the design

Plotting and saving results

Conguring and Partitioning the Design

A conguration le denes the cell and instance view selections for netlisting and simulation.The mixed-signal partitioner uses the conguration le and congured schematic to provideexpansion information for your design.

Creating a Conguration File

In the following steps, you use the hierarchy editor to create a conguration le—or config view —for the tutorial schematic.

1. From the CIW, choose Tools – Librar y Manager .


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Cadence Parasitic Simulation User GuideDiva Flow: Workin