Sigma-Delta Fractional-N Frequency Synthesis

Scott MeningerMichael Perrott

Massachusetts Institute of TechnologyJune 7, 2004

Copyright © 2004 by Michael H. PerrottAll rights reserved.

Note: Much of this material is taken from MITOpenCourseWare

http://ocw.mit.eduCourse: 6.976

Outline

Integer-N synthesis- Bandwidth constraints

Fractional-N synthesis- Issue of fractional spursΣ∆ Fractional-N Synthesis- Quantization noise impact on the PLL

Recent developments for lowering the impact of quantization noiseConclusionsQ&A

Bandwidth Constraints for Integer-N Synthesizers

PFD LoopFilter(1/T = 20 MHz)

ref(t) out(t)

N[k]

Divider

1/T Loop FilterBandwidth << 1/T

PFD output has a periodicity of 1/T- 1/T = reference frequency

Loop filter must have a bandwidth << 1/T- PFD output pulses must be filtered out and average value

extracted

Closed loop PLL bandwidth often chosen to be afactor of ten lower than 1/T

Bandwidth Versus Frequency Resolution

PFD LoopFilter

1.80 1.82 GHz

(1/T = 20 MHz)ref(t) out(t)

out(t)

Sout(f)

N[k]

N[k]9091

Divider

frequency resolution = 1/T

1/T

1/T Loop FilterBandwidth << 1/T

Frequency resolution set by reference frequency (1/T)- Higher resolution achieved by lowering 1/T

Increasing Resolution in Integer-N Synthesizers

PFD LoopFilter

1.80 1.8002 GHz

(1/T = 200 kHz)ref(t) out(t)

out(t)

Sout(f)

N[k]

N[k]90009001

Divider

frequency resolution = 1/T

1/T

1/T Loop FilterBandwidth << 1/T

10020 MHz

Use a reference divider to achieve lower 1/T- Leads to a low PLL bandwidth ( < 20 kHz here )

The Issue of Noise

PFD LoopFilter

1.80 1.8002 GHz

(1/T = 200 kHz)ref(t) out(t)

out(t)

Sout(f)

N[k]

N[k]90009001

Divider

frequency resolution = 1/T

1/T

1/T Loop FilterBandwidth << 1/T

10020 MHz

Lower 1/T leads to higher divide value- Increases PFD noise at synthesizer output

Background: Classical Linearized PLL Model

Φdiv[k]

Φref [k] KV

jf

v(t) Φout(t)H(f)

1N

�πα e(t)

Φvn(t)en(t)

Icp

VCO-referredNoise

f0

SEn(f)

PFD-referredNoise

1/T f0

SΦvn(f)

-20 dB/dec

PFDChargePump

LoopFilterDivider

VCO

N[k]

Classical PLL model- Predicts impact of PFD and VCO referred noise sources- Does not allow straightforward modeling of impact due

to dynamic divide value variationsMore on this shortly …

Background: Classical Linearized PLL Model

Φdiv[k]

Φref [k] KV

jf

v(t) Φout(t)H(f)

1N

�πα e(t)

Φvn(t)en(t)

Icp

VCO-referredNoise

f0

SEn(f)

PFD-referredNoise

1/T f0

SΦvn(f)

-20 dB/dec

PFDChargePump

LoopFilterDivider

VCO

N[k]

Parameterizing in terms of G(f) helps visualize the nature (high-pass or low-pass) and gain of the noise transfer functions

Parameterized Version of Classical Model

Φvn(t)en(t)

Φout(t)Φc(t)

Φn(t)

Φnvco(t)Φnpfd(t)

fo1-G(f)

foG(f)

2πNα

VCO-referredNoise

f0

SEn(f)

PFD-referredNoise

1/T f0

SΦvn

(f)

-20 dB/dec

Divider Control

of Frequency Setting

(assume noiseless for now)

G(f) represents the PLL closed loop dynamicsG(f) is low-passNature of noise transfer very easily seen from the parameterized model

Modeling PFD Noise Multiplication

PFD spectral density multiplied by N2 before influencing PLL output phase noise

Φvn(t)en(t)

Φout(t)Φc(t)Φn(t)

Φnvco(t)Φnpfd(t)

fo1-G(f)

foG(f)�πNα

VCO-referredNoise

f0

SEn(f)

PFD-referredNoise

1/T f0

SΦvn(f)

-20 dB/dec

Divider Controlof Frequency Setting

(assume noiseless for now)

Sen(f)�πNα

2

Rad

ians

2 /Hz

SΦvn(f)

f(fo)opt0

Rad

ians

2 /Hz SΦnpfd(f)

SΦnvco(f)

f(fo)opt0

High divide values high phase noise at low frequencies

Fractional-N Frequency Synthesizers

Break constraint that divide value be integer- Dither divide value dynamically to achieve fractional values- Frequency resolution is now arbitrary regardless of 1/T

Want high 1/T to allow a high PLL bandwidth

DitheringModulator

PFD LoopFilter

1.80 1.82 GHz

(1/T = 20 MHz)ref(t) out(t)

out(t)

Sout(f)

N[k]Nsd[k]

Nsd[k]90

90

91

91Divider

frequency resolution << 1/T

1/T

Classical Fractional-N Synthesizer Architecture

1-bit

PFD LoopFilter

ref(t)

div(t)

out(t)

frac[k]Accumulator

N/N+1

carry_out[k]

e(t)

Nsd[k] = N + frac[k]

Use an accumulator to perform dithering operation- Fractional input value fed into accumulator- Carry out bit of accumulator fed into divider

Accumulator Operation

residue[k]

carry_out[k]

frac[k] =.25

1-bitM-bit

M-bitfrac[k]

Accumulatorcarry_out[k]

residue[k]

clk(t)

Carry out bit is asserted when accumulator residue reaches or surpasses its full scale value- Accumulator residue increments by input fractional

value each clock cycle

Fractional-N Synthesizer Signals with N = 4.25

phase error(t)

carry_out(t)

out(t)

div(t)

ref(t)

e(t)

Divide value set at N = 4 most of the time - Resulting frequency offset causes phase error to

accumulate- Reset phase error by “swallowing” a VCO cycle

Achieved by dividing by 5 every 4 reference cycles

The Issue of Spurious Tones

1-bit

PFD LoopFilter

ref(t)

div(t)

out(t)

frac[k]Accumulator

N/N+1

carry_out[k]

e(t)

Nsd[k] = N + frac[k]

PFD error is periodic- Note that actual PFD waveform is series of pulses – the

sawtooth waveform represents pulse width values over timePeriodic error signal creates spurious tones in synthesizer output- Ruins noise performance of synthesizer

The Phase Interpolation Technique

1-bitM-bit

M-bit

PFD LoopFilter

ref(t)

div(t)

out(t)

frac[k]Accumulator

N/N+1

carry_out[k]

e(t)

D/A

residue[k]

α

Phase error due to fractional technique is predicted by the instantaneous residue of the accumulator- Cancel out phase error based on accumulator residue

The Problem With Phase Interpolation

1-bitM-bit

M-bit

PFD LoopFilter

ref(t)

div(t)

out(t)

frac[k]Accumulator

N/N+1

carry_out[k]

e(t)

D/A

residue[k]

α

Gain matching between PFD error and scaled D/A output must be extremely precise- Any mismatch will lead to spurious tones at PLL output

Is There a Better Way?

A Better Dithering Method: Sigma-Delta Modulation

M-bit Input 1-bitD/A

Analog Output

Input

QuantizationNoise

Digital InputSpectrum

Analog OutputSpectrum

Time Domain

Frequency Domain

Σ−∆

Digital Σ−∆Modulator

Sigma-Delta dithers in a manner such that resulting quantization noise is “shaped” to high frequencies

Dither

The sigma-delta noise shaping analysis assumes a white quantization noise spectrumIn order to make the input look “sufficiently exciting” a dither signal can be added to itDithering methods are directly taken from sigma-delta ADC and DAC design- This makes sense since the synthesizer is really a DAC

(digital to phase)- Most common method is to add a random sequence to

the LSB’s of the input

Sigma-Delta Frequency Synthesizers

PFD ChargePump

Nsd[m]

out(t)e(t)

Σ−∆Modulator

v(t)

N[m]

LoopFilter

DividerVCO

ref(t)

div(t)

MM+1

Fout = M.F Fref

f

Σ−∆Quantization

Noise

Fref

Riley et. al.,JSSC, May 1993

Use Sigma-Delta modulator rather than accumulator to perform dithering operation- Achieves much better spurious performance than

classical fractional-N approach

Summary: Sources of Phase Noise in Σ∆ Synthesis

Charge-pump / Phase Detector / Reference- Low-pass filtered by PLL, dominant at low offset frequencies

VCO- High-pass filtered by PLL, dominant at high offset frequenciesΣ∆ dithered quantization noise- Low-pass filtered by PLL, noise/bandwidth tradeoff exists

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

Frequency

Spe

ctra

l Den

sity

(dB

c/H

z)

f0 1/T

10 kHz 100 kHz 1 MHz 10 MHz

PFD-referrednoise

SΦout,En(f)

VCO-referred noise

SΦout,vn(f)

Σ−∆noise

SΦout,∆Σ(f)

fo = 84 kHz

Digital Σ∆ N[k]Σ∆ Noise

InSynth Output

fc

Parasitic

Pole

A quick note on the linearized model

Non-linearities break the assumptions of the linear model - The shaped noise can be “folded down” to lower

frequencies due to non-linearities in the synthesizer PFD/Charge-pump design

This process is best seen through behavioral simulation

Digital Σ∆ N[k]Σ∆ Noise

InSynth Output

fc

Parasitic

Pole

A Well Designed Sigma-Delta Synthesizer

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

Frequency

Spe

ctra

l Den

sity

(dB

c/H

z)

f0 1/T

10 kHz 100 kHz 1 MHz 10 MHz

PFD-referrednoise

SΦout,En(f)

VCO-referred noise

SΦout,vn(f)

Σ−∆noise

SΦout,∆Σ(f)

fo = 84 kHz

Order of G(f) is set to equal to the Sigma-Delta order- Sigma-Delta noise falls at -20 dB/dec above G(f) bandwidth

Bandwidth of G(f) is set low enough such that synthesizer noise is dominated by intrinsic PFD and VCO noise

Impact of Increased PLL Bandwidth

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

Frequency

Spe

ctra

l Den

sity

(dB

c/H

z)

f0 1/T

10 kHz 100 kHz 1 MHz 10 MHz

PFD-referrednoise

SΦout,En(f)

VCO-referred noise

SΦout,vn(f)

Σ−∆noise

SΦout,∆Σ(f)

f0 1/T

10 kHz 100 kHz 1 MHz 10 MHz

Frequency

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

Spe

ctra

l Den

sity

(dB

c/H

z)

PFD-referrednoise

SΦout,En(f)

VCO-referred noise

SΦout,vn(f)

Σ−∆noise

SΦout,∆Σ(f)

fo = 84 kHz fo = 160 kHz

Allows more PFD noise to pass throughAllows more Sigma-Delta noise to pass throughIncreases suppression of VCO noise

3 GHz/1.2GHz