8/3/2019 Pen Ti Um Pro

http://slidepdf.com/reader/full/pen-ti-um-pro 1/11

05/05/12 1

Pentium Pro Processor Overview

Elijah W. Bass December 6, 2000

8/3/2019 Pen Ti Um Pro

http://slidepdf.com/reader/full/pen-ti-um-pro 2/11

05/05/12 2

Pentium Pro Roadmap

• Pentium Pro Overview• Instruction Set Format

• Process Stages• Processing Units• Branch Prediction

• Pentium Pro/II Performance• Pentium Pro/II Cache Performance

8/3/2019 Pen Ti Um Pro

http://slidepdf.com/reader/full/pen-ti-um-pro 3/11

05/05/12 3

Pentium Pro Overview• The main goal in the design of the P6 family micro-

architecture was to exceed the Pentium processor performance while utilizing the existing 0.6-micrometer,

four-layer, metal BICMOL manufacturing process.• The Pentium Pro processor has a three-way superscalar

architecture, permitting the execution of up to threeinstructions per clock cycle.

• The P6 superscalar implementation has dynamic executioni.e. micro-data flow analysis, out-of-order execution,superior branch prediction, and speculative execution.Object code is decoded by three instruction decode unitsworking in parallel.

8/3/2019 Pen Ti Um Pro

http://slidepdf.com/reader/full/pen-ti-um-pro 4/11

05/05/12 4

Pentium Pro Instruction Set

Format

• Pentium Pro executes the x86 CISC set• Pentium Pro decodes and translates each Intel

x86 instruction into micro-operations• The Pentium Pro processes instructions in three

stages

8/3/2019 Pen Ti Um Pro

http://slidepdf.com/reader/full/pen-ti-um-pro 5/11

05/05/12 5

Pentium Pro Process Stages • The first stage consists of the instruction begin

fetched, decoded, and converted into micro-ops• Reservation station (RS) is the buffer between the

first and second stages• The second stage consists of the micro-operations

being executed in the out-of-order core• The third stage retires the micro-operations in

original program order • Completed micro-operations wait in the reorder

buffer until all of the preceding instructions have been retired

8/3/2019 Pen Ti Um Pro

http://slidepdf.com/reader/full/pen-ti-um-pro 6/11

05/05/12 6

Pentium Pro Processing Units• P Pro micro-

architecture pipeline isdivided into four

sections – 8K L1 caches – 256KB, 512KB, 1MB,

or 2MB L2 caches

– the front end, – the out-of-orderexecution core

– the retire section

8/3/2019 Pen Ti Um Pro

http://slidepdf.com/reader/full/pen-ti-um-pro 7/11

05/05/12 7

P Pro Branch Prediction

• Predicted to jump the nexttime if the counter is in state 2

or 3• Predicted to not jump if in

state 0 or 1• P Pro branch prediction

mechanism can learn torecognize repetitive patterns

8/3/2019 Pen Ti Um Pro

http://slidepdf.com/reader/full/pen-ti-um-pro 8/11

05/05/12 8

Pentium Pro/II Performance

• The Pentium II L2 cache utilizes standardcommodity SRAM

• The faster core frequencies and larger PentiumII L1 cache size often compensate for theslower L2 cache speed

8/3/2019 Pen Ti Um Pro

http://slidepdf.com/reader/full/pen-ti-um-pro 9/11

05/05/12 9

Pentium Pro/II Cache

Performance• P II L2 Cache is located

off the processor die

• P II L2 Cache operatesat ½ core frequency

• P II cacheability limit is512 MB

• P Pro cacheability limitis 4 GB

8/3/2019 Pen Ti Um Pro

http://slidepdf.com/reader/full/pen-ti-um-pro 10/11

05/05/12 10

Pentium Pro/II Memory Access

• Pentium Pro 200/256 out perform P II 233/512• Pentium Pro 200/1024 performs similar to P II 266/512

8/3/2019 Pen Ti Um Pro

http://slidepdf.com/reader/full/pen-ti-um-pro 11/11

05/05/12 11

Pentium Pro/II Applicability

• P II outperform P Pro in CPU intensive apps• P Pro outperform PII in memory intensive apps