Philips 37pfl7605h Ch q552.1e-La

8/11/2019 Philips 37pfl7605h Ch q552.1e-La

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Colour Television Chassis

Q552.1ELA

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Contents Page Contents Page1. Revision List 2

2. Technical Specifications, Diversity, and Connections2

3. Precaut ions, Notes, and Abbreviat ion List 6

4. Mechanical Instructions 10

5. Service Modes, Error Codes, and Fault Finding 23

6. Alignments 41

7. Circuit Descriptions 47

8. IC Data Sheets 60

9. Block Diagrams

Wiring diagram Rembrandt 32" 77Wiring diagram Rembrandt 37" - 42" 78

Wiring diagram Van Gogh 32" - 40" 79

Wiring diagram Matisse 32" 80

Wiring Matisse 40" 81

Block Diagram Video 82

Block Diagram Audio 83

Block D iagram Control & C lock S igna ls 84

Block Diagram I2C 85

Supply Lines Overview 86

10. Circuit Diagrams and PWB Layouts Drawing PWB

AL1 820400089786 AmbiLigh t Common 87 94

AL2 820400089773 3 LED LiteOn 89 94

AL1 820400089691 9 LED LiteOn 90 94

AL1 820400089703 15 LED LiteOn 92 94

AL1 820400090592 AmbiLigh t Common 95 102

B06 820400089962 LVDS DVBS 138

B06 820400089572 LVDS Non DVBS 142

B07 820400089602 DVBS FE 146

B08 820400089624 DVBS Supply 147

B09 820400089822 DVBS Con. 149

B09 820400089812 Non DVBS Con. 150

B11 820400090693 TCON LGD 151

B11 820400090704 TCON LGD 155

B13 820400090732 TCON AL CPLD 159

B13 820400090742 TCON AL CPLD 160B14 820400090714 TCON SHARP 161

B14 820400090724 TCON SHARP 167

310431363643 SSB Layout 173

310431364003 SSB Layout 175

310431364025 SSB Layout 177

310431364064 SSB Layout 179

11. Styling Sheets

Rembrandt 32" 181

Rembrandt 37" & 42" 182

Van Gogh 32" - 52" 183

Matisse 32" - 46" 184


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http://www.p4c.philips.com/cgi-bin/dcbint/cpindex.pl?ctn=32PFL5605H/12&dct=PSS&scy=GBhttp://www.p4c.philips.com/cgi-bin/dcbint/cpindex.pl?ctn=32PFL5605H/05&dct=PSS&scy=GBhttp://www.p4c.philips.com/cgi-bin/dcbint/cpindex.pl?ctn=32PFL5405H/60&dct=PSS&scy=GBhttp://www.p4c.philips.com/cgi-bin/dcbint/cpindex.pl?ctn=32PFL5405H/05&dct=PSS&scy=GBhttp://www.p4c.philips.com/cgi-bin/dcbint/cpindex.pl?ctn=32PFL5605H/60&dct=PSS&scy=GBhttp://www.p4c.philips.com/cgi-bin/dcbint/cpindex.pl?ctn=40PFL5605H/12&dct=PSS&scy=GBhttp://www.p4c.philips.com/cgi-bin/dcbint/cpindex.pl?ctn=40PFL5605H/05&dct=PSS&scy=GBhttp://www.p4c.philips.com/cgi-bin/dcbint/cpindex.pl?ctn=37PFL5405H/12&dct=PSS&scy=GBhttp://www.p4c.philips.com/cgi-bin/dcbint/cpindex.pl?ctn=37PFL5405H/05&dct=PSS&scy=GBhttp://www.p4c.philips.com/cgi-bin/dcbint/cpindex.pl?ctn=32PFL7605H/12&dct=PSS&scy=GBhttp://www.p4c.philips.com/cgi-bin/dcbint/cpindex.pl?ctn=32PFL7605H/05&dct=PSS&scy=GB


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Technical Specifications, Diversity, and Connections EN3Q552.1E LA 2.

2.3 Connections

Figure 2-1 Connection overview

Note:The following connector colour abbreviations are used

(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=

Grey, Rd= Red, Wh= White, Ye= Yellow.

2.3.1 Side Connections

1 - SD-Card: Secure Digital Card - In/Out (optional)

4 -Vdd Supply

5 -CLOCK S igna l

6 - G ND2 Gnd

7 -DAT0/D0 Signal

8 -DAT1/IRQ Signal 9 -DAT2/NC Signal

10 -CD Signal

11 -GND Gnd

12 -WP Signal

13 -GND Gnd 14 GND Gnd

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10 11 1212 13 14 15 16

5 6 7 8 9

1

2

3

4

12WP

14GND


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Technical Specifications, Diversity, and Connections EN5Q552.1E LA 2.

16 - VGA: Video RGB - In

Figure 2-8 VGA Connector

1 -V ideo Red 0 .7 VPP/ 75 ohm

2 -Video Green 0.7 VPP/ 75 ohm 3 -Video Blue 0.7 VPP/ 75 ohm

4 - n.c.

5 -Ground Gnd

6 -Ground Red Gnd

7 -Ground Green Gnd

8 -Ground Blue Gnd

9 - +5VDC +5 V

10 - Ground Sync Gnd 11 -n .c.

12 - DDC_SDA DDC data

13 -H-sync 0 - 5 V 14 -V-sync 0 - 5 V

15 - DDC_SCL DDC clock

2.4 Chassis Overview

Refer to chapter Block Diagramsfor PWB/CBA locations.

1

610

11

5

15

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http://www.atyourservice-magazine.com/


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Mechanical InstructionsEN 10 Q552.1E LA4.

4. Mechanical Instructions

Index of this chapter:

4.1 Cable Dressing Rembrandt series

4.2 Cable Dressing Van Gogh styling

4.3 Cable Dressing Matisse styling

4.4 Service Positions

4.5 Assy/Panel Removal Rembrandt Styling

4.6 Assy/Panel Removal Van Gogh Styling4.7 Assy/Panel Removal Matisse Styling

4.8 Set Re-assembly

Notes:

Figures below can deviate slightly from the actual situation,

due to the different set executions.

4.1 Cable Dressing Rembrandt series


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Mechanical Instructions EN 11Q552.1E LA 4.

Figure 4-2 Cable dressing 37PFL5405H/xx

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Mechanical InstructionsEN12 Q552.1E LA4.

4.2 Cable Dressing Van Gogh styling


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Mechanical Instructions EN13Q552.1E LA 4.

Figure 4-6 Cable dressing 40PFL5605H/xx with DVB-S

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4.3 Cable Dressing Matisse styling


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4.4 Service Positions

For easy servicing of a TV set, the set should be put face down

on a soft flat surface, foam buffers or other specific workshop

tools. Ensure that a stable situation is created to perform

measurements and alignments. When using foam bars take

care that these always support the cabinet and neveronly the

display. Caution:Failure to follow these guidelines can

seriously damage the display!

Ensure that ESD safe measures are taken.

4.5 Assy/Panel Removal Rembrandt Styling

The instructions apply to the 42PFL5405H/xx.

4.5.1 Rear Cover

With the Rembrandt styling, a new concept of housing has

been introduced, having consequences for Service when

opening the set.

Part of the back cover now forms one assy with the LCD panel

and will be swapped together with this panel. For opening theset, only remove the smaller part of the rear cover as

described below!

Warning!

The snaps on the backside of the LCD Panel secure the

backlight units and should never be released!Release

destroys the LCD Panel and voids warranty.

Refer to Figure 4-18for details.

Warning:Disconnect the mains power cord before you remove

the rear cover.

Note:it is notnecessary to remove the stand while removing

the rear cover.


The stand and -subframe do notneed to be removed for

removing the central subwoofer.

When defective, replace the whole unit.

4.5.3 Mains Switch

The mains switch is mounted on the front bezel with one screw.

4.5.4 Main Power Supply

Refer to Figure 4-10and Figure 4-11for details.

Figure 4-10 Main Power Supply

Figure 4-11 Main Power Supply - back shielding

1

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2

2

22

2

2

2

2 1

1

1

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4.5.5 Small Signal Board (SSB)


Figure 4-12 SSB

Figure 4-13 SSB - back shielding

1. Unplug all connectors [1] and [2].

2. Remove the fixation screws [3].

3. Take the board out.When defective, replace the whole unit.

When remounting, ensure that the back shielding plate is

positioned correctly.

4.5.6 Front Bezel


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12

3

3

3

33

3

3

3

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33333

3

3

3

3

3


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Figure 4-15 IR & LED board

1. Detach the front bezel from the set as earlier described.

2. Release the clips [1] that secure the IR & LED board in the

bezel and take the board out.

3. Unplug the connectors.


4.5.8 Keyboard Control Board


Figure 4-16 Keyboard Control board

1. Detach the front bezel from the set as earlier described.

2. Unplug the connector [1].

3. Release the clips that secure the board [2] and take the

board out.


4.5.9 LCD Panel


Figure 4-17 LCD board -1-

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1

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1

2

3

2

2

3

3 3

2


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Figure 4-18 LCD board -2-

Warning!

The snaps on the backside of the LCD Panel secure the

backlight units and should never be released!

1. Remove the tweeters as earlier described.

2. Remove the central subwoofer as earlier described.

3. Remove the mains switch as earlier described.

4. Remove the Main Power Supply board as earlier

described, together with its back shielding.

5. Remove the Small Signal Board as earlier described,

together with its back shielding.

6. Remove the cable from the clamp [1].

7. Remove the stand [2] together with its subframe [3].

8. Detach the front bezel together with the IR & LED board

and Keyboard Control board as earlier described.

9. Ensure all (sub-) frames, boards and cables that do not

belong to the LCD panel are removed before sending the

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Do not releaseo not rele e


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4.6 Assy/Panel Removal Van Gogh Styling

The instructions apply to the 46PFL5605H/xx.

4.6.1 Rear Cover

Warning:Disconnect the mains power cord before you remove

the rear cover.

Note:it is notnecessary to remove the stand while removing

the rear cover.

1. Remove all screws of the rear cover.

2. Lift the rear cover from the TV. Make sure that wires and

flat coils are not damaged while lifting the rear cover from

the set.

Special note for 40" sets

Refer to Figure 4-19to Figure 4-22for details.

Figure 4-19 Rear cover 40" -1-



1. Lift the rear cover on the bottom [1].

2. Push back the cover [2] to unlock the catches.

3. If the rear cover catches still lock, place a flat screwdriver

between flare and rear cover and turn it until the rear cover

and the flare are disassembled from the catch.

4. The location of the catches are indicated with [1], [2], [3]

and [4].

4.6.2 Speakers

Tweeters

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11

2

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24232221


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4.6.3 Main Power Supply


Figure 4-23 Main Power Supply

1. Unplug all connectors [1].

2. Remove the fixation screws [2].

3. Take the board out.


4.6.4 Small Signal Board (SSB)


Figure 4-25 IR & LED Board -1-


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1

1

1

2

2

2

2

2

2

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2

1

3

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3

3

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1. Remove the stand [1].

2. Remove the IR & LED board cover [2].

3. Release the clips [3] that secure the IR & LED board.

4. Remove the connectors [4] on the IR/LED board.

4.6.7 Keyboard Control Board


Figure 4-28 Keyboard Control board

1. Unplug the connector on the IR & LED board that leads to

the Keyboard Control board as earlier described.

2. Release the cable from its clamps.

3. Release the clip on top of the unit [1] and take the unit out.

When defective replace the whole unit

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4

33

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1


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Figure 4-29 LCD Panel

4.7 Assy/Panel Removal Matisse Styling

The Matisse styling is similar to the Van Gogh styling. No

detailed information is available at time of publishing.

4.8 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse

order.

Notes:

While re-assembling, make sure that all cables are placed

and connected in their original position.

Pay special attention not to damage the EMC foams in the

set. Ensure that EMC foams are mounted correctly.

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1

1

1

1

1

22

22

22

1

1

1

1

1

2

44 4 4 4 4

3

3

43

44

43

4

3

4

3

4

4


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Service Modes Error Codes and Fault FindingEN 26 Q552 1E LA5


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Service Modes, Error Codes, and Fault FindingEN26 Q552.1E LA5.

5.3 Stepwise Start-up

When the TV is in a protection state due to an error detected by

stand-by software (error blinking is displayed) andSDM is

activated via shortcutting the SDM solder path on the SSB, the

TV starts up until it reaches the situation just before protection.

So, this is a kind of automatic stepwise start-up. In combination

with the start-up diagrams below, you can see which supplies

are present at a certain moment. Caution: in case the start-up

in this mode with a faulty FET 7U0X is done, you can destroyall ICs supplied by the +1V8 and +1v1, due to overvoltage (12V

on XVX-line). It is recommended to measure first the FET

7U0X or others FETs on shortcircuit before activating SDM via

the service pads.

The abbreviations SP and MP in the fig ures stand for:

SP: protection or error detected by the Stand-by

Processor.

MP: protection or error detected by the MIPS Main

Processor.

ActiveSemi

St bySt by

Mainson

Mains

off

GoToProtection

- WakeUp requested

- Acquisition needed- Tact switch pushed

-stby requested andno dataAcquisitionrequired

-St by requested- tact SW pushed

WakeUp

requested

WakeUprequested

(SDM)

GoToProtection

Hibernate

- Tact switch pushed- last statusishibernate

after mainsON

Tact switchpushed

Service Modes, Error Codes, and Fault Finding EN 27Q552.1E LA 5.


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Service Modes, Error Codes, and Fault Finding EN27Q552.1E LA 5.

No

EJTAG probeconnected ?

No

Yes

Cold boot?No

Set IC slave addressof Standby P to (A0h)

An EJTAG probe (e.g. WindPower ICE probe) can beconnected for Linux Kernel debugging purposes.

Detect EJTAG debug probe(pulling pin of the probe interface toground by inserting EJTAG probe)

Off

Standby Supply startsrunning.All standby supply voltagesbecome available.

st-by P resets

Stand by orProtection

Mainsisapplied

-Switch Audio-Reset high.It islow in the standby mode if the standby

mode lasted longer than 10s.start keyboard scanning, RC detection. Wake up reasonsare

off.

If the protection state wasleft by short circuiting theSDM pins, detection of aprotection condition during

startup will stall the startup. Protection conditionsin aplaying set will be ignored. The protection mode will

not be entered.

Detect2 ismoved to an interrupt. To be checked ifthe detection on interrupt base isfeasible or not or ifwe should stick to the standard 40msinterval.

+12V, +24Vs, AL and Bolt-on poweris switched on, followed by the +1V2 DCDC converter

Enable the supply detection algorithm

Switch ON Platform and display supply by switchingLOW the Standby line.

Initialise I/O pinsof the st-by P:-Switch reset-AVCLOW (reset state)-Switch reset-system LOW (resetstate)-Switch reset-Ethernet LOW (reset state)-Switch reset-USB LOW (reset state)-Switch reset-DVBsLOW (reset state)- keep Audio-reset and Audio-Mute-Up HIGH

Enable the DCDC converters(ENABLE-3V3n LOW)

NoDetect2 high received

within 2 seconds?

12Verror:Layer1: 3Layer2: 16

Enter protectionYes

Wait 50ms


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Semi Standby

Initialize audio and videoprocessing IC'sand functionsaccording needed use case.

Assert RGB video blankingand audio mute

Wait until previouson-state isleft more than 2seconds ago. (to prevent LCD display problems)

The assumption here isthat afast toggle (SEMI ->ON. Inthese states, the AVC isstill active and can

provide the 2sdelay. If the transition ON->SEMI->STBY->SEMI->ON can be made in lessthan 2s,we have to delay the semi -> stby transition until

the requirement ismet.

Switch Audio-Reset low and wait 5ms

unblank the video.

Wait until valid and stable audio and video, corresponding tothe requested output isdelivered by the AVC.

The higher level requirement isthat audio andvideo should be demuted without transient

effectsand that the audio should be demutedmaximum 1sbefore or at the same time asthe

unblanking of the video.

Release audio mute and wait 100msbefore any other audio

handling isdone (e.g. volume change)

Request Tcon to Switch on the backlight in adirect LED or

set Lamp-on I/O line in case of aside LED

Switch on the Ambilight functionality according the last statussettings.

There isno need to define thedisplay timingssince the timing

implementation ispart of the Tcon.

Start POK linedetection algorithm

return

Startup screen Optionand Installation setting

Photoscreen ON?

Yes

Backlight already on?(splash screen)

No

Yes



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Active

Wait x ms(display file)

Mute all sound outputs viasoftmute

Mute all video outputs

switch off LCD backlight(I/O or IC)

Force ext audio outputsto ground

(I/O: audio reset)And wait 5ms

switch off Ambilight

Set main amplifier mute (I/O: audio-mute)

Wait 100ms

Wait until Ambilight hasfaded out: Output power

Observer should be zero

Switch off LVDSoutput in 85500Theexact timingsto

switch off thedi l (LVDS

Switch off POK linedetection algorithm

200Hz set?

No

Yes

Instruct 200HzTcon to turn off

the display



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transfer Wake up reasonsto the Stand by P.

Semi Stand by

Disable all supply related protectionsand switch offthe DC/DC converters(ENABLE-3V3n)

Switch OFF all suppliesby switching HIGH the

Standby I/O line

Switch AVC system in reset state(reset-system andreset-AVC lines)

Switch reset-USB, Reset-Ethernet and Reset-DVBsLOW

Important remarks:

release reset audio 10 sec after entering

standby to save power

Also here, the standby state hasto bemaintained for at least 4s before starting

Wait 5ms

Wait 10ms

Delay transition until ramping down of ambient light isfinished. *)

If ambientlight functionality wasused in semi-standby(lampadaire mode), switch off ambient light (see CHS

ambilight)

*) If thisisnot performed and the set is

switched to standby when the switch off ofthe ambilightsisstill ongoing, the lightswill

switch off abruptly when the supply iscut.

Switch Memoriesto self-refresh (thiscreatesamore

stable condition when switching off the power).


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Set isstarting up in Factory mode

Set isstarting up in F actory mode?

Noisy picture with bands/linesisvisible and theRED LED iscontinuouson.

An Fisdisplayed and the HDMI 1input isdisplayed.

- Pressthe volume minusbutton on the TVslocal keyboard for 10

seconds

- Pressthe SOURCEbutton for 10 secondsuntil the Fdisappears

from the screen or the noise on the screen isreplaced by blue mute

The noise on the screen isreplaced

with the blue mute or the Fisdisappeared!

Unplug the mainscord to verify the correctdisabling of the factory-mode.

Program display option code

via062598MENU, followed bythe 3digitscode of the display

(thiscode can be found

on asticker inside the set).


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AlignmentsEN44 Q552.1E LA6.

6.7 Total Overview SAM modes
http://www.p4c.philips.com/


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Table 6-10 SAM mode overview

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description

Hardware Info A. SW version e.g. Q5521_0.33.0.0 Display TV & Standby SW version and CTN serialnumber

B. Standby processor version e.g. STDBY_42.42.0.0

C. Production code e.g. see type plate

Operation hours Displays the accumulated total of operation hours.TVswitched on/off & every 0.5 hours is increase one

Errors Displayed the most recent errors

Reset error buffer Clears all content in the error buffer

Alignment White point Colour temperature Normal 3 different modes of colour temperature can be se-lected

Warn

Cool

White point red LCD White Point Alignment. For values,

see Table 6-4 White tone default setting 32" until 6-7

White tone default setting 42"White point green

White point blue

Ambilight Select module

Brightness

Select matrix

TCON alignment used when a new display code (after a SSB

exchange) is keyed-in and if you have alignment

values from production; see Table 6-8 TCON default

settings

Reset TCON alignment used when a new display code (after a SSBexchange) is keyed-in and if you do nothave

alignment values from production

Dealer options Virgin mode Off/On Select Virgin mode On/Off. TV starts up / does not

start up (once) with a language selection menu after

the mains switch is turned on for the first time (virgin

mode)

E-sticker Off/On Select E-sticker On/Off (USPs on-screen)

Auto store mode None

PDC/VPS

TXT page

PDC/VPS/TXT


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AlignmentsEN46 Q552.1E LA6.

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description


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Option numbers Group 1 e.g. 00008.01793.15421.08192 The first line (group 1) indicates hardware options 1to 4

Group 2 e.g. 44013.34315.00000.00000 The second line (group 2) indicates software options5 to 8

Store Store after changing

Initialise NVM N.A.

Store Select Store in the SAM root menu after making any

changes

Operation hours display 0003 In case the display must be swapped for repair, youcan reset the Display operation hours to 0. So,this one does keeps up the lifetime of the display it-

self (mainly to compensate the degeneration behav-iour)

Software maintenance Software events Display Display information is for development purposes

Clear

Test reboot

Test cold reboot

Test application crash

Hardware events Display Display information is for development purposes

Clear

Test setting Digital info Centre frequency: 774605208

QAM modulation: None Display information is for development purposes

Symbol rate:

Original network ID: 0

Network ID: 0

Transport stream ID: 0

Service ID: 0Hierarchical modulation: 0

Selected video PID: 0

Selected main audio PID: 0

Selected 2nd audio PID: 0

Install start frequency 000 Install start frequency from 0 MHz

Install end frequency 999 Install end frequency as 999 MHz

Default install frequency

Installation Digital only Select Digital only or Digital + Analogue before instal-lation

Digital + Analogue

Development file ver-sions

Development 1 file version Display parameters DISPT6.0.9.8 Display information is for development purposes

Acoustics parameters ACSTS0.39.6.16

PQ - TV550 1.0.22.1

PQS- Profile set

PQF - Fixed settingsPQU - User styles

Ambilight parameters PRFAM 5.0.2.4

Development 2 file version 12NC one zip software Display information is for development purposes

Initial main software

NVM version Q55x1_0.3.1.0

Flash units software

Temp com file version none

Upload to USB All To upload several settings from the TV to an USB

stickChannel list

Personal settings

Option codes

Alignments

Identification data

Hi li

Circuit Descriptions EN47Q552.1E LA 7.

7. Circuit Descriptions


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p

Index of this chapter:

7.1 Introduction

7.2 Power Architecture

7.3 DC/DC Converters

7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception

7.5 Front-End DVB-S(2) reception

7.6 HDMI

7.7 Video and Audio Processing - PNX85500

7.8 Back-End

7.9 Ambilight

7.10 TCON

Notes:

Only newcircuits (circuits that are not published recently)

are described.

Figures can deviate slightly from the actual situation, due

to different set executions.

For a good understanding of the following circuit

descriptions, please use the wiring, block (see chapter

9. Block Diagrams) and circuit diagrams (see chapter

10. Circuit Diagrams and PWB Layouts).Where necessary,

you will find a separate drawing for clarification.

7.1 Introduction

The Q552.1E LA chassis is part of the TV550 platform and

comes with the following stylings: Rembrandt (series

xxPFL54xx), van Gogh (series xxPFL56xx), and Matisse

(series xxPFL76xx). The TV550 platform is the successor of

the TV543 platform.

7.1.1 Implementation

Key components of this chassis are:

PNX85500 System-On-Chip (SOC) TV Processor

TX31XX Hybrid Tuner (DVB-T/C, analogue)

STV6110AT DVB-S tuner

SII9x87 HDMI Switch

TPA312xD2PWP Class D Power Amplifier

LAN8710 Dual Port Gigabit Ethernet media access

controller.

7.1.2 TV550 Architecture Overview

For details about the chassis block diagrams refer tochapter 9. Block Diagrams. An overview of the TV550

architecture can be found in Figure 7-1.

Circuit DescriptionsEN48 Q552.1E LA7.


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Figure 7-2 Architecture of TV550 platform - TCON integrated on SSB

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7.1.3 SSB Cell Layout


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Figure 7-3 SSB layout cells (top view) (non-DVBS without TCON)

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VGA

C

lass-

D

DC/DC1M99

1M95

1

7

3

5

1M 20

CA

LOWP

ROFILE

FLASH

SPO

H D

MI1. 3

HD

M

I

1.3

U S B

2.0

S D - S L O T

S c a r t 1 / Y P b P r

S c a r t 2 / Y P b P r Pr

Pb

Y

1 M 3 6

D D R 2

D D R 2

F P G A

20,00D D R 2

D D R 2

PNX85500

M1

2 7 x 2 7

1.00m m

DDR

E TH

IS

S P DIF

A NA

A UD

A NA

V IDS TD B Y

GP IO

H D MI

CA

TS - IN

L V D S - O U T

U S B

RJ451D3

8

1G 51 1G 501M 71 1 M 59 2D D IM

serv

L/R

U S B

2.0Tuner

NOS

PLITTER

!!!

9187

OUT

01 2

3

C T R L

RL

HD

M

I

1.3

HD

M

I

1.3

DC /DC1M99

M95

1 M20

CA

LOWP

ROFILE

FLASH

Quad LVDS

S D - S L O T

1 M 3 6

D D R2 F P G A

2 0 ,0 0D D R2

D D R2

PN X85500M 1

27 x271.00 m m

DDR

E TH G P IO

H D M I

C A

TS -IN

LVD S -OU T

U S B

1 G 51 1G 501M 71 1 M 59 2D D IM

DVB-S DVB-S

1M20 1 M 3 6 1 G51 1G501M 71 1 M59 2 D D IM



50/184

Figure 7-5 SSB layout cells (top view) (non-DVBS with TCON)

18770_248_100203.eps

100219

VGA

Class-

D

DC /DC1M99

1M95

17

3

5

1 M20

CA

LOWP

ROFILE

FLASH

SPO

H D

M I

1. 3

HD

MI

1.3

U S B

2. 0

Quad LVDS

S D - S L O T

S c a r t 1 / Y P b P r

S c a r t 2 / Y P b P r Pr

Pb

Y

1 M 3 6

D D R2

D D R2

F P G A

20,00D D R2

D D R2

PN X85500M 1

27 x271.00 m m

DDR

E TH

IS

S P D IF

A N A

A U D

A N A

V ID S TD B Y

G P IO

H D MI

C A

TS -IN

LVD S -OU T

U S B

RJ451D

38

1 G 51 1G 501M 71 1 M 59 2D D IM

serv

L/R

U S B

2. 0Tuner

NOS

PLITTER

!!!

9187

OUT

0

1 2

3

CT RL

RL

HD

MI

1.3

HD

MI

1.3

DVB-S

1 M2 0 1 M 3 6 1 G51 1G 501M 71 1 M59 2 D D IM

TCON


7.2 Power Architecture


51/184

Refer to figure Figure 7-6for the power architecture of this

platform.

Figure 7-6 Power Architecture TV550 platform

7.2.1 Power Supply Unit

All power supplies are a black box for Service. When defective,

a new board must be ordered and the defective one must be

returned, unless the main fuse of the board is broken. Always

replace a defective fuse with one with the correct

specifications! This part is available in the regular market.

Consult the Service website for the order codes of the boards.

Important deltas with the TV543 platform are:

New power architecture for LED backlight (PSL, PSLS,

Output to the display; in case of

- IPB: High voltage to the LCD panel

- PSL and PSLS (LED-driver outputs)

- PSDL (high frequent) AC-current.

7.2.2 Diversity

The diversity in power supply units is mainly determined by the

diversity in displays. Table 7-1 Supply diversitylists the

different types of displays with its associated PSUs:

18770_234_100127.eps

100127


52/184


7.4 Front-End Analogue and DVB-T, DVB-C;

ISDB-T reception

Channel decoder; I2C address 0xD0

LNB switching regulator; I2C address 0x14

A lifi


53/184

p

7.4.1 European/China region

The Front-End for the European/China region consist of the

following key components:

H ybrid Tuner

Switchable SAW filter 7/8 MHz (Eur.), or single SAW filter

(8 MHz) (China) Bandpass f il ter

Amplifier

PNX85500 SoC TV processor with integrated DVB-T and

DVB-C channel decoder and analogue demodulator.

Below find a block diagram of the front-end application for this

region.

Figure 7-10 Front-End block diagram European/China region

7.4.2 Brazil region

The Front-End for the Brazil region consist of the following key

components:

Hybrid Tuner with integrated SAW filter and amplifier

External ISDB-T channel decoder covering the Brazilian

digital terrestrial TV standard

Bandpass f il ter

Amplifier

PNX85500 SoC TV with integrated analogue demodulator.

Below find a block diagram of the front-end application for this

region.

Amplifier

PNX85500 SoC TV processor with integrated DVB-T and

DVB-C channel decoder and analogue demodulator.

Below find a block diagram of the front-end application for

DVB-S(2) reception.

Figure 7-12 Front-End block diagram DVB-S(2) reception

This application supports the following protocols:

polarization selection via supply voltage (18V = horizontal,

13V = vertical)

band selection via toneburst (22 kHz): tone on = high

band, tone off = low band

satellite (LNB) selection via DiSEqC 1.0 protocol

reception of DVB-S (supporting QPSK encoded signals)

and DVB-S2 (supporting QPSK, 8PSK, 16APSK and

32APSK encoded signals), introducing LDPC low-density

parity check techniques.

7.6 HDMI

In this platform, the Silicon Image Sil9x87 HDMI multiplexer is

implemented. Refer to figure 7-13 HDMI input configurationfor

the application.

18770_235_100127.eps

100219

18770_237_100127.eps100219


54/184


7.8 Back-End


55/184

The following backlight types can be distinguished:

CCFL/EEFL backlight; applicable to the xxPFL54xx sets

LED backlight:

- side-view (edge) LED without scanning: PSL power

board; applicable to xxPFL76xx sets

- side-view (edge) LED with scanning: PSLS power board;

not applicable to this chassis

- direct-view LED with 0D-dimming: PSL power board;

applicable to xxPFL56xx sets

- direct-view LED with 2D-dimming: PSDL power board;

not applicable to this chassis.

Refer to section 7.2.2 Diversityfor an in-depth explanation of

the different power boards that are used.

Figure 7-15 Backlight (xxPFL54xx, xxPFL56xx, xxPFL76xx sets)

application

7.9 Ambilight

In this chassis, only 2-sided Ambilight is implemented. Refer to

figure 7-16 Ambilight architecture.

18770_242_100203.eps

100203

18770_209a_100202.eps

100202

1M

59

1M09

MTKor

PNX85500

SSB

Glue

logic

1

M83

1

M84

AmbiLight

1

M83

1

M84

AmbiLight

1M09

PSU


+3V3


56/184

Figure 7-17 LED grouping per board

The communication between PNX85500, ComplexProgrammable Logic Device (CPLD) and the Ambili ght module

uses the SPI protocol; refer to figure 7-18 Communication

protocol outside LED board. Between the CPLD and the LED

driver, as extra line is mentioned:

Non-SPI signals that are required for the LED driver

Temperature sensor line.

Figure 7-18 Communication protocol outside LED board

Refer to figure for an overview of the communication inside the

LED board.

Figure 7-20 Ambilight buffer

The temperature sensor is built around item no. 7B30 (diagram

AL1A) and indicates overtemperature of the board. Refer to

figure 7-21 Temperature sensor.

Figure 7-21 Temperature sensor

The EEPROM (item no. 7B07; diagram AL1A) contains

alignment information about the mounted LEDs and is

programmed during the alignment process in production. Refer

to figure 7-22 EEPROM.

18770_210_100126.eps100126

3

6

L

E

D

18

4

6L

E

D

24

5

6

L

ED

30

4+

5

L

E

D

9

2

6L

E

D

12

3

5

L

ED

15

6

6

L

E

D

36

18770_211_100126.eps

100126

CPLDPN XSPI SPI + extra

1M59

LE D

DriverBuffer

SPI SPISPI

M83

M84

Extra

18770_214_100126.eps100126

83B30-1

220R

1

4 5

220R

3B30-43B01-1

100R

1 8

5

6

7B20-174LVC2G17

1

2

2B17

100n

33p

2B01

100R

3B01-22 7

100p

2B02

+3V3

3

2

5

4

74LVC2G177B20-2

33p

2B00

2B10

100p

PWM-CLOCK

SPI-CLOCK-BUF

PWM-CLOCK-BUF

SPI-CLOCK

18770_215_100126.eps

100126

-T

+3V3

10n

2B09

FB40

2B08

10n

1K5

1%

3

6

3B39-2

2

7

3B39-31

%

1K5

1

3

4

5

2LMV331IDCK

7B30

+3V3

1K5

1%

8

1

3B39-1

3B34

RES100K

10K

3004 R

ES

3B11

10K

+3V3

FB41

TEMP-SENSOR

2B20

100n

8M95010 WDW67B07

+3V3

SPI-CLOCK-BUF

SPI-DATA-IN-BUF


+3V3


57/184

Figure 7-23 LED driver

The Overvoltage Protection Circuit is built around item no.

7B50, 7B51, 7C20 and 7C22 (diagram AL1B). Refer to figure

7-24 Overvoltage Protection Circuit.

18770_217_100126.eps

100126

OUT

12

11

GSCLK

IREF

MODE

SCLK

SIN

SOUT

XERR

XHALF

XLAT 10

NC

9

8

VCC

0

1

2

3

4

5

6

7

BLANK

13

14

15

GND GND_HS

VIA

VIA

VIA

VIA

2K0

3B31

FB20

3B21 150R

+3V3

+3V3

25

32

FB35

9

10

11

14

15

12

23

27

22

5

16

17

18

19

20

21

6

7

8

31

30

33

24

26

3

12

13

28

29

4

TLC5946RHB7B26-1

100n

2B11

3 6

150R3B00-3

2B04-4

100p

4

5

36

37

38

39

40

41

42

7B26-2TLC5946RHB

34

35

3B18

1K8

1 8

150R

3B00-1

1

8

2B04-1

100p

150R3B00-44 5

150R

3B00-22 7

2B04-2

100p

2

7

3

6

2B04-3

100p

10K

3B22

BLANK

SPI-DATA-IN-BUF

PWM-G1

PWM-R1

PWM-G3

PWM-R3PWM-R2

PWM-B2

PWM-G2

DATA-SWITCH

PWM-G4

PWM-R4

PWM-B4

PWM-R5

PWM-G5

PWM-B5

LATCH

SPI-DATA-IN

SPI-DATA-OUT

PWM-CLOCK-BUF

SPI-CLOCK-BUFPROG

PWM-B1

PWM-B3

BLUE

GREEN

RED

BLUE

GREEN

RED

BLUE

GREEN

RED

BLUE

GREEN

RED

BLUE

GREEN

RED

BLUE

GREEN

RED

65

21

43

99-235/RSBB7C-A24/2D7005

1

8

10K

3B07-1

FB30

3B07-3

10K

3

6

FB31

1

43

700299-235/RSBB7C-A24/2D

65

2

65

21

43

6

700499-235/RSBB7C-A24/2D

3B03-3

1K5

3

2

7

3B07-2

10K

+24V

2 7

1K5

3B03-2

3B36

270R

+24V

2

6

1

BC847BS(COL)7B23-1

3B35

270R

3B37

68R5

3

4

BC847BS(COL)7B23-2

63

65

21

43

700199-235/RSBB7C-A24/2D

4

5

10K

3B07-4

7003

65

21

43

99-235/RSBB7C-A24/2D

1 83B03-1

1K5

+24V

43

99-235/RSBB7C-A24/2D7000

65

21

+24V

PWM-R1

PWM-B1



58/184

Figure 7-25 TCON architecture

For the TCON block diagram, refer to figure 7-26 TCON block

diagram.

18770_238_100127.eps100127

EEPROM

TFT LCD Panel

Mini -LVDS

ControlSignals

+3.3V+1.8V

VGH(+28V)VGL(-6 V)

+12 V

LVDS (10 bit)

Timing

Controller

PowerBlock

Gamma

Reference

VoltageSource Drive IC

GateDriveIC

PNX8550

LCD Panel

TCONMain P latform

SSB

+16 V

LV DS

Receiver

Data

PathBlock(Line

Buffer)

Mini-LVDS

Transmitter

Mini-LVDSOPC ODC DCA

rmatter/Serializer

Spread

SpectrumSDRAM

16 bit

RLV P/N

R1A~E

R 1 C LK

Mini-LVDS

Output

LVDSInput

Timing Co ntroller IC


Notes to figure 7-26 TCON block diagram:

LVDS receiver: converts the data stream back into RGB

data and SYNC signals (Vsync, Hsync, Data Enable - DE)

Timing Control Function: generates control signals to

column drivers and row drivers (Source Enable - SOE,

Gate Enable - GOE, Gate Start Pulse - GSP).


59/184

ODC: Over Drive Circuit - to improve LC response

Data Path Block: the video RGB data input to data path

block is delayed to align the column driver start pulse with

the column driver data

For an overview of the TCON DC/DC converters, refer to figure

7-27 TCON DC/DC converters.

Figure 7-27 TCON DC/DC converters

7.10.1 TCON Programming

For LGD - TCONs, the EEPROM can be programmed viaComPair (via I2C communication).

For Sharp - TCONs, the data can be flashed with a SPI

Programmer (via SPI communication). This device has to be

ordered separately.

7.10.2 TCON Alignment

The purpose of TCON alignment is to obtain equal voltages for

both positive and negative LC polarity. This is to avoid flicker

and image sticking.

The alignment value for the TCON is stored in the main

18770_240_100128.eps

100128

DC/DC

Controller+12V

LGD SHP Where Used

VGH +28V +35VTo Gate Drivers(Gate

High Voltage)

VGL -6V -6VTo Gate Drivers (Gate

Low Voltage)

Vcc +3V3 +3V3Timing Controller IC

Supply Voltage

Vcc +1V8 +1V2Timing Controller IC

Supply Voltage

Vref +16V +15V2Gamma Reference

Voltage

Vdd +16V +15V6 Source Driver Supply

Voltage

IC Data SheetsEN60 Q552.1E LA8.

8. IC Data Sheets

Thi h t h th i t l bl k di d i l t i l di ( ith th ti f d l i


60/184

This chapter shows the internal block diagrams and pin

configurations of ICs that are drawn as black boxes in the

electrical diagrams (with the exception of memory and logic

ICs).

8.1 Diagram USB HubB01C, USB2513B (IC 7F25)

Block diagram

Pinning information

Note : The LED port indicators only apply to USB2513i.

To Upstream

VBUS

3.3 V

Upstream

PHY

Upstream

USB Data

Repeater Controller

Serial

Interface

Engine

Serial

Interface

To EEPROM or

SMBus Master

SCLSDA

Port

Controller

Bus-

Power

Detect/VbusPulse

PHY#1

USB DataDownstream

OC

SenseSwitch/

LEDDrivers

USB DataDownstream

Port

Power

3.3 V

PLL

24 MHz

Crystal

Routing & Port Re-Ordering Logic

Regulator

CRFILT

Port

Power

Regulator

PHY#x

Port #xOC Sense

Switch Driver/LED Drivers

TT#x

TT

#1

...Port #1OC SenseSwitch Driver/

LED Drivers

OCSense

Switch/LED

Drivers

...

The x indicates the number of available downstream ports: 2, 3, 4, or 7.

D33

SET

_N

_IND

/CFG

_SEL[1]

L/SMBCLK/CFG

_SEL[0]

A/SMBDATA/NON

_REM[1]

US

_DET

IC Data Sheets EN61Q552.1E LA 8.

8.2 Diagram Temp Sensor + HeadphoneB01J, LM75BDP (IC 7FD1)


61/184

Block diagram

Pinning information

LM75B

SDA

VCC

SCLA0

OS

DNG1AA2

BIAS

REFERENCE

BAND GAP

TEMP SENSOR

OSCILLATOR

POWER-ON

RESET

11-BIT

SIGMA-DELTA

A-to-D

CONVERTER

POINTER

REGISTER

TIMER

COMPARATOR/

INTERRUPT

COUNTER

LOGIC CONTROL AND INTERFACE

CONFIGURATION

REGISTER

THYST

REGISTER

TOS

REGISTER

TEMPERATURE

REGISTER

LM75BDP

VADS CC

0ALCS

1ASO

1

2

3 6

8

7


8.3 Diagram PNX NandFlash - Conditional AccessB02A, PNX85500 (IC7S00)


62/184

Block diagram

Pinning information

TSout/in for

TSinput

CVBS, Y/C,

LVDSfor

analog CVBS

SPDIF

Low-IF

SSIF, LR

HDMI

CI/CAMPEG

PRIMARYLVDS

VIDEOSECONDARY

MEMORY

VIDEO3D COMB

DIGITAL IF

AUDIO DEMOD

AUDIO IN

HDMI

SCALER,

AUDIO DSP

AUDIO DACS

AUDIO OUT

450 MHz

500 MHz

I2C PWM Px_x IR ADC UART I2C GPIO Flash

analog audio

I2S

SPDIF

SYSTEM

USB 2.0

PNX8550x

DVB-T/Cchannel decoder

DVB

AV-PIP

SPI

RECEIVER

(8051)CONTROLLER

AND DECODE

DECODER

PCMCIA

RGB

PROCESSORSYSTEM

CONTROLLER

MULTI-STANDARD

VIDEODECODER

24KEf CPUMIPS32

x 10

AV-DSP

REDUCTIONAND NOISE

DE-INTERLACE

OUTPUTVIDEO

SUB-PICTURE

ENCODER

OUTPUTVIDEO

quad channel)(single, dual orflat panel display

DRAWINGENGINE

Scatter/GatherTSDemux

Motion-accuratepixel processing

SDMemory

Card

EthernetMAC

analog Y/C

Direct-IF

PNX8550xE

2 4 6 8 101213

1415 17

1619

18 2021 23

222425

261 3 5 7 9 11

ball A1index area

ML

KJ

H

F

D

G

E

CB

A


8.4 Diagram AudioB03A, TPA3120D2PWP (IC7D10)


63/184

1 F

SD

PVCCL

TPA3120D2

PVCCR

VCLAMP

GAIN1

BYPASS

1 F

1 F

0.22 F

AGND

} Control

Shutdown

Control

LIN

RIN

BSR

BSL

PGNDR

PGNDL

0 .2 2 F

22 H

22 H

0 .6 8 F

470 F

0 .6 8 F

1 F

4 70 F

GAIN0

AVCC

MUTE

ROUT

LOUT

1

2

3

4

24

23

22

21

PVCCL

SD

PVCCL

MUTE

PGNDL

PGNDL

LOUT

BSL

PWP (TSSOP) PACKAGE(TOP VIEW)

Pin Configuration

Block Diagram


8.5 Diagram DC/DCB03B, TPS53126PW (IC7U03)


64/184

Pin Configuration

Block Diagram


8.6 Diagram DC/DCB03E, ST1S10PH (IC 7UD0)


65/184

Block Diagram

Pin Configuration


8.7 Diagram DC/DCB03E, LD1117DT25 (IC 7UD2)


66/184

Figure 8-7 Internal block diagram and pin c onfiguration

Block Diagram Pin Configuration

F_15710_166.eps

230905

LD1117DT

DPAK


8.8 Diagram Ethernet + ServiceB04C, LAN8710A-EZKH (IC 7E10)


67/184

Block diagram

Pinning information

10M Rx

Logic

100M Rx

LogicDSP System:

Clock

Data Recovery

Equalizer

Analog-to-

Digital

100M PLL

Squelch &

Filters

10M PLL

Receive Section

Central

Bias

HP Auto-MDIX

Management

ControlSMI

RMII/MIILogic

TXP / TXN

TXD[0:3]TXENTXER

TXCLK

RXD[0:3]RXDV

RXERRXCLK

CRSCOL/CRS_DV

MDCMDIO

LED1LED2

LED Circuitry

MODE Control

nINT

nRST RXP / RXN

10M Tx

Logic

10M

Transmitter

100M Tx

Logic

100M

Transmitter

Transmit Section

PLLXTAL1/CLKIN

XTAL2

MODE0MODE1MODE2

PHY

Address

Latches

PHYAD[0:2]

Auto-

Negotiation

Interrupt

Generator

RMIISEL

MDIX

Control

Reset

Control

RBIAS

VDD2A

LED2/nINTSEL

LED1/REGOFF

XTAL2

XTAL1/CLKIN

VDDCR

RXD3/PHYAD2

RXCLK/PHYAD1

L 0 O 0 S O2

TXD2

MDC

nRST

nINT/TXER/TXD4

TXD0

TXEN

TXCLK

TXD1

RBIAS

TXD3

TXN

RXDV

RXN

VDD1A

TXP

RXP

1

2

3

4

5

6

7

8

SMSCLAN8710/LAN8710i

32 PIN QFN

(Top View)

9 10

11

12

13

14

15

22

21

20

19

18

17

28

27

26

25

16

24

23

32

31

30

29

VSS


8.9 Diagram HDMIB04D, SII9287B (IC 7EC1)


68/184

Block diagram

Pinning information


8.10 Diagram HeadphoneB04E, TPA6111A2DGN (IC 7EE1)


69/184

18770_309_100217.eps

100217

Block diagram

Pinning information

BiasControl

8

1

7

4

VO1

VO2

VDD

5

2

3

6

IN1

BYPASS

SHUTDOWN

VDD/2

IN2

+

+

1

2

3

4

8

7

6

5

VO1IN1

BYPASS

GND

VDDVO2IN2

SHUTDOWN

D OR DGN PACKAGE

(TOP VIEW)


8.11 Diagram Circuit Diagrams and PWB LayoutsB07A, STV6110AT (IC 7R02)


70/184

Figure 8-11 Internal block diagram and pin configuration

18770_304_100217.eps

100217

Block diagram

PLL, dividers

Amplifier

RF_INIP

I

2

C bus interface

IN

QP

QNAGC

RF_OUT

SCLXTAL_IN

SDA

DC offset compensation

XTAL_OUT

XTAL_INN


8.12 Diagram Circuit Diagrams and PWB LayoutsB08A, TPS54283PWP (IC 7T03)


71/184

Block diagram

7FB1

+

Soft Start

1 CCOMP

+

S Q

QR

R+

CurrentComparator

BP

f(IDRAIN1

) + DC(ofst)

2

1

3

Anti-CrossConduction

1.2 MHzOscilator

Divideby 2/4

Ramp

Gen 1

Ramp

Gen 2

CLK1

CLK2

BP

CLK1

Weak

Pull-Down

MOSFET

5EN1

6EN2

6 A6 A

VDD2

Internal

Control

10SEQ

150 k

150 k

OutputUndervoltage

Detect

BPFB1

FB2

CLK1

4GND

8FB2

+

Soft Start

2 CCOMP

+

S Q

QR

R+

Current

Comparator

BP

13

14

12

Anti-CrossConduction

BP

CLK2

Weak

Pull-Down

MOSFET

11BP

CLK2

4GND

5.25-VRegulator

BOOT1

PVDD1

SW1

BOOT2

PVDD2

SW2

f(IDRAIN2) + DC(ofst)

f(IDRAIN1

)

f(IMAX1

)

Overcurrent Comp

f(ISLOPE1

)

Level

Shift

Level

Shift

f(IDRAIN2

)

f(IMAX2

)f(ISLOPE2)

FET

Switch

TSD

PVDD2

f(ISLOPE1

)

f(ISLOPE2

)

SD1

SD2

UVLO

0.8 VREF

SD2

0.8 VREF

SD1

Overcurrent Comp

RCOMP

RCOMP


8.13 Diagram Circuit Diagrams and PWB LayoutsB08B, LNBH23Q (IC 7T50)


72/184

Block diagram

Pinning information

SDA SCL

LNBH23

ADDR

A-GND

IC Diagnostics

IC interface

DSQIN

Vup

VoRX

VoTX

LX

22KHzOscill.

PW

M

Co

ntroller

Rsense EN

VSEL

Linear Post-reg

+Modulator

+Protections

+Diagnostics

ITEST

TTX EN

VSEL

VOUT Control

EXTM

P-GND

Preregulator

+U.V.lockout

+P.ON reset

BypVcc Vcc- LISEL TTX

TEN

DSQOUT

DETIN22KHz Tone

Amp. Diagn.

22KHz Tone

Freq. Detector

TTX

VCTRL

SDA SCL

LNBH23

ADDR

A-GND

IC Diagnostics

IC interface

DSQIN

Vup

VoRX

VoTX

LX

22KHzOscill.22KHzOscill.

PW

M

Co

ntroller

Rsense EN

VSEL

Linear Post-reg

+Modulator

+Protections

+Diagnostics

ITEST

TTX EN

VSEL

VOUT Control

EXTM

P-GND

Preregulator

+U.V.lockout

+P.ON reset

BypVcc Vcc- LBypVcc Vcc- LISEL TTX

TEN

DSQOUT

DETIN22KHz Tone

Amp. Diagn.

22KHz Tone

Freq. Detector

TTXTTX

VCTRL

1 n . c.

2 n . c.

3 n.c .

4 LX

5 P -G N D

6 S DA

7 n . c.

8 n.c .

9 S CL10ADDR

11 DS Qo ut

12 DS QIN

13 EXTM

14TTX

1 5 B Y P

16n .c .

17n .c .

18 Vcc-L

1 9 V c c

20A- GND

21VoRX

22VoTX

23

Connected with power groundsand to

the ground layer through viasto dissipate the heat.

Epad


8.14 Diagram TCON ControllerB11A, TL2429MC (IC 7J01)

Bl k di


73/184

Figure 8-14 Internal block diagram and pin configuration

18770_310_100217.eps

100217

Block diagramRLV0~6P/M,

ODC + OPC

TCON

mini-LVDS

TFT LCD ARRAY

GateDriver

1

Gate

Driver2

Gate

Driver

n

Source

Driver 1

Source

Driver 2

Source

Driver 5

Source

Driver 8

VST(GSP)

SOE,POL

1RxA~E

2RxA~E

1RxCLK

2RxCLK

LVDS

Input

EEPROM

(LUT)16Kbit

or 32Kbit

SCL

SDA

LLV0~6P/M

3RxA~E

4RxA~E

3RxCLK

4RxCLK

Internal

SSIC

Frame Memory

SDRAM

Gate inpanel

1

Gate in

panel2

Gate in

panel

n

GCLK1,

,GCLK3

,

,GCLK6


8.15 Diagram TCON ControllerB11B, TPS62110RSA (IC 7JH1)

Bl k di


74/184

Block diagram

Pinning information

16 15 14 13

1

2

GND

GND

PGNDExposedThermal

P d

VIN

DNGP

WS

WS

GP

12

11

_

+

_+

_

+

_

+

_

+

REF

REF

IAVG Comparator

P-Channel

Driver

Shoot-Through

LogicControl

Logic

1-MHz

Oscillator

ComparatorS

R

N-Channel

V (COMP)

Sawtooth

Generator

V

I

Undervoltage

Lockout

_

+Compensation

REF

R2

R1

V I

EN

SW

DNGPBF

Gm

Thermal

Shutdown

Vina

_

+

_+SKIP Comparator

_

+

_+

PG

LBO

LBI GND

A. The internal feedback divider is disabled and the FB pin is directly connected

to the internal GM amplifier.


8.16 Diagram TCON ControllerB11B, MAX17113ETL (IC 7JF1)

Block diagram


75/184

Block diagram

Pinning information

DEL2

FSEL

VIN

VL

EN2

PGND

IN2

IN2

27282930 26 24 23 22

EN1

25

32 LX2LX1

31

19

20 LX2

OUT

21

PGND

STEP-DOWN OSC

VL

LX2

GND2

OUT

FB2

VIN

REF

AGND

DEL1

VL VL

VIN

VIN (12V)

3.3V

2A

150mV

STEP-UP

POWER-UP

SEQUENCE

HV

SWITCH

BLOCK

NEGATIVE

REG

POSITIVE

REG

IN2

LX1

PGND

FB1

COMP

FSEL

AGND

SWI

SWO

PGOODPGOOD

3.3V

VL

BST

VGOFF

-6V

100mA

REF

VL

AVDD16V

1.5A

REF

DEL2

DLP

DRVN

FBN FBP

REF

VIN

CPGND

50% OSC

EN1STEP-DOWN, NEGATIVE

ON/OFF

EN2STEP-UP, POSITIVE

CHARGE PUMP ON/OFF

P

VGON

35V

50mA

DRN

THR

MODE

CRST

CTL GON

CONTROL

GON

AVDD

SRC

SWO

SRCDRVP

CPGND

RESET


8.17 Diagram TCON DC/DCB14B, ISL97653AIRZ (IC 7KFA)

Block diagram


76/184

Block diagram

Pinning information

1

40

2

3

4

30

29

28

27

39 38 37 36 35 34 33 32 31

LDO-CTL

LDO-FB

PVIN1

AGND

PROT

LX2

LX1

PGND2

PGND1

TEMP

COMP

FBB

RSET

HVS

PVIN2

CB

LXL1

LXL2

+-

+-

+-

+-

+-

+-

+-

+-

CONTROL

LOGIC

SAWTOOTH

GENERATOR

CURRENT

AMPLIFIER

CURRENT LIMIT

COMPARATOR

CURRENT LIMIT

THRESHOLD

REFERENCE BIAS

AND

SEQUENCE CONTROLLER

VREF

GM AMPLIFIER

UVLO COMPARATOR

OSCILLATOR

0.75 VREF

REGULATOR

SUPN

0.2V

UVLO COMPARATOR

0.4V

0.75 VREF

VREF

POUT

RSENSE

BUFFER

CONTROL

LOGIC

VREF

SAWTOOTHGENERATOR

SLOPECOMPENSATION

GM AMPLIFIER

SUPP

CURRENT LIMITTHRESHOLD

CURRENTLIMITCOMPARATOR

SUPP

C1- C1+ C2+ C2-POUT CTL COM

BUFFER

LX1

PGND1

CB

LXL1

CM2

FBL

FBP

FBN

NOUT

PVIN1,2

EN

CDEL

PVIN1,2

VL

FBB

CM1

PGND2

LX2

CURRENT AMPLIFIER

SLOPECOMPENSATION

VREF

FREQ

HVS

LOGIC

RSET HVS PROT

LXL2

DRN

680kHz

VL

LDO

CONTROL

LOGIC2

LDO-CTL

LDO-FB

TEMP

SENSORTEMP

BlockDiagrams EN 77Q552.1E LA 9.

9. Block Diagrams

9-1 Wiring diagram Rembrandt 32"WIRING DIAGRAM 32" REMBRANDT

Board Level Repair


77/184

2010-Feb-19 back todiv. table

MAINSSWITCH

11P

1M95

9P

1M99

1319

1P3

1316

1P3

2P3

1311

2P3

13081735

4P

1M95

11P

1M99

9P

1JA2

60P

1JA1

60P

1M20

8P

MAINSC

ORD

8191

8JA1

8JA2

CN2 CN1

3PJ

1

SSB(1150)B

MAIN POWER SUPPLYIPB 32 PLHC-P981A B(1005)

LCD DISPLAY

(1004)

LOUDSPEAKER

(5213)

TOBACKLIGHT

TOBACKLIGHT

KEYBOARD

CONTROL

(1114)

IR / LED BOARD

(1112)

8M99

8M20

8M95

8311

18770_400_100217.eps100219

1M99 (B03C)1. +12VD2. +12VD3. GND4. GND5. LAMP-ON6. BACKLIGHT-PWM_BL-VS7. BACKLIGHT-BOOST8. BACKLIGHT-PWM-ANA-DISP

9. POWER-OK

1M95 (B03C)1. +3V3-STANDBY2. STANDBY3. GND4. GND5. GND6. +12V7. +12V8. +12V

9. +24V-AUDIO-POWER10.GND-AUDIO11.MAINS-OK

1735 (B03A)1. LEFT-SPEAKER2. GND-AUDIO3. GND-AUDIO4. RIGHT-SPEAKER

1M20 (B09A)1. LIGHT-SENSOR2. GND3. RC4. LED-25. +3V3-STANDBY6. LED-17. KEYBOARD8. +5V

1JA2 (B11C)1. GND|19.VDD20.VDD|24.VCC25.VCC|60.GND

1JA1 (B11C)1. GND|36.VCC37.VCC|41.VDD42.VDD|60.GND

HIGH VOLTAGE

LN

Component Level RepairOnly For Authorized Workshop

USB

HDMI

PHONE

CONDITIONALACCESS

HDMI

HDMIHDMIVGA

SCART

TUNER

J2

3P

J1

8P

EN 78Q552.1E LA 9.BlockDiagrams

9-2 Wiring diagram Rembrandt 37" - 42" -

Board Level Repair

Component Level RepairOnly For Authorized Workshop


78/184


TWEETER(5215)

TWEETER(5215)

MAINSSWITCH

11P

1M95

9P

1M99

1319

1P3

1316

1P3

2P3

1311

2P3

13081735

4P

1M95

11P

1M99

9P

1JA2

60P

1JA1

60P

1M20

8P

MAINSC

ORD

8191

8JA1

8JA2

CN2 CN1

3PJ

1

SSB(1150)B

MAIN POWER SUPPLYIPB 37 PLHD-P982A B

IPB 42 PLHF-P983A B(1005)

LCD DISPLAY

(1004)

TOBACKLIGHT

TOBACKLIGHT

KEYBOARD

CONTROL

(1114)

IR / LED BOARD

(1112)

8M99

8M20

8M95

8311

18770_401_100217.ep s100219

1M99 (B03C)1. +12VD2. +12VD

3. GND4. GND5. LAMP-ON6. BACKLIGHT-PWM_BL-VS7. BACKLIGHT-BOOST8. BACKLIGHT-PWM-ANA-DISP9. POWER-OK

1M95 (B03C)1. +3V3-STANDBY2. STANDBY

3. GND4. GND5. GND6. +12V7. +12V8. +12V9. +24V-AUDIO-POWER10.GND-AUDIO11.MAINS-OK

1735 (B03A)1. LEFT-SPEAKER2. GND-AUDIO

3. GND-AUDIO4. RIGHT-SPEAKER

1M20 (B09A)1. LIGHT-SENSOR2. GND

3. RC4. LED-25. +3V3-STANDBY6. LED-17. KEYBOARD8. +5V

1JA2 (B11C)1. GND|

19.VDD20.VDD|24.VCC25.VCC|60.GND

1JA1 (B11C)1. GND|

36.VCC37.VCC|41.VDD42.VDD|60.GND

HIGH VOLTAGE

LN

USB

HDMI

TUNER

PHONE

CONDITIONALACCESS

HDMI

HDMIHDMI VGASCART

LOUDSPEAKER

(5213)

J2

3P

J1

8P

BlockDiagrams EN79Q552.1E LA 9.

9-3 Wiring diagram Van Gogh 32" - 40"

TO DISPLAY TO DISPLAYLCD DISPLAY

(1004)

WIRING DIAGRAM 32"- 40" VAN GOGH

Board Level Repair


79/184


TWEETER(5216)

TWEETER(5216)

MAINSSWITCH

11

P

1M95

9P

1M99

2P3

1311

2P3

1308

1735

4P

1M95

11P

1319

32"-6P

1316

32"-12P

1319

40"-10P

1316

40"-10P

1M99

9P

1KA2

80P

1KA1

80P

1M20

8P

MAINSC

ORD

8191

3PJ1

SSB(1150)B

MAIN POWER SUPPLY32"-FSP124-3MS01 B40"-DPS-206CP A B(1005)

KEYBOARD

CONTROL

(1114)

IR / LED BOARD

(1112)

8M99

8M95

8311

18770_402_100217.eps100219

1M99 (B03C)1. +12VD2. +12VD3. GND4. GND5. LAMP-ON6. BACKLIGHT-PWM_BL-VS7. BACKLIGHT-BOOST8. BACKLIGHT-PWM-ANA-DISP9. POWER-OK

1M95 (B03C)1. + 3V3-STANDBY2. STANDBY3. GND4. GND5. GND6. +12V7. +12V8. +12V9. +24V-AUDIO-POWER10.GND-AUDIO11.MAINS-OK 1735 (B03A)

1. LEFT-SPEAKER2. GND-AUDIO3. GND-AUDIO4. RIGHT-SPEAKER

1M20 (B09A)1. LIGHT-SENSOR2. GND3. RC4. LED-25. + 3V3-STANDBY6. LED-17. KEYBOARD8. +5V

1KA2 (B14E)1. GND|11.VLS_15V612.VLS_15V6|33.VCC_3V334.VCC_3V3|78.VGH_25V79.VGL_6V80.GND

1KA1 (B14E)1. GND|11.VLS_15V612.VLS_15V6|33.VCC_3V334.VCC_3V3|78.VGH_25V79.VGL_6V80.GND

LN

Component Level Repair

Only For Authorized Workshop

USB

HDMIT

UNER

PHONE

SPDIF

CONDITIONA

LACCESS

HDMIHDMI VGASCART

LOUDSPEAKER

(5213)

8M20

TOBACKLIGHT

8KA1

8KA2

NOTFOR32" TV-SETS NOTFOR32" TV-SETSJ2

3P

J1

8P


80/184


81/184

EN82Q552.1E LA 9.BlockDiagrams

9-6 Block Diagram Video

B02 PNX85500 B06B VIDEO OUT - LVDS B11A TCON CONTROLLER (LGD) B11C MINI LVDS

B01A COMMON INTERFACE

B07A DVBS FE

7R02 7R01

7600PNX85433EH/M2A

VIDEO STREAMB02A LVDSB02F

VIDEO

PCMCIA

CONDITIONALACCESS

20+3V3

MD0

MDI

7F0174LVC245APW

BUFFER

1P00

68P

51

52

18

17+5VCA

CA-MDO(0-7)MDO(0-7)

CA-MDI(0-7)

PX1

PX2

PX1

PX2

1G50

TO DISPLAY(TCONONDISPLAY)

TO TCONSSB TO DISPLAY(TCONONSSB)

LML

1

2

3

3

1JA1

60

34

21

58

53

13

7J01TL2429MC

GMA

7J02

M24C32

EEPROMSDA-TCON

SCL-TCON 41

42

37

36+VCC

+VDD


82/184


B11BTCON DC/DC

B04A ANALOGUE EXTERNAL S A

B01I VGA

B04BANALOGUE EXTERNALS B

B01FHDMI & CI

B07A DVBS-FE

B05ADDR

B01CUSB HUB

B01BFLASH

B14ATCON CONTROL (SHARP) B14E MINI LVDS (

B14DMPD

B14CP GAMMA &VOM & FLASH

B01HHDMI B04D HDMI

1E04

1E08

1E03

21

7R02STV6110AT

DVB-S

TUNER

7R01STV0903BAC

DVB-S

CHANNEL

DECODER

7

ANALOG VIDEOB02I

HDMI_DVB02C

AV3-PB

AV3-Y

AV3-PR

PB

PR

Y

EXT 1

EXT 2

EXT 3

1E01

1E02

2021

1

7

11

1516

2021

1

7

11

1516

SCART1

SCART2

19

7E04

19

7E05

1

1E05

2

3

14

13

R-VGA

G-VGA

B-VGA

H-SYNC-VGA

V-SYNC-VGA1 6

10

11

5 15

VGA

CONNECTOR

AC12

AD15

AE15

AC15

AF13

AC18

AB18

AE16

AD16

AF16

AV1-BLK16

7E09-1

AV2-STATUS8B02G

CONTROL

AV1-STATUS8

16 AV2-BLK

7E09-2

B02G

CONTROL

B02G

B02G

CONTROL

CONTROL

63 HDMIA-RXC-

HDMIA-RX0+

HDMIA-RX0-

HDMIA-RX1+

HDMIA-RX1-

HDMIA-RX2+

HDMIA-RX2-

62

61

60

59

58

57

56

HDMIA-RXC+

U26

T25

T26

W24

U25

V26

W26

W25

V25

RX1_B_P

RX2_B_N

RX2_B_P

RREF

RX1_B_N

RX0_B_P

RXC_B_P

RXC_B_N

RX0_B_N

TXC_N

TXC_P

TX0_N

TX0_P

TXA_N

TX1_P

TX2_N

TX2_P

PNX85500

18770_405_100217.eps100219

IP

SAT IN

2

2

2

TUNER_P

TUNER_N

IF_AGC

7E06

CVBS-MON-OUT1 AF11CVBS1_OUT

7 AV4-PB AD14 AI23

AV4-PR15 AC14AI33

11 AV4-Y AE14AI13

AV2-CVBS20 AB14AI42

ATV_CVBS_Y3

CR

VGA_R

VSYNC_IN

VGA_G

VGA_B

PR_R_C1

Y_G1

PB_B1

AC1315 AV1-RAV1_R

7 AD13AVI-BAV1_B

11 AE13AV1-GAV1_G

20 AB15AV1-CVBSCVBS_Y1

TNR_SER1_MIVAL

TNR_SER1_SOP

TNR_SER1_MICLK

TNR_SER1_DATA

HSYNC_IN

+3V3

3S0W

1

5SVHSIN

24

3

1ECB Y-SVHS

C-SVHS

PX3

PX4

PX3

PX4

QUAD LVDS

1920x1080

100/120HZ

1G51

+VDISP

TO DISPLAY(TCONONDISPLAY)

I2C

50

51

49

40

40

3

4

2

1

TO TCONSSB

TO TCONSSB

TO TCONSSB

TO DISPLAY

(TCONONSSB)

RML

N.C.41

1JA2

59

60

48

40

27

24

25

20

19

2

1

1

20 8IM

32 122XTAL

18 12QP

19 11QM

78 TS-DVBS-VALID

75 TS-DVBS-SOP

74 TS-DVBS-CLOCK

73 TS-DVBS-DATA

4

AD12

AE12

AF12

MEMORYB02B

V1DDR2-VREF-CTRL3

A2DDR2-VREF-CTRL2

VREF_2

VREF_1

CONROLB02E

FLASHB02A

7F20NAND02GW3B2DN6FNAND04GW3B2DN6F

NAND

FLASH

256MB

512MB

4

3

2

1

USB-DM

USB-DP

USB-DM2

5000 Serie

7000 Serie

USB-DP2

USB-DM1

USB-DP1

SIDEUSBCONNECTOR

1P08

+5V-USB1

R26

R25

12,37+3V3VCC

USB_DP

USB_DN

+5V-USB2

XIO_D

2

1

3

4

4

3

2

1

SIDEUSBCONNECTOR

1P07

2

1

3

4

9F26

9F25

9F21

9F20XIO-D(00-07)

5000 Serie 256MB7000 Serie 512MB

7JC1MAX9668ETP

TIMING

CONTROL

GMA

GMA

GAMMA

REF

SYST

7JD1MAX17119ET

LEVELSHIFTER

CLKGCLK

+VCC

+VDD

2

13

PX1

PX2

PX3

PX4

TO DISPLAY(TCON ON SSB)

TO DISPLAY(TCONONSSB)

L_LV

R_LV

1KA2

59

81

48

50

13

24

25

20

19

1KA1

81

50

13

58

53

2

13

1

1

7KAAUPD809900F

7KQAISL24837IRZ

TIMING

CONTROL

GMA

GMA

REFVOLTAGE

GEN

7KQBM25P32

FLASH

7KUEMAX17079GTL

LEVELSHIFTER

CS(1U-12U)CS(1-12)

+VCC

+VDD

41

42

37

36+VCC

+VDD

SPI

SDO

SCS

SCK

2

13

SSB3104 313 6364* SSB3104 313 6400*

SSB3104 313 6402*SSB3104 313 6406*

OR

Only 7000 Serie

7EC1SII9187ACNUSII9287BCNU

HDMI

SWITCH

VCC33

RXC

RXD

RXB

RXA

72

71

69

68

66

65

63

62

42

41

39

39

36

35

33

32

23

22

20

19

17

16

14

13

90

89

87

86

84

83

8180

19

1

18

2

1

1P05

3

4

7

9

1012

6

DRX2+

DRX2-

DRX1+

DRX1-

DRX0+

DRX0-

DRXC+DRXC-HDMI SIDE

CONNECTOR

19

1

18

2

1

1P02

3

4

7

9

10

12

6

CRX2+

CRX2-

CRX1+

CRX1-

CRX0+

CRX0-

CRXC+

CRXC-HDMI 1CONNECTOR

1

1P03

3

4

7

9

10

12

6

BRX2+

BRX2-

BRX1+

BRX1-

BRX0+

BRX0-

BRXC+

BRXC-

1

1P04

3

4

7

9

10

12

6

ARX2+

ARX2-

ARX1+

ARX1-

ARX0+

ARX0-

ARXC+

ARXC-

19

1

18

2

HDMI 2CONNECTOR

19

1

18

2

HDMI 3CONNECTOR

9,27,64+3V3-HDMI

Only 7000 Serie

Only ForDVBS

PNX-IF-AGC

4

5

1F75

SAW36MHZ17

2F74

2F78

2F90 3F79-1

3F79-45F70

1T01TH2603

IF-OUT1

IF-OUT2

MAIN HYBRID

TUNER

2

3

4

7

6

PNX-IF-P

PNX-IF-N11

10 1

2

7F75UPC3221GV

AGCAMPLIFIER

IN

VCC

OUT

AGCCONTROL

1

SELECT-SAW

RF IN

5F73

7F70

B02E

CONTROL

BANDPASS

FILTER

TUN-IF-P

TUN-IF-N

1R10

16M

31

30

DDR2-VREF-DDR

A1E2A1E2A1E2A1E2

+1V8

SDRAM

128MB

7B01EDE1108AGBG

SDRAM

128MB

7B02EDE1116AEBGEDE1108AGBG

SDRAM

128MB

7B03EDE1108AGBG

DQ

A

SDRAM

128MB

7B00EDE1116AGBGEDE1108AGBG

VREF

VDDL

VREF

VDDL

VREF

VDDL

VREF

VDDL

DDR2-D(0-31)

D(24-31)

D(16-23)

D(8-15)

D(0-7)

DDR2-A(0-13)

5000 Serie 256MB 7000 Serie 512MB

BlockDiagrams EN83Q552.1E LA 9.

9-7 Block Diagram Audio

B02D CLASS-D B03A AUDIO

B02 PNX85500B01A COMMON INTERFACE

7H00PNX85439EH/M2

AUDIOB02D

AD7

1735

1

2

SPEAKERL

ADAC(1) +AUDIO-L

7D10TPA3123D2PWP

CLASS D

POWER

OUT-L

PVCC_L

PVCC_R

512 22IN-L

LEFT-SPEAKER

ADAC_1

AUDIO

1,3

10,12+24V-AUDIO-POWER

5D07

5D08

VIDEO STREAMB02A

PCMCIA

CONDITIONALACCESS

20+3V3

MD0

MDI

7F0174LVC245APW

BUFFER

1P00

68P

51

52

18

17+5VCA

CA-MDO(0-7)MDO(0-7)

CA-MDI(0-7)

7S05LM324P

14


83/184


B01H HDMI B04D HDMI B02DPNX85500: AUDIO

B04E HEADPHONE

B04B ANALOGUE EXTERNALS B

B04A ANALOGUE EXTERNALS A

B01J TEMP SENSOR + HEADPHONEB01F HDMI & CI

B07A DVBS-FE

B05A DDR

B01C USB HUB

B01B FLASH

STANDBYB03H

HDMI_DVB02c

STANDBYB02G

PNX85500

18770_406_100217.eps100219

AE7

SPEAKERL3

4

SPEAKERR

SUBWOOFER

(OPTIONAL)

ADAC(2) -AUDIO-R

RESET-AUDIOAD1

AC19

ADAC(4)

AMP1

AMP2ADAC(3)

HEADPHONEOUT 3.5mm

AF7

AD6

7EE1TPA6111A2DGN

HEADPHONEAMPLIFIER

1

7IN-1

SHUTDOWN

IN-2

2

6

5

A-PLOP B03A

B02G

B03C

AMPLIFIER

OUT-R

10 6

15

IN-R

MUTE

SD

4

2

AUDIO-MUTE-UP

A-STBY

A-STBY

B04A

STANDBY &PROTECTION

7D03

MAINSWITCHDETECT

7D03

RIGHT-SPEAKER

AE6

AF6

AE10

AF10

AD10

AC10

AU DI O- OU T- L 1

7

3

1E08

4

6

5

ADAC(5)

ADAC(6)

AUDIO-IN3-L

AUDIO-IN3-R

AE9

AF9AUDIO IN

L+R

ADAC_2

PO_7

PO_6

ADAC3

ADAC4

1328

2

3

1

7 EE 0-1 7 EE 0-2

1D38

1

2

3DETECT2

MAINS-OK

1

1E01-1

3

6

AP-SCART-OUT-L

AP-SCART-OUT-R

2

1

1E02

3

2

6

AP-SCART-OUT-L

AP-SCART-OUT-R

AUDIO-IN2-R

AUDIO-IN2-L

2021

1

7

11

1516

SCART1

SCART2

A-PLOP

7E01A-PLOP

B03C

2021

1

7

11

1516

7S05

AUDIO-OUT-R3EA7-4

3EA7-1

AUDIO-IN1-L

AUDIO-IN1-R

5D03

7EC1SII9187ACNUSII9287BCNU

HDMI

SWITCH

VCC33

RXC

RXD

RXB

RXA

72

71

69

68

66

65

63

62

42

41

39

39

36

35

33

32

23

22

20

19

17

16

14

13

90

89

87

86

84

83

81

80

19

1

18

2

1

1P05

3

4

7

9

10

12

6

DRX2+

DRX2-

DRX1+

DRX1-

DRX0+

DRX0-

DRXC+

DRXC-HDMI SIDECONNECTOR

19

1

18

2

1

1P02

3

4

7

9

10

12

6

CRX2+

CRX2-

CRX1+

CRX1-

CRX0+

CRX0-

CRXC+

CRXC-HDMI 1CONNECTOR

1

1P03

3

4

7

9

10

12

6

BRX2+

BRX2-

BRX1+

BRX1-

BRX0+

BRX0-

BRXC+

BRXC-

1

1P04

3

4

7

9

10

12

6

ARX2+

ARX2-

ARX1+

ARX1-

ARX0+

ARX0-

ARXC+

ARXC-

19

1

18

2

HDMI 2CONNECTOR

19

1

18

2

HDMI 3CONNECTOR

14 ARC-eHDMI+ eHDMI+

9,27,64+3V3-HDMI

8+3V3VDD

VO_1

VO_2

AD9

AC9

AUDIO-IN4-L

AUDIO-IN4-RVGA(ORDVI)

AUDIO

1E09

2

3

1

AIN4_L

AIN4_R

ADAC_5

ADAC_6

AIN1_R

AIN2_L

AIN2_R

AIN3_L

AIN3_R

ADAC_5

ADAC_6

AIN1_L

21

7R02STV6110AT

DVB-STUNER

7R01STV0903BAC

DVB-SCHANNEL

DECODER

7

ANALOG VIDEOB02I

IP

SAT IN

TUNER_P

TUNER_N

IF_AGC

TNR_SER1_MIVAL

TNR_SER1_SOP

TNR_SER1_MICLK

TNR_SER1_DATA

20 8IM

32 122XTAL

18 12QP

19 11QM

78 TS-DVBS-VALID

75 TS-DVBS-SOP

74 TS-DVBS-CLOCK

73 TS-DVBS-DATA

4

PNX-IF-AGC

4

5

1F75

SAW36MHZ17

2F74

2F78

2F90 3F79-1

3F79-45F70

1T01TH2603

IF-OUT1

IF-OUT2

MAIN HYBRID

TUNER

2

3

4

7

6

AD12

AE12

AF12

PNX-IF-P

PNX-IF-N11

10 1

2

+5V-TUN-PIN7F75UPC3221GV

AGC AMPLIFIER

IN

VCC

OUT

AGCCONTROL

1

SELECT-SAW

RF IN

5F73

7F70

B02E

CONTROL

BANDPASSFILTER

MEMORYB02B

V1DDR2-VREF-CTRL3

A2DDR2-VREF-CTRL2

VREF_2

VREF_1

8

1E07

1AF5

AF18

DIGITALAUDIO

OUT

SPDIF-OUT-PNX

SEL-HDMI-ARC

SPDIF-OUT2

1

4

5

3

8

SPDIF_OUT

P0_4

7S09&

+3V3

A-PLOP

7D15

A-PLOPB04E

CONROLB02E

FLASHB02A

7F20NAND02GW3B2DN6FNAND04GW3B2DN6F

NAND

FLASH

256MB

512MB

4

3

2

1

USB-DM

USB-DP

USB-DM2

5000 Serie

7000 Serie

USB-DP2

USB-DM1

USB-DP1

SIDEUSB

CONNECTOR

1P08

+5V-USB1

R26

R25

12,37+3V3VCC

USB_DP

USB_DN

+5V-USB2

XIO_D

2

1

3

4

4

3

2

1

SIDEUSBCONNECTOR

1P07

2

1

3

4

9F26

9F25

9F21

9F20

XIO-D(00-07)

DDR2-VREF-DDR

A1E2A1E2A1E2A1E2

+1V8

SDRAM

128MB

7B01EDE1108AGBG

SDRAM

128MB

7B02EDE1116AEBGEDE1108AGBG

SDRAM

128MB

7B03EDE1108AGBG

DQ

A

SDRAM

128MB

7B00EDE1116AGBGEDE1108AGBG

VREF

VDDL

VREF

VDDL

VREF

VDDL

VREF

VDDL

DDR2-D(0-31)

D(24-31)

D(16-23)

D(8-15)

D(0-7)

DDR2-A(0-13)

5000 Serie 256MB 7000 Serie 512MB

5000 Serie 256MB7000 Serie 512MB

Only 7000 Serie

Only 7000 Serie

Only ForDVBS

5000 Serie mux SIL9187 - non Instaport7000 Serie mux SIL9287 - Instaport

5EC2

TUN-IF-P

TUN-IF-N

1R10

16M

31

30

63 HDMIA-RXC-

HDMIA-RX0+

HDMIA-RX0-

HDMIA-RX1+

HDMIA-RX1-

HDMIA-RX2+

HDMIA-RX2-

62

61

60

59

58

57

56

HDMIA-RXC+

U26

T25

T26

W24

U25

V26

W26W25

V25

RX1_B_P

RX2_B_N

RX2_B_P

RREF

RX1_B_N

RX0_B_P

RXC_B_P

RXC_B_N

RX0_B_N

+3V3

3S0W

EN84Q552.1E LA 9.BlockDiagrams

9-8 Block Diagram Control & Clock Signals

B01D SD-CARD B02A PNX85500 B06C AMBILIGHT

CONTROL + CLOCK SIGNALS

TOAMBILIGHT

MODULE

B02E ETHERNET

PNX85500

7S00PNX85507EB

SD-CARDCONTROL

1P09

W21 SDIO-DAT3CC_DAT3

2 W6

SDIO-CLK

SDIO-CMDCMD

10 U6SDIO CDn

W15CLK

7 W5SDIO-DAT0DAT_0

8 W4SDIO-DAT1DAT_1

9 W3SDIO-DAT2DAT_2

PXCLK54B02E

B02G

1M59

2

1

3

5

8

7

10

11

13

Pin8

Pin3

Pin5

Pin7

Pin6

Pin4

Pin9

Pin2

Pin1

7GA0XC9572XL

CPLD41

43

40PNX-SPI-SDI

39PNX-SPI-SDO

3PNX SPI CS BLnV22

PNX-SPI-CLK

AMBI-SPI-CLK-OUT22

AMBI-SPI-SDO-OUT27

AMBI-SPI-SDI-OUT_G123

AMBI-PWM-CLK_B229

AMBI-SPI-CS-OUTn_R230

AMBI-LATCH1_G231

AMBI-PROG_B119

AMBI-BLANK_R120

AMBI LATCH2 DI S28


84/184


B04D HDMI

B04C ETHERNET + SERVICE

B01A COMMON INTERFACE

B09A DVBSCONNECTOR BOARDB11D CONNECTORSB14F CONNECTORS

B01B FLASH

B03C DC / DC

B05A DDR

B01E PNX85500-CONTROL

B04V ETHERNET + SERVICE

B02E PNX85500: MIPS B01C USB HUB

B03C DC / DC

B02GPNX85500:STANDBY CONTROLLER

B07A DVBS-FE B01K TUNER BRAZIL

B02G PNX85500: STANDBY CONTROLLER

1F51

1

3

4

5

2LEVEL SHIFTED

FOR

DEBUGUSE

ONLY

7E10LAN8710A-EZK

ETHERNET

ETHERNET

CONNECTOR

RJ45

B02A

VIDEOSTREAMB02A

CA-A(00-14)

1M99

7

6

5

1M95

2

LED1 AD26

AE26

AA22DETECT2

AA26

AF19

RESET-STBYn

4xHDMI

CONNECTOR

AB22RESET-SYSTEM

AD21 ENABLE-3V3n

CONNECTOR

AC25LED2

1S02

54M

AF17

AE17

CONTROLB02E

CONTROLB02E

STANDBYB02G

HDMI_DVB02C

AD22AV1-BLK

AF20 STANDBY

AD19

AD23KEYBOARD

RC

LIGHT-SENSOR

AE19 TACH0

AB19 RESET-AUDIO

AF1 SENSE+1V1

AE25AV1-STATUS

BACKLIGHT-OUT

BACKLIGHT-BOOST

RESET-SYSTEMnAE4 B01KB02G

B03G

AC21 POWER-OK

B03B

B02G

B07A

B01E

7S20NCP303LSN28G

2INP

1OUTP

+3V3-STANDBY

GND

B02E

B02H POWER

7EC1SII9187ACNU

HDMISWITCH

B04A

1P00

1

68

PCMCIA

CONDITIONAL

ACCESS

UA_RX_0

UA_TX_1

P1_7

P6_4

P2_2

P2_7

P1_1

P2_6

P0_6

VDD_1V1

P2_3

XTAL_I

XTAL_O

P5_1

P5_O

P3_2

P3_3

P3_5

P3_4

CADC_2

CADC_3

RESET_IN

P1_2

W24RREF

HDMI_RX

P1_0

PWM_1

PWM_0

7F027F03

7F047F05

7F01

TO

POWER

SUPPLY

B04A

COMMONINTERFACE

TO

POWER

SUPPLY

+3V3-STANDBY

+5V

B04E

B03C

SDM

SPI-PROGAF22

AB20 FF04

FF29

18770_407_100217.ep s100217

RXD-UP

TXD-UP

Y23

Y24UART

SERVICE

CONNECTOR

AG1

AH5

RXD1-MIPS

TXD1-MIPS

LED-2

LED-1

1

2

3

4

5

6

7

8

1M20

7U43

ARX-HOTPLUG

1E06

2

3

1

AC22AV2-BLKB04A

AE24AV2-STATUSB04A

P2_0AC20LCD-PWR-ONn

B03H

RESET-STBYn

RESET-DVBS

AA15 SENSE+1V2B03DVDDA_1V2

AA18 RESET-DVBSB07AP0_1

AE18 RESET-ETHERNETnB04CP0_3

AF18 SEL-HDMI-ARCB02DP0_4

AE

Documents

Philips 37pfl7605h Ch q552.1e-La