Slide 1

Project mid presentation

Presented by : Olga Liberman & Yoav Shvartz Supervisor : Moshe Porian

28.1.2012

Symbol Generator: . ...1ContentsReminderTop ArchitectureMicro architectureSchedule : "

2IntroGenerating symbols on display screens is an essential operation these days. Commonly used in varies applications:

Mobile phonesTelevisionsMilitary applications

: .: .

3Reminder - SpecificationsGenerating symbols on display screen using:Cyclone II FPGA Host communication via UART protocolInternal communication via Wishbone protocolInput - Grayscale symbols 32 x 32 pixelssaved in external SDRAMOutput - Grayscale image resolution 640x480 pixelsMain clock freq. 133MHz VESA (monitor) freq. 40 MHz

: . . UART WISHBONE 133MHz Vesa4TX PathMemoryManagementRX Path

SDRAM ControllerWBSWBSWBMWBMWBSWBSDisplayControllerWBSHost(Matlab)

VGA Display

IS42S16400 SDRAMWBMWBMUARTUARTVESAWishboneINTERCONopcodeTop Architectureuart tx "" UART , UART TX UARTME frame finish WTME ME ....uart tx "" UART , UART TX UARTME frame finish WTME ME ....5123161718193212316171819321231617181932SDRAM 2^12 X 2^8 Symbol #1Symbol #2Symbol #N1323111113231313231323132SCREEN640X480Reminder - Interaction 0/1Address of the symbol in the SDRAM

XYOp-Code11111FIFO A/B20X256 bit Address of symbol (0,0) in the SDRAMAddress of symbol (14,19) in the SDRAMRAM 300X13 bitAddress of symbol (0,1) in the SDRAM :SDRAM . FIFO . 622222123161718193212316171819321231617181932111111323111113231313231323132FIFO AFIFO BSDRAMSCREEN2222211111 Toggeling FIFOs SDRAMFIFO FIFOVesa7TX PathMemoryManagementRX Path

SDRAM ControllerWBSWBSWBMWBMWBSWBSDisplayControllerWBSHost(Matlab)

VGA Display

IS42S16400 SDRAMWBMWBMUARTUARTVESAWishboneINTERCONTop Architecture8Micro ArchitectureWBSWBMOpcode UniteOPURAM

OPU -FIFO

Re-Mng

FIFO A

FIFO B

MUXDual Clk FIFO

SDRAMMemoryRegVESAController - 133 MHz 40 HzWBS busData busWrite busRead busRe Mng ValidVsyncWBM busReq_in_trgWrite busWrite busData A Data B Data Data MUX SelVESA BusOpcode

Rd _en A/B (- , ): . OPU 3 8 opcode 1. OPU-FIFO . Vsync , OPU-FIFO RAM . , Re_Mng_Valid .Re_Mng VESA: SDRAM Memory Reg SDRAM, FIFO A/B , DC FIFO, VESA Controller . VESA Controller Req_in_trg Re_Mng "" . 9Micro Architecture - OPUGoal: 1.Unites every 3 packs of MPD into 1 opcode by a FSM.2.Sending the changes to OPU - FIFO * When we reach state MPD3 then we have 1 opcode (24 bit).* MPD = Message Pack Data MPD 1

MPD 2

MPD 3

opcode

MPD= Message Pack Data (1 pack of 8 bits that is transmitted in the Payload field. There can be more than 1 MPD in Payload field and the number of MPD is represented by the field Data Length in the transmitted message. MPD3 OPU-FIFO10Micro Architecture OPUpins:Wbs_adr_i [9..0]Wbs_tga_i [9..0]Wbs_dat_i [7..0]Wbs_cyc_iWbs_stb_iOpcode UniteWbs_ack_oWbs_stall_oWbs_err_oClk_133resetOpcode_fifo_wr_enOpcode_fifo_data_in[23..0]Micro ArchitectureWBSWBMOpcode UniteOPURAM

OPU -FIFO

Re-Mng

FIFO A

FIFO B

MUXDual Clk FIFO

SDRAMMemoryRegVESAController - 133 MHz 40 HzWBS busData busWrite busRead busRe Mng ValidVsyncWBM busReq_in_trgWrite busWrite busData A Data B Data Data MUX SelVESA BusOpcode

Rd _en A/B (- , ): . OPU 3 8 opcode 1. OPU-FIFO . Vsync , OPU-FIFO RAM . , Re_Mng_Valid .Re_Mng VESA: SDRAM Memory Reg SDRAM, FIFO A/B , DC FIFO, VESA Controller . VESA Controller Req_in_trg Re_Mng "" . 12Micro Architecture OPU FIFOGoal:Stores commands from the OPU.Sending the changes to RAM.Size : 300 x 24 (rows x bits)RAM_adr_wr[8..0] = 20*x + y Com_type = 0 (remove a symbol) RAM_data_in[0..13]= "00"Com_type = 1(add a symbol) RAM_data_in [0..13]= "com_add".0/1Com add

XYThe Opcode FIFO receives the opcodes from the Opcode Unite block. It stores the opcodes until the VSYNC of the VESA is active. Then, the opcodes will be written to the calculated row in the RAM: RAM_adr_wr[8..0] = 20*x + y.If com_type = 0 (remove a symbol) then RAM_data_in[0..13]= "00"Else (add a symbol) RAM_data_in [0..13]= "com_add".* Com_type = the first bit indicating if we want to add or remove the symbol

13Micro Architecture OPU FIFOpins:op_fifo_wr_enop_fifo_data_in[23..0]Opcode FIFO300 x 24 (row x bit)(VSYNC) op_fifo_rd_enClk_133resetRAM_adr_wr[8..0]RAM_wr_enRAM_data_in[13..0]Op_fifo_emptyOp_fifo_fullOp_fifo_used[8..0]rd_mng_enMicro ArchitectureWBSWBMOpcode UniteOPURAM

OPU -FIFO

Re-Mng

FIFO A

FIFO B

MUXDual Clk FIFO

SDRAMMemoryRegVESAController - 133 MHz 40 HzWBS busData busWrite busRead busRe Mng ValidVsyncWBM busReq_in_trgWrite busWrite busData A Data B Data Data MUX SelVESA BusOpcode

Rd _en A/B (- , ): . OPU 3 8 opcode 1. OPU-FIFO . Vsync , OPU-FIFO RAM . , Re_Mng_Valid .Re_Mng VESA: SDRAM Memory Reg SDRAM, FIFO A/B , DC FIFO, VESA Controller . VESA Controller Req_in_trg Re_Mng "" . 15Micro Architecture RAMpins:RAM_adr_wr[8..0]RAM_wr_enRAM_data_in[13..0]RAM300 x 14 (row x bit)RAM_adr_rd[8..0]RAM_rd_enRAM_data_out[13..0]RAM_out_validClk_133resetMicro ArchitectureWBSWBMOpcode UniteOPURAM

OPU -FIFO

Re-Mng

FIFO A

FIFO B

MUXDual Clk FIFO

SDRAMMemoryRegVESAController - 133 MHz 40 HzWBS busData busWrite busRead busRe Mng ValidVsyncWBM busReq_in_trgWrite busWrite busData A Data B Data Data MUX SelVESA BusOpcode

Rd _en A/B (- , ): . OPU 3 8 opcode 1. OPU-FIFO . Vsync , OPU-FIFO RAM . , Re_Mng_Valid .Re_Mng VESA: SDRAM Memory Reg SDRAM, FIFO A/B , DC FIFO, VESA Controller . VESA Controller Req_in_trg Re_Mng "" . 18Micro Architecture Rd_MngGoal: The "brain" of the Symbol Generator block Functionality:Calculating relevant row in the RAM and receiving data. Calculating row and column in the SDRAM (where the symbol sits).Managing the toggling between the two FIFOs, using FSM. " 19Micro Architecture Rd_MngFSM:

IDLEWRITE A READ BresetREAD A WRITE BRAM updatedRd_mng_enWRITE AREAD BReq_in_trg(req_in_trg)AND(NOT last row of the frame)(req_in_trg)AND(last row of the frame)req_in_trgFinished deliver last row to DC FIFO Toggeling: idle. RAM " OPU-FIFO , Rd_Mng SDRAM FIFO A. VESA (req_in_trg), FIFO . toggling VEAS, FIFO B.

20Micro Architecture Rd_Mngpins:RAM_data_out[13..0]RAM_out_validWbm_dat_i[7..0]Read_Manager(=RM)RAM_rd_enRAM_adr_rd[8..0]Wbm_stall_iWbm_ack_iWbm_err_iWbm_add_o[9..0]Wbm_tga_o[9..0]Wbm_cyc_oWbm_std_oClk_133resetReceiving data from SDRAMWbm_dat_o[7..0]Requesting data from SDRAMFIFO_A_rd_enFIFO_A_data_in[7..0]FIFO_A_wr_enFIFO_B_rd_enFIFO_B_data_in[7..0]FIFO_B_wr_enreq_in_trgMicro ArchitectureWBSWBMOpcode UniteOPURAM

OPU -FIFO

Re-Mng

FIFO A

FIFO B

MUXDual Clk FIFO

SDRAMMemoryRegVESAController - 133 MHz 40 HzWBS busData busWrite busRead busRe Mng ValidVsyncWBM busReq_in_trgWrite busWrite busData A Data B Data Data MUX SelVESA BusOpcode

Rd _en A/B (- , ): . OPU 3 8 opcode 1. OPU-FIFO . Vsync , OPU-FIFO RAM . , Re_Mng_Valid .Re_Mng VESA: SDRAM Memory Reg SDRAM, FIFO A/B , DC FIFO, VESA Controller . VESA Controller Req_in_trg Re_Mng "" . 22Micro Architecture FIFO A/BGoal: The toggled FIFOs Size: 20x256 bitsPins: " 23Micro ArchitectureWBSWBMOpcode UniteOPURAM

OPU -FIFO

Re-Mng

FIFO A

FIFO B

MUXDual Clk FIFO

SDRAMMemoryRegVESAController - 133 MHz 40 HzWBS busData busWrite busRead busRe Mng ValidVsyncWBM busReq_in_trgWrite busWrite busData A Data B Data Data MUX SelVESA BusOpcode

Rd _en A/B (- , ): . OPU 3 8 opcode 1. OPU-FIFO . Vsync , OPU-FIFO RAM . , Re_Mng_Valid .Re_Mng VESA: SDRAM Memory Reg SDRAM, FIFO A/B , DC FIFO, VESA Controller . VESA Controller Req_in_trg Re_Mng "" . 24