“PROGRAMMABLE PATTERN GENERATOR”

MID-TERM PRESENTATION

Students :Or Shperling & Liron Ulman

Instructor :Ina Rivkin

DSPReceiver :

Analogue Pre-Processing

D/A D/AD/AD/A

A/D

Trigger Out

SystemControllerTrigger in

Start

Stop

X t X t 5 GHz

Low Frequency

CONFIG

DATA

Our design

ML605 Board

Project’s Goals & Definitions

Designing an On-Line configurable “Pattern Generator” using 2 implementations:(1) Xilinx IP-Core DDS (Direct Digital

Synthesizer).(2) A memory which will be use as a LUT for the pattern values, with a logic which will govern the memory output.

User’s trigger will initiate sine output. Test the implementations on ML605 platform.

Project’s requirements (1)

Configuration phase- Inserting required Frequency and initial phase.

‘Start’ initiates system iteration. Some delay after ‘Start’, our system is ready for trigger.

‘Trigger in’ is 1KHz PRI [Pulse Repetition Interval].

1st ‘Trigger in’ initiates 4 channels of sine signal with different frequency and different phase.

Every ‘Trigger in’ reset the phase of all channels to the initial phase.

‘Stop’ means : “End of current iteration”.

Project’s requirements (2)

Trigger_out is an output for the A/D to inform the Sine is ready.

Trigger_out(t) = Trigger_in (t – (T1 + TDM ))T1 = Our module delay from triggerTDM = Analogue receiver delay

At least 32 sampling points per sine period.

Data width according to D/A width – typically 24 bits.

Frequencies analysis Signal resolution and clock frequency

dictates maximal sine frequency :

Our clock is produced by a DCM unit which is fed by 66 MHz board crystal’s “User Clock”.

We’ve examined some clock frequency till satisfactory results have been achieved.

sin 32clk clkf f

fsamples per period

Implementation

First Implementation – using a built-in library unit- Direct Digital Synthesizer (DDS)- to compute the sine.

Second Implementation- our own implementation and logic design, using memory units and logic.

SINE[0..23]

PHASE_OUT[0..4]CE

CLK

RDY

SCLR

WE

REG_SELECT

DATA[0..4]

DDS Module

DCM

CLK_IN

CLK_OUT

DDS Design’s high level

Controller

START

TRIG_IN

RESET

STOP

CE

SCLR

WE

REG_SELECT

STATE

ProgrammableDelay

STATE

TRIG_OUTTRIG_IN

RDY

SINE

PHASE_OUT

X4

CONFIG

Controller States Machine

Idle

Trig=‘1’

Trig = ‘1’

Run Reset Phase

Wait for Trig

Config

Stop = ‘1’

State= “000”

State= “011”

State= “010”

SCLR=‘1’

State= “100”

State= “001”CE = ‘1’

Start = ‘1’Config = ‘1’

CE = ‘1’

CE = ‘1’CE = ‘1’

CE = ‘0’

WE = ‘1’

SCLR=‘1’

Frequency testing -200 MHz clock, sampled at

400 MHz – runs on board

Sine is too noisy.

132 MHz clock, sampled at 264 MHz – runs on board

Noise exists but is not significant – good enough.

Conclusions Maximal frequency is :

Applying higher frequency will be possible only if we trade-off resolution or suffering significant signal noise at the D/A’s inputs.

sin

1324.125

32

MHzf MHz

Logic simulation

Sine generator – Memory implementation

0

sin(π/4)

0x00000000x00000040x0000008

Sine

Whole sine information found within ¼ of a period.

Addresses jump will be determined by initialized frequency.

Initial address will be determined by initialized phase

SINE[0..23]

PHASE_OUT[0..4]

CLK

Memory

Addresses counter

Frequency

Address

Memory implementation – General Design

STATE

RDY

SINE

PHASE_OUTX4

ADDRESS

Phase

Controller

START

TRIG_IN

RESET

STOPSTATE

CONFIG

From User

Controlsignals

From User

Action Items from PDR ML605 board interface with “outer

world” :(1) 2 Mezzanine connectors, FMC-LPC,

FMC-HPC, can handle 250 MHz LVDS.(2) No Serializer - Deserializer (SerDes) is available.

2x FPGA Mezzanine Card (FMC) connector

Current Status

Final phases of DDS implementation – successful logic simulation with 4 channels. Now- board implementation

One channel was tested successfully on board

Gantt Chart

Finish design based on DDS module

Perfomance testing on board

Design sine generator based on memory module

Memory controller design

Integration and Logic Simulation and board implementation

Perfomance testing on board

Mid Term14/4/2013

Final1/7/2013