Registers and Counters - National Chiao Tung Universityviplab.cs.nctu.edu.tw/course/DCD2010_Fall/DCD_Lecture_06.pdf · Registers and Counters Lan-Da Van (范倫達), ... 4-bit register

Digital Circuit Design

Registers and Counters

Lan-Da Van (范倫達), Ph. D.

Department of Computer Science

National Chiao Tung University

Taiwan, R.O.C.

Fall, 2010

[email protected]

http://www.cs.nctu.edu.tw/~ldvan/

Lecture 6


Lan-Da Van DCD-06-2

Outlines

Registers

Shift Registers

Ripple Counters

Synchronous Counters

Other Counter

Lecture 6


Lan-Da Van DCD-06-3

Registers

Clocked sequential circuits a group of flip-flops and combinational gates

connected to form a feedback path

Flip-flops + Combinational gates

(essential) (optional)

Register: a group of flip-flops

gates that determine how the information is transferred into the register

Counter: a register that goes through a predetermined sequence of

states

Lecture 6


Lan-Da Van DCD-06-4

Four-Bit Register

An n-bit register

n flip-flops capable of

storing n bits of binary

information

4-bit register

Lecture 6


Lan-Da Van DCD-06-5

Four-bit Register with Parallel Load

Lecture 6


Lan-Da Van DCD-06-6

Shift Registers

Shift register

a register capable of shifting its binary information in one or

both directions

Simplest shift register

11

01 1

01

10

1

Four-bit shift register

Lecture 6


Lan-Da Van DCD-06-7

Serial transfer vs. Parallel transfer

Serial transfer

Information is transferred one bit at a time

shift the bit out of the source register into the destination

register

Parallel transfer:

All the bits of the register are transferred at the same time

Transfer

Lecture 6


Lan-Da Van DCD-06-8

Serial Transfer from Reg A to Reg B

1 0 1 1 0 0 1 0

Lecture 6


Lan-Da Van DCD-06-9

Serial Transfer from Reg A to Reg B

Lecture 6


Lan-Da Van DCD-06-10

Serial Adder Using D Flip-Flops

4-Bit SR

4-Bit SR

Lecture 6



Serial Adder Using D Flip-Flops

Clk

SC

SI_B

SO_B

1 1 1 10 0 0 0

1 1 1 10 0 0 0

SO_A 1 10 0

S 0 0 0 1

C 1 1 1 0

0101+0011=1000

Lecture 6



JQ = x y

KQ = x y = (x + y)

S = x y Q

Serial Adder Using JK Flip-Flops

Lecture 6



Ci

Second form of serial adder

Serial Adder Using JK Flip-Flops

Lecture 6



Universal Shift Register

Shift Register

Unidirectional shift register

Bidirectional shift register

Universal shift register:

has both direction shifts & parallel load/out capabilities

Capability of a universal shift register:

1. A clear control to clear the register to 0.

2. A clock input to synchronize the operations.

3. A shift-right control to enable the shift right operation and the serial input and output lines associated with the shift right.

4. A shift-left control to enable the shift left operation and the serial input and output lines associated with the shift left.

5. A parallel-load control to enable a parallel transfer and the nparallel input lines associated with the parallel transfer.

6. n parallel output lines.

7. A control state that leaves the information in the register unchanged in response to the clock.

Lecture 6



Four-Bit Universal Shift Register

Clear s1 s0 A3+ A2+ A1+ A0+ (operation)

0 × × 0 0 0 0 Clear

1 0 0 A3 A2 A1 A0 No change

1 0 1 sri A3 A2 A1 Shift right

1 1 0 A2 A1 A0 sli Shift left

1 1 1 I3 I2 I1 I0 Parallel load

Lecture 6



A0

Four-Bit Universal Shift Register

Lecture 6



Ripple Counters

Counter:

a register that goes through a prescribed sequence of states

upon the application of input pulses

Input pulses: may be clock pulses or originate from some

external source

The sequence of states: may follow the binary number

sequence ( Binary counter) or any other sequence of states

Categories of counters

Ripple counters: The flip-flop output transition serves as a

source for triggering other flip-flops.

no common clock pulse (not synchronous)

Synchronous counters: The CLK inputs of all flip-flops

receive a common clock.

Lecture 6



Four-Bit Binary Ripple Counter

1 0 0 1

1 0 1 0

1 0 1 11 1 0 0

1 1 1 1

1 1 0 1

0 0 0 0

A simple complement flip-flop

can be obtained:

from a JK flip-flop with the J and

K inputs tied together

from T flip-flop

use a D flip-flop with the

complement output connected

to the D input.

Example: 0011=>0100

Lecture 6



Four-Bit Binary Ripple Counter

Lecture 6



Timing Analysis of Binary Ripple Counter

Count

A1

A2

1 1

A3

A0 1 1 10 00 1 100 10

0 0 1 10 0 1 10 0

0 0 0 0 1 1 1 1 0 0 0 0

0 0 0 0 0 0 0 0 1 1 1 1

Lecture 6



BCD Ripple Counter

Hint1: Q1 changes state after each clock pulse.

Hint 2: Q2 complements every time Q1 goes from 1 to 0 as long as Q8=0. When Q8becomes 1, Q2 remains at 0.

Hint 3: Q4 complements every time Q2 goes from 1 to 0.

Hint 4: Q8 remains at 0 as long as Q2 or Q4 is 0. When both Q2 and Q4 become 1, Q8complements when Q1 goes from 1 to 0. Q8is cleared on the next transition of Q1.

Lecture 6



Three-Decade BCD Ripple Counter

Lecture 6




Synchronous counter

A common clock triggers all flip-flops simultaneously.

Design procedure

apply the same procedure of sync seq ckts

Sync counter is simpler than general sync seq ckts

Lecture 6


Lan-Da Van DCD-06-24Four-bit synchronous binary counter

Four-Bit Sync. Binary Counter

up

down

down A'0

down A'0 A'1

down A'0 A'1 A'2

up A0

up A0 A1

Four-bit up-down binary counter

Lecture 6



Timing Analysis of Sync. Binary Counter

Clk

A1

A2

1 1

A3

A0 1 1 10 00 1 100 10

0 0 1 10 0 1 10 0

0 0 0 0 1 1 1 1 0 0 0 0

0 0 0 0 0 0 0 0 1 1 1 1

CE

Lecture 6



Sync. BCD Counters

Simplified functions: Need to consider other unused 6 cases

Lecture 6



Sync. BCD Counters

T

C

T

C

1 T

C

T

C

Q1 Q2 Q4 Q8

CLK

y

Lecture 6



Four-Bit Sync. Binary Counter with Parallel Load

Lecture 6



Four-Bit Sync. Binary Counter with Parallel Load

Lecture 6



Generate any count sequence:

E.g.: BCD counter Counter with parallel load

Sync. BCD Counter with Parallel Load

Lecture 6



Other Counters

Counters:

can be designed to generate any desired sequence of states

Divide-by-N counter (modulo-N counter)

a counter that goes through a repeated sequence of N states

The sequence may follow the binary count or may be any other arbitrary sequence

n flip-flops 2n binary states

Unused states

states that are not used in specifying the FSM

may be treated as don’t-care conditions or may be assigned specific next states

Self-correcting counter

Ensure that when a ckt enters one of its unused states, it eventually goes into one of the valid states after one or more clock pulses so it can resume normal operation.

Analyze the ckt to determine the next state from an

unused state after it is designed

Lecture 6



An example

Two unused states: 011 & 111

The simplified flip-flop input eqs:

JA = B, KA = B

JB = C, KB = 1

JC = B, KC = 1

Counters with Unused States

Lecture 6



Counter with Unsigned States

Lecture 6



Ring counter:

a circular shift register with only one flip-flop being set at any

particular time, all others are cleared

(initial value = 1 0 0 … 0 )

The single bit is shifted from one flip-flop to the next to

produce the sequence of timing signals.

T0 T1 T2 T3

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

1 0 0 0

Ring Counter

Lecture 6



Application of counters

Counters may be used to generate timing signals to control the sequence of

operations in a digital system.

Approaches for generation of 2n timing signals

Method 1: a shift register with 2n flip-flops

Method 2: an n-bit binary counter together w/ an n-to-2n-line decoder

Ring Counter

Lecture 6



Johnson Counter

Ring counter vs. Switch-tail ring counter Ring counter

a k-bit ring counter circulates a single bit among the flip-flops to provide k distinguishable states.

Switch-tail ring counter

is a circular shift register w/ the complement output of the last flip-flop connected to the input of the first flip-flop

a k-bit switch-tail ring counter will go through a sequence of 2kdistinguishable states. (initial value = 0 0 … 0)

Disadv. of the switch-tail ring counter if it finds itself in an unused state, it will persist to circulate in

the invalid states and never find its way to a valid state.

Johnson counter a k-bit switch-tail ring counter + 2k decoding gates

provide outputs for 2k timing signals

Lecture 6



Johnson Counter

Lecture 6



Conclusion

From this lecture, you have learned the

follows: Registers

Shift Registers

Ripple Counters


Other Counter

Documents

Registers and Counters - National Chiao Tung Universityviplab.cs.nctu.edu.tw/course/DCD2010_Fall/DCD_Lecture_06.pdf · Registers and Counters Lan-Da Van (范倫達), ... 4-bit register