RENO Electronics- QBEE -

장 지 승 ( 전남대학교 )

RENO Collaboration Meeting, 2008.10.10.

Contents

1. QBEE 의 소개와 성능2. DAQ 구성

- Master Clock 소개- Online computer setup

3. 진행상황과 계획

QBEE - QTC Based Electronics with Ethernet -

• Super-Kamiokande 를 위해 동경대의 ICRR 에서 개발• 개발목표1. Stable DAQ system for next 10~20 years

ATM (Analog Timing Module from KEK) was used for long time2. Better data quality

1) Reflection signal and Temperature dependenceA dead time for mu-decay detection (~us interval events)2) Charge dynamic range and Energy resolutionlower energy(~3MeV) solar neutrinos to multi-GeV or higher energy neutrinos

3. Recording every hit of PMTAnti-neutrino events for supernova relic neutrino search by detecting 200us delayed signal

4. High speed signal processing Nearby galactic supernova burst events

Dead time fre

e !!

High sensitivity !!

High speed !!

Overview of QBEE12

PM

Ts12

PM

Ts

….….

8QTC(Charge to Time converter)

4TDC(Time to Digital Converter)

Power supply DC

RJ4

5R

J45

Computer

Master Clock• 60MHz clock• TDC reset • TRG ID• Event#

100Mbps

100Mbps

Ethernet card

FPGA

Hit timing

Charge

• TDC (ATLAS Muon TDC)- Digitizes the each edge time

• FPGA (DSM, SIC etc)- Calculates the digitized hit timing and integrated charge

• QTC

• Built-in Calibration pulser & Temperature sensor

Specification of QBEEbased on IWATSU manual

1. The number of the ch. : 24ch2. Charge dynamic range : 0.2-2500pC (1250 p.e.), 3 gain range (Small ~51pC, Medium 51~357pC, Large 357~25

00pC3. Charge Linearity : +/- 1%

4. Charge resolution: ~0.1pC(.05p.e.), Timing resolution: ~0.15nsec5. Temperature dependence (per degree) Gain variation : 0.4% Pedestal variation : less than 0.15pC Charge accuracy after pedestal subtraction : less than 0.15% Timing variation : less than 0.02nsec

Pedestal temperature coefficient

650

670

690

710

730

750

770

790

810

830

850

0 20 40 60 80

Input voltage [mV]

QT

CO

UT

[ns

]

Temp=29deg

Temp=34deg

6. Processing speed : 900ns/hit7. Discriminator : 0 ~ -1.7mV, 0~3.4mV, 0.-11.9mV8. Noise level : Noise hit rate < 10Hz @ -0.3mV DSC

9. Cross talk hit : less than 1/1000 between ch. @-0.6mV DSC

Time

0s 100ns 200ns 300ns 400ns 500nsV(R6:1)-0.16m -0.0003

-4.0m

-3.0m

-2.0m

-1.0m

0

1.0m

2.0m

PMTsignal

-0.3mV

cross-talk

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 0.2 0.4 0.6 0.8 1

Input voltage [V]

effi

cien

cy

ch2-->ch1

ch2-->ch0

ch1-->ch2

ch1-->ch0

ch0-->ch1

ch0-->ch2

Reflection<-60dB

TD× 2

TD is delay time of Coaxial-cable

10. Reflection coefficient : less than 1/1000 (-60dB) @ 20inch PMT and 70m coaxial cable

11. FIFO memory size : 1.5MB12. Power consumption (Maximum)

+5.2V/1.6A, -5.4V/0.7A, +8/0.81A, -8V/0.3A, +15V/0.1A(DB)less than 24W

DAQ 구성

Master Clock Module

TRG module

Sync. Out

Distributer

• RENO requirement – 18 QBEEs per 1 detector

@ SuperK

ComputerFla

t cable

60KHzSerial signal( TRG ID &Event # etc. )

60MHz clockTRG ID, event#

QBEE output 100Mbps

100Mbps

MCLK output specification

Output via 100Mbps Ethernet cable (1,2) pair : 60 MHz clock (5,6) pair : TDC reset + Trigger ID + 32 bit event

# (3,4) and (7,8) pairs : not used

Spec. of serial signal [ 1 bit = 1 clock, total 38 clocks = 633 nsec ]

Header (always 1)

Trigger on/off + TDC reset on/off• Trigger w/o TDC reset (10)• Trigger w/ TDC reset (11)• TDC reset only (No Trigger) (01)

Trigger (Narrow/Wide + Pedestal + Split)

32 bit event #

60 MHz clock

Serial signal

Start at a negative edge of the clock

110 100 00000000000000100110110000011001

60KHz Serialized signal633nsec

60MHz clock

• Example of Master Clock Output

Header (always 1)

Trigger on/off + TDC reset on/off

Trigger (Narrow/Wide + Pedestal + Split)

32 bit event #

Serial signal

Storage

100Mbps/QBEE x 18 LAN SWITCH

SISCO SYSTEMCatalyst 2960G Series

1Gbps x 3

……

Computer

FujitsuPGR10317L-D

QBEE24 PMTs

LAN SWITCH

Computer...

MergerSoftware trig.

ComputerVME-

TRG Module

collectorsenderBit3

1Gbps(?)

collectorsortersender

Computer

Data flow manager

Computer

Organizer

Online computer setup with QBEEbased on SuperK online system

Master Clock Module

Distributor

Flat cable

Sync. Out

……

18 output

• Each computer has 4 core• is Ethernet cable

Front End Computer

24PMTs

QBEE

FastEthernet

18 QBEEs

QBEE

QBEE

QBEE

QBEE

Sender

Collector

Collector

Collector

Collector

Collector

Sorter

Front end computer

1.5MB/sec/QBEE

27MB/sec

Merger

• Schematic view of data flow in front end computerbased on SuperK online system

Software for this process was provided by Iwatsu and SuperK online group.

Storage

100Mbps/QBEE x 18 LAN SWITCH

SISCO SYSTEMCatalyst 2960G Series

1Gbps x 3

……

Computer

FujitsuPGR10317L-D

QBEE24 PMTs

LAN SWITCH

Computer...

MergerSoftware trig.

ComputerVME-

TRG Module

collectorsenderBit3

1Gbps(?)

collectorsortersender

Computer

Data flow manager

Computer

Organizer

Online computer setup with QBEE

Master Clock Module

Distributor

Flat cable

Sync. Out

……

18 output

• Each computer has 4 core• is Ethernet cable

Front End Computer

Data from the front-end PC

Merger

Combine the data from each FEPC by using the HW trigger number.

• The software trigger system

1 2 3 4 5 6 7 8 9HW trig. no.

1 2 3 4 5 6Event no.

• The Merger system

#of e

ven

ts

MCLK & Distributor

Power Supply for TKO

LAN switch

18 QBEEs in TKO

FAN

VME w/ TRG

Electronics setup for 1 detector

6 PC

10 H

V sp

litte

r

FAN

PMTHV supply

NIM

개수 구입처 진행상황QBEE 50 IWATSU 전량 서울대 도착Ethernet card 50 Boston Univ. 5 개 -11 월 초 SuperK 에서

나머지 - 차후 보스톤에서Master Clock 4 IWATSU 10 월 말 도착예정TRG Module 4 IWATSU 10 월 말 도착예정Distributer 4 IWATSU 10 월 말 도착예정TKO crate 6 KEK

REPIC ( 수리 )3 개 수리요청 , 수리 후 도착예정부족분은 KEK 에 문의중

TKO power supply

4 KEK 전량 확보 ,수리 문의중

Pulse Gen.

FI/FO – 24ch.

11 월 중 QBEE test 시작을 목표로 하고 있음

진행상황과 계획