Abhishek Kumar A-293 3rd floor Mobile: +91-8468997221New Ashok Nagar, New Delhi E-Mail: abhi17.sgi@gmail.com

OBJECTIVE

To work in an intellectual Environment focusing on VLSI and Layout areas, where I can utilized my skills to achieving company’s goals and objectives.

EXPERIENCE

3+ years of experience in design Layout for memory. Memory Circuit, Memory Architecture Memory Compilers and having experience of DRC, LVS instance level, chcells Extraction, Lefcheck, antenna check, Miniarray, ERC, IR, EM checks and QA .Done projects for following foundries: TSMC 28, SMIC 40, UMC40, Intel 14, Intel 10, GF 14, Samsung 14nm & Samsung 10 nm.During Work at Synopsys I had delivered many test chips & Memory compilers. Possesses Knowledge of memory architecture, Memory layout and circuit design & dealing with CAD issue.

SYNOPSYSPeriod : Nov 2012 – PresentDesignation : Analog & Mixed signal design engineer

AWARDS

For Successful completion of Intel 14nm Program.

PROJECT EXPERIENCE (Nov 2012 to Present)

Project (Maintenance) : 1Organization : Synopsys India Pvt Ltd Duration : 2 Months. Nov2012-Dec2012Technology : TSMC28nm HD1PTools : Synopsys: Custom Designer, Caliber: DRC/LVS, ICV: DRC/LVSRole : DRC, LVS, VERC, ANTENNA, LefCheck.

Project (Maintenance) : 2 Organization : Synopsys India Pvt Ltd Duration : 3 Months. Jan2013-Mar2013Technology : SMIC40nm HDSPTools : Synopsys: Custom Designer, Caliber: DRC/LVS, Hercules: DRC/LVSRole : Layout owner, Leaf cells development, ECOs, DRC, LVS, VERC,

ANTENNA, LefCheck, Full compiler QA.

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Project (Scratch) : 3Organization : Synopsys India Pvt Ltd Duration : 12 Months. April2013-Mar2014Technology : Intel14nm HSRF1PTools : Synopsys: Custom Designer, ICV: DRC/LVS/DENSITY/VERC/ASICRole : Leaf cell development, DRC, LVS, MIniarrays, ANTENNA, Instance level DRC/ LVS/DENSITY, Extraction, LefCheck.

Project (Maintenance) : 4Organization : Synopsys India Pvt Ltd Duration : 4 Months. Oct2013-Jan2014Technology : UMC40nm HD1PTools : Synopsys: Custom Designer, Caliber: DRC/LVS, Hercules: DRC/LVSRole : Layout owner, Leaf cell development, ECOs, DRC, LVS, instance level

DRC/LVS, VERC, EM- IR fixes, ANTENNA, Lefcheck, Miniarrays, Full compiler QA.

Project (Scratch) : 5Organization : Synopsys India Pvt Ltd Duration : 10 Months. April2014-Jan2015Technology : SS/GF14nm HD1P (LPE, LP, LPP)Tools : Synopsys: Custom Designer, Caliber: DRC/LVS,

ICV: DRC/LVS/VERC, ANTENNA.Role : Leaf cell development, DRC, LVS, instance level LVS/DRC, VERC

Fixes, EM-IR fixes, ANTENNA, DFM, Extraction, & Lefcheck,Ownership of full compiler DRC, DFM and full QA.

Project (Scratch) : 6Organization : Synopsys India Pvt Ltd Duration : 2 Months. Feb2015-Mar2015Technology : Intel14nm uhdrf2p_LP, hsrf1p_LPTools : Synopsys: Custom Designer, ICV: DRC/LVS /VERC/ASIC/DENSITYRole : Supporting role in DENSITY & DRC fixes to achieve the

compiler dead line.

Project (Scratch R&D) : 7Organization : Synopsys India Pvt Ltd Duration : 2 Months. April2015-May2015 Technology : Intel10nm HSRF1PTools : Synopsys: Custom Designer, ICV: DRC/LVS/DENSITYRole : Leaf cell development, DRC, LVS, Area Comparison

Project (Scratch) : 8Organization : Synopsys India Pvt Ltd Duration : 2.5 Months. Jun2015-Aug2015Technology : SS10nm UHD2PRFTools : Synopsys: Custom Designer, ICV: DRC/LVSRole : Leaf cell development, DRC, LVS, Extraction.

Project (Scratch) : 9Organization : Synopsys India Pvt Ltd

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Duration : 5 Months & cont. Aug2015-PresentTechnology : Intel10nm HSRF1P_HPC1&HPC2 (On Going)Tools : Synopsys: Custom Designer, ICV: DRC/LVS/DENSITYRole : Leaf cell development, DRC, LVS, Density, Extraction.

TECHNICAL SKILLS

Layout leaf cell development, DRC, LVS, DFM, ERC, Lefcheck, Miniarray & Antenna. Instance LVS and DRC. EM-IR layout corrections. Good knowledge of UNIX & LINUX.

STRENGTHS Demonstrated ability to work in a demanding team-oriented environment. Proven ability to remain calm, focused and organized to deliver results on time

when under pressure. Self –starter with an ability to learn things quickly. Competent to handle any adverse situation. Good understanding of the concepts used in Memory Layout.

EDUCATIONAL AND PROFESSIONAL CREDENTIALS

B.Tech (Electronics & Communication) 2008-12 Sharda Group of institutions UPTU – First DivisionHIGHER SECONDARY 2006 U.P. Board – First DivisionSENIOR SECONDARY 2004 U.P. Board – First Division

PERSONAL DETAILS

Date of Birth : 21st April 1989 Languages : Hindi & English Nationality : Indian Marital Status : Single Current Address : A-293 3rd floor New Ashok Nagar, New Delhi- 110096 Permanent Address : Dheeraj Prasad Gupta, Kashipur S.R.N Bhadohi U.P -

221401

Date: Name: Abhishek Kumar

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