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הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל. המעבדה למערכות ספרתיות מהירות. Midterm report Project name:. Satellite Inner communication – SpaceWire & CAN Bus. By: Michael Tsitrin , Asaf Modelevsky Instructor: Ina Ravkin. Goals to accomplish in the Project. - PowerPoint PPT Presentation
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Spring 08-Winter 09 semester Spring 08-Winter 09 semester
Satellite Inner communication – Satellite Inner communication – SpaceWire & CAN BusSpaceWire & CAN Bus
By: Michael Tsitrin, Asaf ModelevskyBy: Michael Tsitrin, Asaf Modelevsky
Instructor: Ina RavkinInstructor: Ina Ravkin
הטכניון - מכון טכנולוגי לישראל
הפקולטה להנדסת חשמל
המעבדה למערכות ספרתיות מהירות
Midterm report
Project name:
Spring 08-Winter 09 semester Spring 08-Winter 09 semester
Goals to accomplish in the ProjectGoals to accomplish in the Project
Implement a SpaceWire host interface to the Amba Implement a SpaceWire host interface to the Amba AHB bus of a SoPC system with Leon3 processor. AHB bus of a SoPC system with Leon3 processor. This host will connect to SpaceWire port that is This host will connect to SpaceWire port that is already exists.already exists.
Simulate the implementation in Modelsim.Simulate the implementation in Modelsim. Test the SpaceWire core in a closed loop.Test the SpaceWire core in a closed loop. Test the SpaceWire core by communicating with Test the SpaceWire core by communicating with
another system using SpaceWire physical link.another system using SpaceWire physical link.
Spring 08-Winter 09 semester Spring 08-Winter 09 semester
The LEON3 system including SpaceWire CoreThe LEON3 system including SpaceWire Core
AMBA AHB
SW port descriptionSW port description
The SW port follows the E50-12A specifications for a SpaceWire The SW port follows the E50-12A specifications for a SpaceWire Link.Link.
The SW port provides a physical link interface towards the outside The SW port provides a physical link interface towards the outside world and a control interface toward the host in which the port relies.world and a control interface toward the host in which the port relies.
The Network Level in which the SpaceWire port operates is The Network Level in which the SpaceWire port operates is “Network Level 2” (Character Level).“Network Level 2” (Character Level).
Therefore, such a SpaceWire port can be commanded to transmit Therefore, such a SpaceWire port can be commanded to transmit only SpaceWire characters. only SpaceWire characters.
The SW design was developed entirely in a XILINX environment The SW design was developed entirely in a XILINX environment and implemented by using XILINX library IP’s.and implemented by using XILINX library IP’s.
Spring 08-Winter 09 semester Spring 08-Winter 09 semester
The SW port we integrate to the systemThe SW port we integrate to the system
Spring 08-Winter 09 semester Spring 08-Winter 09 semester
The SW port architectureThe SW port architecture
Spring 08-Winter 09 semester Spring 08-Winter 09 semester
Current stage of implementation: Minimal SystemCurrent stage of implementation: Minimal System
Spring 08-Winter 09 semester Spring 08-Winter 09 semester
AM
BA
AH
B S
LA
VE
BU
S
Ho
st i
nte
rfac
e
(Fro
m A
HB
bus
to S
W p
ort) SW Port
Oth
er S
W l
ink
inte
rfac
e
(Already exists)
Our mission
We start our implementation with basic configuration: SW AHB slave interface, with small packets of data to exchange directly with LEON3 processor.We start our implementation with basic configuration: SW AHB slave interface, with small packets of data to exchange directly with LEON3 processor.
Host interface block diagramHost interface block diagram
Spring 08-Winter 09 semester Spring 08-Winter 09 semester
Sig
nals
to
AH
B
Sig
nals
to
SW
Por
t
The FSM of the AHB interfaceThe FSM of the AHB interface
Spring 08-Winter 09 semester Spring 08-Winter 09 semester
Spring 08-Winter 09 semester Spring 08-Winter 09 semester
Basic test of the systemBasic test of the system
SW core
AM
BA
AH
B B
US
Dout
Sin
Din
Sout
We will write a data chunk to the SW core, and We will write a data chunk to the SW core, and than we will read from it.than we will read from it.We should read the same data we wrote.We should read the same data we wrote.
Spring 08-Winter 09 semester Spring 08-Winter 09 semester
Advanced test of the systemAdvanced test of the system
SW link interface
SW
cor
e
Board with LEON3 system
Test equipment with SW interface
We will try to transfer complete files from the Leon3 We will try to transfer complete files from the Leon3 system to the test PC over the SpaceWire physical link.system to the test PC over the SpaceWire physical link.
Current minimal system Vs. Final systemCurrent minimal system Vs. Final system
Minimal system:Minimal system: Reading data from SW is done only by processor’s request.Reading data from SW is done only by processor’s request. Data transfer rate is limited by FIFO’s size because of slow AHB Data transfer rate is limited by FIFO’s size because of slow AHB
bus transactions (assumption, not tested yet).bus transactions (assumption, not tested yet). Simple implementation.Simple implementation.
Final system:Final system: Reading from SW will be done by a more complex interface, Reading from SW will be done by a more complex interface,
based on DMA engines or Interrupt mechanism.based on DMA engines or Interrupt mechanism. Implementation will relay on SW interface as described in GRLIB Implementation will relay on SW interface as described in GRLIB
manual.manual.
Spring 08-Winter 09 semester Spring 08-Winter 09 semester
Implementation of SW interface as Implementation of SW interface as described in GRLIB manualdescribed in GRLIB manual
The SW AMBA interface consists of AHB Master interface and DMA The SW AMBA interface consists of AHB Master interface and DMA FIFO’s.FIFO’s.
The DMA engines have 32-bit wide FIFO’s which used for reading The DMA engines have 32-bit wide FIFO’s which used for reading and writing on the AHB.and writing on the AHB.
Receiver and Transmitter DMA’s write/read at half the FIFO’s size Receiver and Transmitter DMA’s write/read at half the FIFO’s size bursts.bursts.
Spring 08-Winter 09 semester Spring 08-Winter 09 semester
Present stage of projectPresent stage of project Successfully connected the SW minimal Successfully connected the SW minimal
configuration to the LEON3 system.configuration to the LEON3 system. When connected in closed-loop SW core When connected in closed-loop SW core
recognized the connection and moved to “run” recognized the connection and moved to “run” state.state.
Data from LEON3 processor transferred Data from LEON3 processor transferred successfully through the SW transmitter, closed successfully through the SW transmitter, closed loop and to the SW receiver.loop and to the SW receiver.
Our next step is to to read the data from the Our next step is to to read the data from the receiver and compare it with the sent data.receiver and compare it with the sent data.
Spring 08-Winter 09 semester Spring 08-Winter 09 semester
Time tableTime table Until the end of December - finish simulating the Until the end of December - finish simulating the
minimal configuration with ModelSim.minimal configuration with ModelSim.
Until beginning of February - debugging of the Until beginning of February - debugging of the complete minimal system with GRMON, while complete minimal system with GRMON, while communicating with SW test equipment.communicating with SW test equipment.
Beginning of March - final report and Beginning of March - final report and preparation for the next semester - designing the preparation for the next semester - designing the final system architecture.final system architecture.
Spring 08-Winter 09 semester Spring 08-Winter 09 semester