Sentinel Scheduling

Sentinel SchedulingSentinel Scheduling

Multimedia Systems Lab.2006 년 5 월 17 일

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2006/05/17 Sentinel Scheduling 2 / 32

OUTLINEOUTLINE

Necessity of Sentinel Scheduling

Sentinel Scheduling Design

Sentinel Scheduling Algorithm

How to generate recovery code

Summary


Necessity of Sentinel SchedulingNecessity of Sentinel Scheduling

Needs of Speculation ILP is necessary in VLIW and Superscalar architectures Insufficient ILP within basic blocks (especially for non-numeric

applications) Instruction scheduling across basic block boundaries is need

Benefits of Speculation Increase ILP (break control dependencies) Tolerate latencies (issue long-latency instruction earlier) Increase loop-level parallelism



Problem of Speculation Speculated instructions may raise exceptions Code often contains tests to prevent exceptions (divide by

zero)

What instructions make exception?

How can handle exceptions?



only some instructions can cause exceptions (PEI’s) PEI : potentially excepting instructions

Cause of Exceptions Memory operations (segmentation fault, null exception) Divide operations (divide by zero) Any floating-point operation (NaN)

Other operations can be speculatively scheduled without worrying about exceptions



Method for exception processing Approach A – only allow speculative code motion on

instructions that do not cause exception → too restrictive ILP

Approach B – hardware support→ hardware cost

Four Implementations Restricted Percolation General Percolation Instruction Boosting Sentinel Scheduling



Restricted Percolation Software-only speculation. Complier is allowed to move instructions above branches

only if they never cause exceptions and the compiler can find a destination for the operation that isn’t used in the other path.



General Percolation Hardware must implement silent (non-faulting) verions of all PEIs Speculate PEIs by replacing with silent versions Downside : exceptions in speculative ops may never be detected.





Pros Low hardware cost Allows more speculation than restricted percolations

Cons Writing garbage into dest register makes bugs harder to find Some exceptions may never get caught



Instruction Boosting Scheduler not responsible for dealing with exceptions or

preventing state modifications. Add hardware to deal with speculation issues

• Shadow register file buffers instruction results• Shadow store buffers hold data from store instructions

When speculative instructions execute, their results go into shadow register file and shadow store buffer.

Speculating results commit into memory, register file when their associated branch completes.





pros Allows more instructions to be speculated Good exception recovery

cons Big hardware cost Bypassing may increase cycle time



From Instruction boosting provide an effective framework for speculative code motion of instrs. and

identification of exceptions

From general percolation lower hardware implementation cost

→ Sentinel Scheduling


Sentinel Scheduling DesignSentinel Scheduling Design

Design Objectives Correctly ignore exceptions generated by speculative whose execution tur

ns out to be unnecessary Correctly report exceptions generated by speculative instrs. Support recovery from exceptions thus reported Minimize the hardware cost

What’s the sentinel



What’s the watching object?

What can be a sentinel?



Watching object ? Exception of speculative instructions

Sentinel ? any non-speculative inst that read the destination of a

speculative instruction is a sentinel for that inst If no such inst exists, need to add an explicit sentinel inst



Key observation : Instructions have two functions Perform Operation Detect Exception

Architectural Support One bit in each opcode records whether the instruction is speculative Each register contains two additional fields

• Exception flag• Exception PC



Each instruction has sentinel part to detect exception

Sentinel part elimination If there is another inst in inst’s home block which uses the result of inst

• Home block : The home block is the basic block thatcontained the instruction before it was made speculative

I is non-excepting and is not the last direct or indirect use of an excepting instruction’s destination


Sentinel Scheduling AlgorithmSentinel Scheduling Algorithm

Algorithm Identify unprotected instructions - unprotected instruction : an inst whose sentinel cannot be

eliminated Perform conventional scheduling

• If an unprotected instruction is moved above a branch, a sentinel is placed in the place where the instructions were moved speculatively

When a speculative instruction causes an exception, the exception flag is set and its current PC is saved

When the sentinel is executed, the exception flag is checked and an exception is taken



Exception Model : Speculative instructions src(I).except = 0

• I does not cause an exception - Normal execution• I causes an exception- dest(I).except = 1- dest(I).data = pc of I

src(I).except = 1• Exception propagation• dest(I).except = 1• dest(I).data = src(I).data



Exception Model : Non-Speculative instructions src(I).except = 0

• I does not cause an exception - Normal execution• I causes an exception - I reported as source of exception

src(I).except = 1• Report exception for speculative instruction• Signal exception• dest(I).data if PC of exception



Scheduling Constraints Compiler is responsible for ensuring speculative insts don’t overwrite regi

sters needed on the other path of the branch Compiler must ensure that every speculative instrs has a sentinel inst in

its home block Source operations of speculative instructions may not be overwritten until

the sentinel for that instruction executes.










How to generate recovery codeHow to generate recovery code

PEI’s flow dependence chain It is the chain of instructions which are flow dependent on the

PEI The first instruction is flow dependent on the PEI, the second

instruction is flow dependent on the first instruction,… The flow dependence chain stops at a sentinel

Usage of PEI’s flow dependence chain If an explicit check is needed or not Make recovery code



Code Example

I1 beq r5, 1, 50I2 r10 = mem(r11)I3 r3 = r2/41I4 r6 = r3+r4I5 r9 = r10+r6I6 mem(r7) = r6I7 bne r10,0,100

A. Original Code

I2 <s>r10 = mem(r11)I3 <s>r3 = r2/41I4 <s>r6 = r3+r4I5 <s>r9 = r10+r6I1 beq r5, 1, 50I6 mem(r7) = r6I8 check r10I7 bne r10,0,100

B. Scheduled Code

I2’ r10 = mem(r11)I3’ r3 = r3/r1I4’ r6 = r6+r3I5’ r9 = r10+r6I6’ return I6

C. Recovery Block



PEI’s flow dependence chain

I3

I4

I5

I6

I2

I5

An instruction can act as an implicit check for a PEI if it is flow dependent on an instruction located in the PEI’s flow dependence chain and is not speculated

If there is no istruction in a PEI’s home block that meets this criteria, an explicit check must get added



How to generate recovery code The instructions put into the recovery block consist of all the

PEI’s from a home block All the speculated instructions found in the PEI’s flow

dependent chains At the end of the recovery block, a return operations is inserted


SummarySummary

Sentinel Scheduling Correctly ignore exceptions generated by speculative whose execution tur

ns out to be unnecessary Correctly report exceptions generated by speculative instrs. Generate recovery code Minimize the hardware cost

Thank you

Documents

Sentinel Scheduling