Silicon, Interconnect, Packaging and Test Challenges · PDF fileSilicon, Interconnect, Packaging and Test ... interconnect, wafer test ... – Who owns the cost of failed IC’s on

Silicon, Interconnect, Packaging and Test Challenges from a Foundry Viewpoint

SWTC June 2015

Keynote Perspective

Design Test Dev

(DFT) Reticle

Sets Wafer Fab

& FSI Bump Probe

Thin & BSI

Ass’y & Test

OSAT Partners

Process development and characterization

For 3D and 2.5D, μbump is owned by the OSAT

Design Partners

Design flow, rules

and tool alignment

Memory Partners

Integration and

characterization

EDA & IP Partners

Development

and validation

2

Customer Design

Bump and Probe

Assembly, Package Test, Board Mount

Agenda

Trends in Silicon

Packaging Drivers and Solutions

Materials and Design: Challenges and Learning

1

2

3

Test Challenges from Foundry Viewpoint 4

Supply Chain Solutions 5

GLOBALFOUNDRIES 4

Technology Node

Tra

nsis

tor

Cost

Cost of Scaling per Transistor is no Longer Decreasing

FinFET

Cost of Scaling is Rapidly Increasing

• Development cost for 10nm design will approach $400M

5

Cost of Scaling is Too High

• Requires multi-$B lifetime revenue to be economically feasible per design

• Forces foundries to push customers into “good enough” solutions to drive volume

• Must find other solutions

6

Trends in Silicon

Packaging Solutions

Material and Design: Challenges and Learning

1

2

3

Test Challenges 4


Solutions have to balance performance, power, and cost

GLOBALFOUNDRIES Confidential 8

Silicon

• BEOL stacks

• Low K modulus

• Thinness (warpage)

Thermal

• Heatsink

• TIM

Packaging Challenges

10/01/2014 GLOBALFOUNDRIES Confidential

TSV Process Challenges

• TSV integration

• Device KOZ

• Pumping

Substrate

• Core CTE

• Warpage

• Routability

Assembly Challenges

• Die attach and die stacking

• Underfill flow vs gap and pitch

• Warpage management

Bump

• Pitch

• Cu Pillar induced stresses

• EM challenges

Wafer Test

• Contact technology

• Pitch / Parallelism

• Probe card cost

• Supply chain

Bump Pitch (µm) Bandwidth Drive I/O Density

0

20

40

60

80

100

120

140

160

2012 2013 2014 2015

Bump

µBump


Bum

p P

itch (

µm

)

TSV

But Single Die Bump Pitch Isn’t Enough Applying Packaging to Solve Scaling Limits

• SoC Partitioning

– Cost optimization: Logic-Logic side by size or stacked

• Reduced die size

• Increased yield

– Functional optimization: Best fit node per function

• Design reuse without redesign

• Lower risk – lower cost

• Logic-Memory Power & Performance

– Logic & memory integration:

• Increased bandwidth

• Higher performance per watt

• Logic-Logic for Performance

11

SoC Die

1

Die

2

Jan 19th, 2015 GLOBALFOUNDRIES Confidential

Interconnect Density: The Enabler

• Edge Routing provides challenges (side x side solutions (2.5D, WLFO) routing density:

– 0.5µm (silicon interposer) - 5µm (WLFO)

– Small vias needed to enable multi-layer routing

– Shielding

– 1 edge of 10mm die at 2µm L/S, 1/3 of lines used for shielding: 1675 interconnect

– 1 sided routing challenges on design

• Stacked (3D) solutions:

– Area based: 5um vias, 2um keep-outs, 1/3 of TSV used for shielding, limit TSV to <1% of die area


HBM Memory: Routing for 55um Bump Pitch

13 Glass will be technology/supply chain dependent

HBM Routing Capable

Routing Density Solutions


Package Size

IO D

ensity (

traces/m

m o

f ed

ge

)

POP

High Density Laminate

Silicon Packaging (2.5D)

wlCSP (FI)

Incre

asin

g P

erf

orm

ance

HD WLFO

Silicon Packaging (3D)

Low Density Laminate WLFO

Power Envelope is Limited and Costly to Manage

15

June 9, 2015

• Mobile: Maximum skin temperature in smart phones requires shutdown of cores

• Computing: Power required to drive off substrate memory reduces graphics or processor performance

• Networking: > 50% of data center cost is cooling

• Memory: Tj > 80C increases the required DRAM refresh rate, increasing power and heat

• SerDes greatly reduces I/O density required between processor and memory but generates significant heat

• Solution 1: Massively parallel I/O solves the heat problem but requires new technologies with very dense routing capability on substrate

Solution 2: Technological Innovation Power Management 2.5D Roadmap

16

pJ/bit

Memory

Memory

Memory

SoC

Memory

Memory

Memory

Solution 3: Are We Over-Designing?

• Architecture decisions drive interconnect density

• Decisions are often made without understanding impact on cost (and number of suppliers with capability to meet)

• Affects cost at multiple levels: interconnect, wafer test, substrate, assembly

• We need to drive cost impacts prior to design decisions Interconnect, wafer test, substrate, assembly

17

12/12µm L/S 2/2µm L/S

Trends in Silicon


Material and Design: Challenges and Learning

1

2

3

Test Challenges 4


Chip – Package - Interaction

• Polyimide and BEOL layers on one side warp wafers

• There is a decreasing amount of solder to join each bump (or pillar) as pitch shrinks – ie more sensitive to warpage (O/S)

• Substrates, with higher bulk CTE than silicon, dominate warpage from reflow cool down

• Resulting stress is exerted on bump and on BEOL stack, which can break

• Detect separation by ultrasonic imaging

•


Silicon

Bump

or

Pillar

BEOL

Stress

Transmitter

Substrate

Driving CPI at Leading Edge Nodes

S.Kengeri, Semicon SGP 2014

Driven by multi-core processors and increase in I/O

Reduce electrical setbacks inherent with shrinking Cu dimensions

Pb Free CuPillar

Si to laminate CTE mismatch

Organic Substrate

Size

Higher Modulus

Bump

Dielectric Constant

(ILD)

Die Size

Greater stress

More fragile: cohesive strength modulus adhesion

Greater stress Greater stress

Lower-K ILDs vs. Modulus vs. Hardness

B.Chandran, intel Future Fab 2004

Bump Interconnect “Nodes” GLOBALFOUNDRIES Bump/Probe Shipments

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SnAg.Bump

Pb.Bump

CuP


2011 2012 2013 2014 2015 2016 2017 2018 2019

28nm 10nm 14nm Platform

Technology

SnAg ≥ 180µm Pitch

Cu Pillar

µBump

finFET

≥ 130µm Pitch

≥ 100µm Pitch

≥ 80µm Pitch

2.5D/3D ≥ 40µm Pitch

TSV Interposer TSV Diameter/Thickness: 10µm/100µm

3D TSV 6µm Diam/55µm Deep TSV + M3

GLOBALFOUNDRIES Interconnect Roadmap

23

Interaction Between Design and BEOL Stack

• Weaker dielectric

• Cost driver to eliminate layers

• Tougher mechanical reliability requirements

High lead Solder Lead Free Solder

28nm

D.Breuer et al. MAM2014

100um bump pitch

64nm silicon routing pitch

Almost 3 orders of magnitude

GLOBALFOUNDRIES Confidential 25 23.12.2014

White Bump – Localized Crack Under Bump

CSAM example of white bump

FIB SEM

BABSI Bump Assisted BEOL Stability Indentation


[1] H. Geisler, M. Lehr, F. Kuechenmeister, M. Grillberger, German Patent DE 10 2010 002 453 A1 (September 01, 2011).

[2] H. Geisler, E. Schuchardt, M. Brueckner, P. Hofmann, K. Machani, F. Kuechenmeister, D. Breuer, H. Engelmann “

Experimental Analyses of the Mechanical Reliability of Advanced BEOL/fBEOL Stacks Regarding CPI Loading” IRPS 2013

Improve Robustness Die Edge Design

• Crack stop with interconnected metal walls; wider = stronger

• Metal fill with vias in corners to increase robustness

• Complex metal “walls” GLOBALFOUNDRIES Confidential 27

TSV Process Flow and Challenges

Post TSV Etch

Post resist strip

TSV clean

Post TSV Liner

TEOS 03

STI

Post TSV

Barrier Seed

Post TSV ECP

& Anneal

Silicon

STI

CAP

MOL FEOL /

Stack

Post TSV CMP

Land on Cap

Dense array

• TCD / Depth /

BCD uniformity

•Liner step coverage •Barrier Seed

continuity

•Cu step height

•Cap uniformity

•Void free gap fill

•Overburden

28

Via Chains and Pop-up Structures Electrical Test Summary

• Very low impact due on via chains with KOZ at 1μm and 2μm

• TSV pop-up structures show negligible impact of TSV and meet the target specs

29 No degradation as move from 5um to 1um KOZ

Trends in Silicon



1

2

3

Test Challenges 4


Foundry Test Business

• The Foundry does wafer test to provide fast feedback on yield to the fab

– Critical for devices in leading edge fab processes

– Particularly FA drives probe at the Foundry

– Bump is required to get to wafer test

• Cost drives location of bump and probe for mature devices and nodes

• Thus bump and probe are generally at the foundry for leading edge and generally at the OSAT for HVM and trailing edge

• Customers generally provide probe cards because for the Foundry, the customer controls all input probe card costs (I/O, parallelism, product ramp, product lifetime)

• The Foundry (mostly) does not do final package test


Bump Pitch (µm)

0

20

40

60

80

100

120

140

160

2012 2013 2014 2015

Bump

µBump


Bum

p P

itch (

µm

)

TSV

Bump Cost Trend

2012 2013 2014 2015


But Wafer Test Cost Composition is Changing

Dep

PCs

Util + Fac

Maint

I/L

D/L

Other

Today


Dep

PCs

Util + Fac

Maint

I/L

D/L

Other

1 yr Ago

Probe Card Cost

• Cost is increasing with

– Decreasing pitch

– Increasing probe count

– Increasing parallelism

• Which also drives tester cost

• Design impacts

– Cost of test is determined largely in device design


Current cost model ($10/probe) is not scalable with IO quantity and pitch

x8 Total Cost

Head Only

$K

per

Card

Increasing # pins

Probe Card Lifetime

• Pitch reduction drives PC lifetime reduction

– Pin diameter reduction

– Shortening usable tip length


0

0.2

0.4

0.6

0.8

1

1.2

1.4

0

100

200

300

400

500

600

700

800

900

4.0 2.5 2.0

Usable TipLength (µm)

Life time (Mtouchdowns)

Probe pin diameter (mils)

Useable

tip

length

(µ

m)

Life

Tim

e (m

illion to

uchdow

ns)

Typical Product Ramps

1st Quarter 1st Year 2nd Year 3rd Year

Mobile

Graphics or PCProcessor

Automotive


Rela

tive V

olu

me

Net Probe Card Cost per Wafer Shipped

160um 110um 80um


$ p

er

wafe

r ship

ped

Bump Pitch

Not acceptable Forcing a re-think on technology

Wafer Level (wlCSP) Test

• Large Turn-key Business for Foundries

• Business model is selling net-good-die

– Close OSAT partner relationships

• Challenge is processing after test: no electrical failure detection

– Capability and process control at blade and laser saw, pick, inspection, and in tape design critical and tends to drift out of control

– Saw more difficult on wlCSP because of high stress in thick one-sided RDL layers

• WLFO enables molding a small ring around die. Issues:

– Cost: no satisfactory solution

– Need either cheap safe die bare die handling or

– Installed capacity


WL Fan-In

wlCSP Crack Risk from Saw Process

Step 1 Step 2A Step 2B

Note: Drawing is not to scale.

July 23, 2013

Confi

denti

al 40

Street width makes a net good die difference at these small die sizes Laser energy decreases over time Detection difficulty post test Continuous attention on process control essential

Wafer Probe Roadmap Challenges

• Probe card cost , particularly <100µm

• Probe technology < 80µm

– Probe on Microbump?

√ Sacrificial pad?

• Utilize DfT with wrappers to reduce the number of I/O that need to be contacted?

– Ability to re-use tester assets

– Ability to use less dense and cheaper cards

– But difficult for the Foundry to implement

• wlCSP testing methodology


Trends in Silicon



1

2

3

Test Challenges 4


Deep Partnerships A Collaborative Supply Chain

Customer benefits

– Open, flexible, cost-effective supply chain

– Aligns with customer’s preferred partners

– Active co-development to ensure smooth volume ramp

– Suppliers don’t duplicate investment and thus cost is lower

Design Test Dev

(DFT) Reticle

Sets Wafer Fab

& FSI Bump Probe

Thin & BSI

Ass’y & Test

OSAT Partners

Process development and characterization

For 3D and 2.5D, μbump is owned by the OSAT

Design Partners

Design flow, rules

and tool alignment

Memory Partners

Integration and

characterization

EDA & IP Partners

Development

and validation

43

Business Model Challenges for the Foundry

• Don’t invest in what an OSAT can do better/cheaper

• Do invest in leading edge differentiating technology

• For multi-chip techologies:

– Will competitors ship die to a competitor for multi-chip product assembly?

– Who owns the cost of failed IC’s on multi-chip products?

• Close collaboration on development

• Priority as a ‘non-customer’


Collaboration Drives GLOBALFOUNDRIES Packaging

Validated Interposer reference flow

DFT enabled interposer flows

60K/month Bump & Probe Capacity

>15 years experience providing turnkey solutions

2.5D and 3D TSV enabled at Leading Edge

2.5D HBM integration demonstrator

Seamless supply chain model in setup

CPI Qualified at 28nm with low cost FC solutions at two major OSATs

14LPP 2D, 2.5D & 3D Package qualifications at multiple OSATs

2.5D package qualified with GF interposer

3D TSV package qualified

Seamless supply chain models in setup for 2.5D products

Design

Capabilities • Co-Design

Reference Flows

• DFx support and

tools

Internal

Capabilities • Bump & probe

• Turnkey solutions

• Investment in

emerging

technologies

Memory

Partnerships • Logic-Memory

Demonstrators

• Innovative

business models

OSAT

Partnerships • JDAs at leading

edge nodes

• Innovative

business models

Summary


Summary

• End of scaling at always lower cost

• Alternatives driver higher I/O density and new packaging solutions

• The new solutions drive higher cost test and downstream costs (substrate)

• Advancing silicon technology presents material and stress challenges that must be characterized.

• Must have significantly cheaper probe card technology and questioning of cost of test at design

• Need high density substrate solutions at lower cost

• The collaborative supply chain enables accessing best expertise at lowest cost

Thank you to: Jens Kober – Probe Dev and Production John Carulli – Test Development TM Mak – DfT and IP 2.5D/3D Jens Paul – CPI Reliability Rama Alapati – Product Mgt for Packaging

Trademark Attribution

GLOBALFOUNDRIES®, the GLOBALFOUNDRIES logo and combinations thereof, and GLOBALFOUNDRIES’ other trademarks and service marks are owned by GLOBALFOUNDRIES Inc. in the United States and/or other jurisdictions. All other brand names, product names, or trademarks belong to their respective owners and are used herein solely to identify the products and/or services offered by those trademark owners.

© 2014 GLOBALFOUNDRIES Inc. All rights reserved.

Thank you

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Silicon, Interconnect, Packaging and Test Challenges · PDF fileSilicon, Interconnect, Packaging and Test ... interconnect, wafer test ... – Who owns the cost of failed IC’s on