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H. Krüger, EUDET Brainstorming, 3/4.11.2005 1 SI LAB Silizium Labor Bonn Silicon Lab Bonn Physikalisches Institut Universität Bonn • DEPFET Test System • Test Beam @ DESY

Silicon Lab Bonn Physikalisches Institut Universität Bonn

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Silicon Lab Bonn Physikalisches Institut Universität Bonn. DEPFET Test System Test Beam @ DESY. DEPFET sensors 64 x 128 pixels, 36,5 x 28 µm 2 (Q1 2007: 512 x 512 pixels, 33 x 24 µm 2 ) Event rate old system: 10 Hz (various limitations) - PowerPoint PPT Presentation

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Page 1: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 1 SI LABSilizium Labor Bonn

Silicon Lab Bonn

Physikalisches InstitutUniversität Bonn

• DEPFET Test System

• Test Beam @ DESY

Page 2: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 2 SI LABSilizium Labor Bonn

DEPFET Prototype System

• DEPFET sensors– 64 x 128 pixels, 36,5 x 28 µm2

– (Q1 2007: 512 x 512 pixels, 33 x 24 µm2)

• Event rate– old system: 10 Hz (various limitations)– new system: ~1 kHz (w/o zero supp.),

data transfer limited (20 Mbyte/s, USB 2.0)– with zero suppression: ~100 kHz (theor.),

row clock rate limited (10 MHz)

• DAQ– USB 2.0 interface to Win2k/XP PC– independent processes for slow control,

file writing and online-monitoring– inter-process communication via

‘shared memory’ buffers

Page 3: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 3 SI LABSilizium Labor Bonn

Read-out System Hardware

Hybrid

DEPFETMatrix

128 x 64

FPGA

CURO II

SW SW

ADCADC

SRAM

TIATIA

Ctrl

Analog Signal

Hit Add

Ctrl

S3A Board

USB Board

USB µC

EPROM

PowerSupplies

USB 2.0

PC Win 2000/XP

DAQ SW (C++)

USB DLL

USB driver

Trigger Logic

Tri

gg

er /

Bu

sy

DEPFET DUT

S3A Board• Mixed signal board• Dual 65 MHz ADCs • FPGA + 256k SRAM• USB 2.0 interface card

Hybrid • DEPFET matrix• 2 Switcher + Curo• 2 transimpedance

amplifiers

Page 4: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 4 SI LABSilizium Labor Bonn

BAT Bonn ATLAS Telescope

• four planes of double sided strip detectors

– 640 x 640 ch.– 50µ pitch

• analog r/o– VA1 / VA2 chips– S/N ~40-70

• spatial resolution: 4-5 µm• on-module zero suppression• event rate: max. 8 kHz• PCI interface card• DAQ SW for Win2k/XP

Page 5: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 5 SI LABSilizium Labor Bonn

Test Beam Setup with BAT and DEPFET

trigger

TLUTLU

Trigger to modules

BAT modules

Blue Board Bus (BBB)

Win XP

PCI interface

USB interface

Busy from modules

BAT modulesDEPFETTrigger Logic Unit

Page 6: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 6 SI LABSilizium Labor Bonn

Test Beam DAQ Structure

• See talk by Peter Fischer

Page 7: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 7 SI LABSilizium Labor Bonn

Results from DEPFET TB @ DESY August 2005

• noise ~230 e• S/N ~140

(450 µm thick detector)

• purity 96.3%• efficiency 99.3%

5σ seed cut

Page 8: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 8 SI LABSilizium Labor Bonn

Results from DEPFET TB @ DESY August 2005

Limitations:• low frame rate ~10Hz

limited by (old) test setup and

low electron flux @ 6 GeV

• spatial residuals ~10 µm(expected 2-4 µm @ S/N 144)

dominated by multiple scattering @ 6 Gev e-

beam

Page 9: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 9 SI LABSilizium Labor Bonn

Wish List

• Beam– highest possible energy (> 6 GeV)– moderate to high flux (adjustable)– variable bunch structures ?

• Telescope– resolution < 2 µm, area min. 1 x 2 cm2

– low (almost no) material– minimum (adjustable) distance between telescope modules – high event rate (~ O(kHz))

• Mechanics & Cooling– positioning system for DUT (x, y, theta), < 1 µm x-y resolution– cooling: yes, but common schema feasible?

• Trigger– different scintillator sizes to adapt to DUT active area– configurable trigger interface to connect to DUT (Trigger,

Busy, BOR)– event by event r/o or buffered r/o

Page 10: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 10 SI LABSilizium Labor Bonn

Wish List cont.

• Telescope DAQ and integration issues…

Page 11: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 11 SI LABSilizium Labor Bonn

Integration of Telescope and DUT on HW Level

file

• sensors and FE electronic

• first level interconnect

• digitalization & sparsification with common DAQ HW (adopted for DUT)

• COTS interface (Gbit-Ethernet, USB, S-LINK, cPCI, VME…)

• common DAQ control, slow control, file writer (PC, SBC…)

telescope

DUT

DAQ HW

proprietary bus

DAQ ctrl

standard bus interface

computer

interface

Trigger

Page 12: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 12 SI LABSilizium Labor Bonn

Integration of Telescope and DUT on SW Level

file

• sensors and FE electronic

• first level interconnect

• digitalization & sparsification with dedicated DAQ HW

• COTS interface (Gbit-Ethernet, USB, S-LINK, cPCI, VME…) can be different

• still common DAQ control, slow control and file writer but different interfaces

telescope

DUT

DAQ HW

DAQ ctrl

standard bus interfaces

computer

intfc intfc

Trigger

Page 13: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 13 SI LABSilizium Labor Bonn

Integration of Telescope and DUT on Data Level

file

• sensors and FE electronic

• first level interconnect

• digitalization & sparsification with dedicated DAQ HW

• COTS interface (Gbit-Ethernet, USB, S-LINK, cPCI, VME…) can be different

• independent DAQ control, common file writer, running on one or two machines with inter-process communication (shared memory buffers, TCP/IP)

telescope

DUT

DAQ HW

tel. ctrl

standard bus interfaces

computer

intfc

Trigger

DUT ctrl

intfc

IPC

Page 14: Silicon Lab Bonn Physikalisches Institut Universität Bonn

H. Krüger, EUDET Brainstorming, 3/4.11.2005 14 SI LABSilizium Labor Bonn

Discussion

• common omni purpose DAQ (standardized, well documented and maintained, cheap…) would be the ultimate goal

• but: most of the users already have their DAQ (or at least lab test-setups)

• they should not be forced to re-design their setup if they want to use TB@DESY

• integration on SW level is difficult or impossible due to different operating systems

• integration on ‘data-level’ seems to me most flexible, users can stick to their known DAQ

• needs definition and implementation of IPC (via TCP/IP or shared memory buffers), control protocol and common data format

+ four LEMO cables for trigger, busy, reset and “something else”