s

Siliconphotonicseyes onlySilicon photonics

(Fabless & laser

source & modulator)

12 June, 2018

Dong Sung Lim

What is different between photonics & CMOS

thousands

• 낮은 집적도• 소량 생산• 여전히 높은 가격• 시장 규모 (~ $10B)• 제한적 응용

그럼 어떻게 가능했고 언제 시작됐지

• 무어의 법칙 (Moore's law)• 매우 낮은 가격• 대량 생산• 거대한 시장 (~$400B)• 다양한 응용• 새로운 시장 창출

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Short history of CMOS electronics

1948년William ShockleyJohn BardeenWalter Brattain

1958년Jack KilbyRobert Noyce

1979년 MPWMead & Conway(Xerox PAC)

1986년Pure-play FoundryMorris Chang (TSMC)

1965년Moore의 법칙

1980년대EDS PDK

2015년Intel 5세대19억개 집적

1987년Fabless

1971년Intel 4004

2,300개

2000년Intel Pentium 4 4천만개 집적

Moore's law 은 반도체 집적회로의성능이 18개월마다 2배로 증가한다

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• We have to learn 4 lessons from microelectronics

– MPW(Multi Projects Wafer) & PDK(Process Design Kits)

– Foundry & Fabless

• In My views microelectronics already use “”Shared Economy methods”” by MPW & Foundry

Key success factors for Silicon CMOS microelectronics

MPW PDK Fabless Foundry

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Photonics integration direction to go

➢ SiP MPW를 이용하면 저가 고성능 집적화 칩 R&D 및 시제품 제작 가능➢ Si-photonics (SiP) foundry 기반 fabless 비즈니스 모델이 부각

• 2000년대까지는 설계/제조/집적/패키징까지 설비를 갖춘 “vertical”형 업체가 주도

• 2010년부터는 설계를 전문적으로 하고 외부 foundry를 이용하는 “Fabless”형 업체가 주도

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Foundry

MPW

PDK

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Silicon photonics becomes “”Desgin to manufacture””

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Ecosystems for fabless

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Fabless landscape

• Many fabless Silicon Photonics companies have emerged

– From direct collaboration with fabs (Luxtera, ...)

– Starting from MPW (Caliopa, Genalyte, Acacia, Sicoya, Rockley, etc)

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• Established players are also partnering

– e.g. Finisar with ST

• Many keep their fab a secret

• How to enter as a new (fabless) startup?

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Complementary foundry platforms

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www.europractice.com www.vtt.fi sotonfab.co.uk www.amo.de

www.a-star.edu.sg/ime www.aimphotonics.com www.appliednt.com

cmp.imag.fr

Manufacturingplatforms

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Acceable MPWs: technology summary

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ISIPP50G 310nm SOI SG25_PIC VTT platform

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IMEC’s platform

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Photonics PDK at IMEC

Structure of PDK at IMEC

• LFD: Lithography friendly design• LVS: Layout vs. schematics• DRC: Design rule check• GDS: Geometric Data Stream

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IMEC$40,00026.5mm2

HHI, €11,50048 mm2

SMART, €4,4009.2 mm2

IMECMini

$10,0006.25mm2

MPW cost summary

TSMC 90nm CMOS

$50,00016 mm2

• 2017_PIC-Workshop-OFC-2017-LA• http://www.europractice-ic.com/SiPhotonics_pricing.php• 2017_PIC-Workshop-OFC-2017-LA• https://www.a-star.edu.sg/ime/SERVICES/photonics_service_and_platform

CMOS

SiPInP

IME $8,000

6.25mm2

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Broker Process Componentssize (mmxmm)

Price (€)MPW cost (€/mm2)

# of chips

JePPIX HHI Tx20Rx40 DBR/DFB/SOA/EAMs/PDs/Passive/PM 4x12 11,550 240 2

JePPIX SMART TxRx10 DBR, SOA, EAMs, PDs/Passive/RF parts 2x4.6 4,440 480 8

ePIIXfab IMEC ISIPP50G MZM/Ring/PDs/Mux/WDM/Passive 5.15x5.15 40,000 1,508 40

ePIIXfab CEA-LETI Passives with Heaters 6.0x2.0 14,325 1,193 50

ePIIXfab VTT 3 um SOI Passive 5x10 8,000 160 100

OPSiS IME Passive, and Active with Ge and SiGe 2.5x2.5 8,000 1,300 20

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From sampling to low-volume production

• Most Research Fabs (IMEC, LETI, IME) offer a LVM model

• Low volume(<1000 wafers/year) is enough for first market

• IMEC offers

– 2 passive and 2 active MPW runs per year

– Dedicated runs and production on reques

– More than 175 photonics ICs taped-out since 2011

– Production path at commercial foundry (95% of the flow compatible with CMOS90 technology)

– Consistent quality (monitored process) supported by PDK with models and statistics

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With

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IMEC MPW & LVP

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Everybody can think simple way to enter the TRx market

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Winning market : differentiatoin !!!!!

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Speed,

fighting spirit

&

Best baseline players

VS.

Boris BeckerStefan Edberg Ivan Lendl

Can be differentiated because technical challenges in SiP

• Spectral transparency: >1.1 µm (Si bandgap)

• Optical power limitation: < 100 mW (two photon

absorption)

• Distributed backscatter: %’s per cm (sidewall roughness

+ High Index Contrast)

• Optical pathlength error 0.1% - level (Linewidth control

+ High Index Contrast)

• T-sensitivity of pathlength 0.01%/K (thermo-optic

coefficient of Si)

• Bandwidth increase : <100 GHz (Capacitance, Mobility)

• Light source integration : Fundamental challenging

(Indirect bandgap)

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Why not direct lasers on silicon ??

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Si could be a good laser material: reduced two photon absorption (100X less), lower waveguide loss: <0.3 dB/cm, higher thermal conductivity

… if it was not an indirect bandgap material!

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Two differentiation points at SiP

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Assembly + packaging + TestIII-V on Silicon

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III-V LD to Silicon : Dimensions & index

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BH InGaAsP DFB LD(280 x 600 nm)

SiP waveguide(200 x 500 nm)Single mode

optical fiber core(8 μm)

1.5082 3.97663.3688

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Things to differentiation: III-V LD to Silicon

• Process: Monolithic direct laser vs.

Heterogeneous vs. Hybrid

• Bonding : Molecular, metal vs. Polymers

• Wafer : WtoW, WtoD vs. DtoD

• Coupling : in-plane vs. off-plane

• Mode conversion : Lens vs. Spot Size Convertor

• lasing mode : III-V vs. III-V Gain+external

feedback

• Pick and place : flip chip vs. ball solder surface

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Method Hybrid Heterogeneous Monolithic

Integration Externally III-V chip aligned to Silicon waveguide

III-V wafer or chip bond on Silicon

Direct growth on SiliconSubstrate

Location of gain Side or on top of Silicon Top of Silicon Top of Silicon

Attachment Externally located- Molecular bonding- Adhesive Epoxy (BCB) - Metallic bonding

Selective area epitaxiallygrowth

Coupling Direct coupling - Evanescent coupling - Self lasing

Structure- Lens & reflectors- Tapered butt- 1/2D Grating

- Rib/Strip/channel WG- Inverted taper- Waveguide grating

- Dots- Wires

Gain materials- InP- QD

- InP- QD

- InAs/GaAs QD- Ge QD

Wavelengthselection and cavity

- Independent laser- DBR/DFB/Ring

- DFB/DBR/Ring - FP with Facets

Passive or active alignment ??

Maybe Yes Not applicable

WFE 7~14% 3~5%, 15% at 25oC ~ 18%

Comparison of lasers for SiP

• WPE : Wall Plug efficiency

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Bonding: Molecular vs. Polymer

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Molecular Bonding (UCSB, HP. LETI etc)

Polymer bonding DVS BCB(Ghent, IMEC etc.)

• Thin (down to ~nm) and uniform bonding interface dielectric

• Strong optical interaction between III-V and Si

• But very smooth, clean, flat surface required

• Easier process, better tolerance to surface conditions

• But Relative thicker (>70 nm) and non-uniform interface polymer

• Poorer optical interaction between III-V and Si, a thermal barrier

DiVinylSiloxane- BenzoCycloButene (DVS-BCB)

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Wafer-to-Wafer vs. Die-to-Die

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In plane vs. out of plane

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• Grating based out of plane optical coupling

– Diffractive structures in SiP chip

– Good coupling efficiency

– Scale to 2D arrays

– Wafer level test

– Wavelength dependent

– Polization dependent

• Mode expansing based in-plane optical coupling

–Wavelength tolerant

–Polarization insensitive

–Compatible with electrical assembly

–Requires modal field size adaption

–1D array optical chip interface

–Chip level test only

Mode conversion by spot size conversion

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Tapered Polymer SiNx SiO2Lensed

RWTH Aachen University

PETRA & University of Tokyo

Edge CouplersTrident Spot size converter

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Mode in silicon vs. III-V

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Mode atIII-V

Mode atSilicon

IMEC-Ghent U.

HP/Aurion

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Luxtera

• Use mature InP laser diode technology (multiple suppliers)

• Include an isolator in the system • Use efficient coupling scheme • Wafer level assembly, packaging

and test • Establish suitable burn-in

methods • Silicon Laser Micro Package:

– Base wafer: silicon micro bench – Lid wafer: cavity with mirror – Hermeticity by solder seal

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2010

Cisco 100G CPAK®

• 1Tbps at front panels

2010

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KAIAM

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2014

MA/COM

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2016

Kotura/Mellarnox

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2007

Tyndal

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Jeong Hwan Song

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2010

Fujitsu/PETRA

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Seok-Hwan Jeong

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2012

NEC & Tohoku

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2015

ORACLE

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Jin Hyung Lee (Currently join the finisar)

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2013

@ OFC2016

SKORPIOS

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Angled SEM

Mode Profile

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2012

Coriant

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SiNx SSC coupler mode size is designed to be 3.52 μm × 0.72 μm to match typical SOA mode sizes

2015

IMEC & LETI

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2012

IBM

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2016

Nokia Bell Labs

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• Ultra wide band RSOA• Rear facet tilted facet

▪ cleaved facet with 30% reflectivity for output▪ 7도 tilted antireflection coated facet for coupling with Silicon PIC

• Coupling III-V gain to silicon : Edge coupling using SSC

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2016

RWTH at AAchen

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2017

UCSB/AURION/Intel

Hyundai Park, BC Kim

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2006

Intel

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2001

Mario Paniccia

Direct growth landscape

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• Peoples still working very hard to get direct lasers on silicocn

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Now modulators : simple background ?

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• Large index change : smaller voltage, smaller VL andhigher efficiency

– III-V : Plasma dispersion + birefringent + Kerr + Pockels + Franz-Keldysh (EAM) + Quantum-confined Stark (EAM)

– Si: Plasma dispersion

• The plasma dispersion effect is related to the density of free carriers in a semiconductor, which changes both the real and imaginary parts of the refractive index.

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Modulator structure options

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• Structure: pn, pin, MOS capacitor• Travelling wave electrodes

• Structure: pin, pn• Sensitive to temperature process

0.005 mm

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Heterogeneous direct and EAM III-V DFB Laser on Silicon

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III-V

III-V-on-silicon laser structure

III-V Lab

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IMEC Mach-Zehnder modulator

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IMEC Ring modulator

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IMEC GeSi EAM

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56Gb/s

3dB = > 50GHz

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Sicoya Node Mached Diode modulator

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• 1D photonic crystal cavity• Waveguide width: 450 nm• Waveguide height: 220 nm• Footprint: < 100 µm²• ∆V -> ∆n -> ∆λ• ∆T on-off modulation • Extinction ratio: 3.6 dB

• Signal / noise ratio: 10.2• Insertion loss: 2-3 dB

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Success story mentioned by Finisar Chris Cole (VCSEL man)

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Needs SiP ecosystems at Korea

설계 공정 패키지 Test Users

현재

미래

New PDK SW

•••••••••국내 SiP 생태계 구축 필요 !!!

Global PDK 소프트웨어

Global foundry

2015

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Amkor & Luxtera co work

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FiberPro SiP wafer test systems

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edX Silicon photonics design by two graduate students

이정수

조정훈

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진행 책임자 주관기관 참여기관 연구비 총연구기간 과제명 사업명 관리기관

종료 김경옥 ETRI - 35억/년 2006.02 -2011.01 실리콘 기반 초고속 광인터커넥션 IC ETRI 지원 KEIT

종료 김경옥 ETRI서울대

(2.5억/년)38억/년 2011.03 -2016.02

실리콘 나노포토닉스 기반 차세대 컴퓨터 인터페이스플랫폼 원천기술개발

ETRI 지원 IITP

진행 김경옥 ETRI - 4억/년 2015.12~2018.12 실리콘 포토닉 3D 인터커넥트 플랫폼 기술 개발 과학기술연구회 ETRI

진행 이종무ETRI

1(+1)억/년(민간투자)

서울/KAIST연세/인하대

5(+5)억/년(민간투자)

2013.06~2018.05 Optical interconnection을 이용한 차세대 BEOL 기술산업원천

(+민간투자)(미래소자사업)

KEIT

종료이종무

ETRI3.1억/년

( EU 주관)

파이버프로(+EU 4개국 7

개 기관)

4.2억/년(+EU 20억/년 )

2013.12~2016.11.실리콘 포토닉스 기반 SDN용 12채널 4x8 광스위치모듈 개발

EU H2020국제공동

KIAT(+EU정부)

종료 이상수 ETRI PPI 2.0억/년 2012.03~2015.02CMOS 포토닉스 기반 2.5Gbps x32 채널 라인카드용송수신 집적화 모듈 개발

산업원천 IITP

진행 정환석 ETRI - ?? 2015.03~2020.02실리콘 포토닉스기반 저누화(low-crosstalk) 광역다중화기 기술

ETRI 지원 IITP

종료 최우영 연세대 - 3억/년 2012.05~2015.04 Silicon기반 지능형 고속전자·광자 송수신기 집적회로 중견연구자 NRF

종료 조문호 포항공대 - 1.5억/년 2010.05~2015.04 광대역 실리콘 광전 집적 소자 중견연구자 NRF

종료 안동환 국민대 - 0.6억/년 2013.12~2016.11초고집적 CMOS 반도체칩과 융합 가능한 실리콘 광인터커넥트의 아키텍쳐 및 핵심 나노광소자 개발

일반연구자 NRF

종료 김경헌 인하대 - 0.5억/년 2013.06~2016.05 실리콘 광도파로 기반 저손실 광신호 처리 소자 연구 일반연구자 NRF

진행 이상수 OptellarGIST/ETRI/중

소업체11억/년 2016.04~2019.04

실리콘 포토닉스 집적화 기반 25Gbps급 다채널 O-밴드 optical connectivity 기술 개발

방송통신산업기술

IITP

진행 오원석 KETI연세대/옵토

위즈12억/년 2016.05~2021.04

실리콘 포토닉스 기반 집적형 초고속 저전력 광송수신 부품 및 모듈 개발

소재부품 KEIT

진행 신양수 하이솔루션 인하대 3.5억/년 2016.12~ 2018.9 100G CWDM4 광트랜시버 실리콘 포토닉스 칩 개발 기술혁신과제 중기청

진행 오원석 KETI옵토위즈/ 외국기관

6(33억)/년(총) 2017.12~2021.12광전집적 기술을 활용한 데이터센터용 초고속, 저전력 송수신 부품 원천기술 개발

산업핵심기술 KEIT

Silicon Photonics 정부 과제

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Conclusions : Did MPW/Foundry/Fabless succeed ???

✓ First PDK came about

✓Fab-less SMEs emerged

✓ First standardized packaging offer

✓ First EU CMOS Photonics MPW runs started in 2006

by ePIXfab (and OPSIS @ USA in 2011)

✓ Primary users of Si Foundry were academic and

now up to 40% industry

✓ Process standardization (220SOI, Implanted Modulators,

GePD, 500nm WG etc.)

industry

Academic

PDK Library Size

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