smta-gdl_smta-gdl_DFM_presentation_2012-07

  • Upload
    tnchsg

  • View
    218

  • Download
    0

Embed Size (px)

Citation preview

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    1/263

    Design for Manufacturability

    (DFM)Design for Assembly (DFA)

    SMTA

    Guadalajara Mexico

    July 12, 2012

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    2/263

    Welcome!!!

    Joe [email protected]

    ITM ConsultingDurham, New Hampshire

    USA

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    3/263

    Joe Belmonte Motorola Information System Group

    Mansfield Massachusetts (MA), USA

    1978 to 1995

    Manger of Advanced Manufacturing Engineering

    Speedline Technologies

    (MPM, Camalot, Electrovert)

    Franklin MA, USA

    1995 to 2007

    Director of Applications Engineer and

    Principal Consultant

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    4/263

    Joe Belmonte Bose Corporation

    Framingham MA, USA

    2007 to 2009Director of Advanced Manufacturing Engineering

    ITM ConsultingDurham New Hampshire, USA

    2009 to PresentPrincipal Consultant

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    5/263

    Whatever comes out of thesegates, we've got a better

    chance of survival if we worktogether. Do you understand?If we stay together, we survive.

    Gladiator Movie Quotes by Author Unknown

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    6/263

    Seminar Agenda Definition of DFM

    Customer Satisfaction Requirements

    Functional Responsibilities of DFM

    Concurrent Engineering

    Early Supplier Involvement Well Defined Development Process

    Defining a Process

    Six Sigma and Statistical Thinking

    Understanding and Controlling Process

    Variation

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    7/263

    Seminar Agenda

    Inspection and Test Planning

    Process Characterization Concepts

    Stencil Design

    Evaluating Printed Circuit Board Designs

    Software

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    8/263

    The significant problems we

    face cannot be solved at thesame level of thinking we were

    at when we created them-- Albert Einstein

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    9/263

    We are what we repeatedly do.Excellence, then,

    is not an act, but a habit.

    -- Aristotle

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    10/263

    Ultimate Purpose of DFM/DFA is

    Customer Satisfaction!!!!!

    Quality Reliability

    Cost

    Delivery

    Features

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    11/263

    Design for Manufacturability

    Design for Manufacturability must includea detailed understanding of the processes

    that will be used to build the product, howthe processes are developed, how theprocesses are controlled, and howcontinuous improvement is accomplished.

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    12/263

    DFM&DFA GuidelinesThe two most important documents the

    electronic assembler should have are:

    Workmanship Standards

    Design for Manufacturability andAssembly (DFMA) Guidelines

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    13/263

    Design forManufacturability

    Definitions

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    14/263

    Design for Manufacturability

    Design for Manufacturability is the process bywhich every aspect of the product and

    process design is formally evaluated to insurethe lowest possible product cost, the fastestpossible process cycle time, and the highestpossible first pass yield.

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    15/263

    Design for Manufacturability

    Designing a product to be produced in themost efficient manner possible (in terms of

    cost, resources, and time) taking intoconsideration how the product will beprocessed, utilizing the existing skill base

    (and avoiding the learning curve) to achievethe highest yields possible

    Phil Zarrow

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    16/263

    Design for ManufacturabilityDesign for Manufacturability is the method for creating

    robust product designs that will be insensitive tolong-term dynamic variation in the processes andmaterials used in the manufacturing and will beimmune to foreseeable misuse of the product in theenvironment in which it is used. -- Motorola

    DFM is the process whereby manufacturing and testengineers influence the product design to make itas manufacturable and testable as possible by

    minimizing cycle time, reducing parts, usingstandard processes and maximizing test coverage.-- Dave Reed, 3COM

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    17/263

    What is DFM&DFA ?

    Design for Assembly (DFA) - is a technique which willminimize total product cost by targeting: (this is the processside of product transformation process)

    Parts Count (This is the major cost driver in Mfg.)

    Assembly Time Part Cost

    The Assembly Process

    Design for Manufacturing (DFM) - is a technique forminimizing fabricated part cost: (this is the material and toolingside of the product development process)

    Optimizing the Fabrication Process Material Selection

    Part Cost

    Tooling Strategies to reduce cost

    Tooling Cost Estimates

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    18/263

    Customer SatisfactionRequirements

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    19/263

    Customer Satisfaction Requirements

    A customer has a right to expect the productto be delivered without defects

    A defect is any variation of a requiredcharacteristic of the product or its parts, which isfar enough removed from its target value to

    prevent the product from fulfilling the physicaland functional requirements of the customer

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    20/263

    Customer Satisfaction Requirements

    A customer has a right to expect the productto be delivered when promised

    Every occurrence of a defect within themanufacturing process requires time to analyze,repair, and test.

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    21/263

    Customer Satisfaction Requirements

    A customer has a right to expect the productnot to experience early life failure

    Early life failures are the result of latent defects,or abnormalities, which will cause failure at somefuture time, depending on the degree of

    abnormality and amount of applied stress. Latentdefects are not detectable by normal test orinspections.

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    22/263

    Customer Satisfaction Requirements

    A customer has a right to expect the productnot to fail excessively in service

    If the product design is robust, it will beinsensitive to long-term dynamic variation in theprocess and materials used in manufacturing

    and will be immune to foreseeable misuse of theproduct in the environment in which it is used.

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    23/263

    Customer Satisfaction Requirements

    Delivered defects are directly proportional tothe total number of defects found in the entire

    manufacturing process. Average cycle time per unit is directly

    proportional to the total number of defects perunit.

    Latent defects are directly proportional to the

    total number of defects found in the entiremanufacturing process.

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    24/263

    Customer Satisfaction Requirements

    Reducing the total number of defects per unitin the entire manufacturing process will:

    Reduce delivered defects

    Reduce the cycle time per unit

    Reduce early life failure rate

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    25/263

    Customer Satisfaction Requirements

    Reduced total defects per unit will result in:

    Increased customer satisfaction

    Reduced warranty cost

    Reduced manufacturing cost

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    26/263

    FunctionalResponsibilities of DFM

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    27/263

    Functional Responsibilities:Development Engineering (Product Design)

    Using supplied capability studies for suppliers andinternal processes, design for 6 sigma performance

    for both supplier and internal processes Set supplier piece part specifications at 4.5 sigma

    based on supplier capabilities.

    Calculate sub-assembly tolerances statistically, thencheck the prototypes against the calculations. Whenchanges are made in components, maintain up-to-

    date assembly output calculations.Supply calculations to assist in new product start upsManufacturing provides performance data to development

    for use in next product design

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    28/263

    Design for Assembly DFA

    Reduced part count is the MAJORadvantage to practicing design for

    assembly DFA

    Part count drives/touches every aspectof an organization

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    29/263

    Design for Assembly DFA

    Are all parts of the

    assembly REQUIRED tomeet the function of thedesign?

    Are these parts required toMOVE relative to each

    other?

    Yes - this partmay berequired

    No

    Yes - this partmay berequiredNo

    Yes - this partmay berequired

    No

    Yes - this partmay berequired

    No

    Must this part be made ofDIFFERENT MATERIALthan other parts in theassembly?

    Is this part NECESSARYfor disassembly or serviceof this assembly?

    Unnecessary Parts Test

    Part is a candidate for elimination

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    30/263

    Building better products requires a goodcomparative perspective about othercompanies to gain insight into othersources of outstanding performance

    Product Development Performance

    Kim Clark & Takahiro Fujimoto

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    31/263

    Definitions

    Benchmarking Is the continuous process of measuring products,

    services and practices against the toughest competitorsor those recognized as industry leaders.

    Competitive Intelligence Is the process of gleaming and combining disparate

    information about a competitor in order to deduce itsobjectives.

    Reverse Engineering Is the systematic dismantling of a product to understand

    its technology with the purpose of replication.

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    32/263

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    33/263

    B th d D h t DFMA

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    34/263

    Boothroyd Dewhurst DFMA

    Software Tools and Services Founded in 1985 in Wakefield Rhode Island

    USA

    Provides product design and productmanufacturability software tools and

    consulting services

    F i l R ibili i

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    35/263

    Functional Responsibilities:Component Engineering

    At the time of component qualification, display in thecomponent qualification report the actual data on

    each critical parameter. Show any corrective actionrequired by the supplier so that all parties are awareof what must be done to finish qualification of the

    part to make it acceptable. Mechanical dimensions must be qualified to the

    same design margins as those of electrical

    parameters. This will be done when supplier data forthe first piece parts is scrutinized.

    F i l R ibili i

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    36/263

    Functional Responsibilities:New Product Introduction Engineering

    Work as closely as possible, as early as possible,with the product development team to insure all

    aspects of manufacturability and testability are builtinto the product design from its inception. Work as amember of the product development team.

    Coordinate and communicate with all concernedgroups (manufacturing, sustaining engineering,development, purchasing, component engineering,

    quality, marketing, sales, etc.) the productdevelopment status at each step of the process.

    F ti l R ibiliti

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    37/263

    Functional Responsibilities:Process/Manufacturing Engineering

    Perform process capability studies on allexisting processes and place under statisticalcontrol. Supply current capability to productdevelopment engineers.

    Start a procedure of process improvementthat brings performance of each process tosix sigma levels. As processes improve,

    update development engineering on the newcapabilities.

    F ti l R ibiliti

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    38/263

    During the prototype and pilot runs, every failuremust be treated as either a parametric or catastrophic

    failure, and its source must be corrected by design orprocess improvements. This applies both to internalfailures and supplier failures.

    At prototype and pilot runs, and in conjunction withproduction personnel, re-check the process capabilitydata to ensure nothing has changed. Maintain

    statistical control and statistically analyze for designmargins to six sigma. Identify each failure and treat

    as described.

    Functional Responsibilities:Process/Manufacturing Engineering

    F ti l R ibiliti

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    39/263

    Perform specification compliance evaluations

    Perform accelerated life/reliability evaluations

    and statistical analysis on all criticalparameters. Report the actual designmargins found in the finished product toproduct design and manufacturing.

    Functional Responsibilities:Product Quality Engineering

    F nctional Responsibilities

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    40/263

    Calculate process capabilities (Cp/Cpk) oneach new piece of equipment or new processbefore turning them over to manufacturing.

    The manufacturing engineer responsible for

    the new equipment or process will verify it inproduction mode and establish thecapabilities and statistical controls (SPC) for

    ongoing manufacturing.

    Functional Responsibilities:Advanced Manufacturing Technology

    Functional Responsibilities:

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    41/263

    Develop supplier process capabilities andfurnish them to development engineering.

    Work with suppliers to improve processcapabilities when the design cannot tolerate

    variation in the suppliers existing processes. Ensure supplier compliance to SPC

    requirements and require that proof of control

    is supplied with each lot of material.

    Functional Responsibilities:Supplier Component Engineer and Purchasing

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    42/263

    ConcurrentEngineering

    N P d t D l t P

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    43/263

    New Product Development Process

    P d t D l t P

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    44/263

    Product Development Process

    DFMA process and tools can be applied throughoutthe product development cycle

    The Cost of Making Changes

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    45/263

    According to President Hiroshi Hamada, Ricoh did not detect aproblem with one of its copiers until the machines were shipped tocustomers.Had the problem been corrected earlier, before the start ofproduction, he estimated the cost of correcting the problem atvarious stages as follows:

    At the design phase: $ 35

    Before procuring parts: $177Before start of production: $368

    Instead, the cost of correcting this problem was:

    $590,000.00

    The Cost of Making Changes

    Wh C t th Bi t Sh d ?

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    46/263

    Who Casts the Biggest Shadow?

    Design 5%

    70% 20%

    Material50%

    5%

    Labor15%

    5%

    Overhead30%

    Influence

    Product Cost

    Adapted from Ford Motor Co.

    D i f M f t bilit

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    47/263

    Design for Manufacturability

    75 to 90% of project/product costs

    are determined during the first

    7 to 8% of development time.

    -- Paul Collins Ph.D., University ofWashington and Strategy ResearchApplications

    C t E i i

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    48/263

    Concurrent Engineering

    Concurrent Engineering is a competitive strategyattempting to simultaneously achieve a portfolio of

    benefits in time, money, and novelty (features). Concurrent Engineering involves multiple functions

    involved in decision-making on product design so

    that downstream issues such as manufacturability,marketability, serviceability, and total life cycleproblems are anticipated at very early productdesign stages.

    -- Paul Collins Ph.D. University of Washington and Strategy ResearchApplications

    C t E i i

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    49/263

    Concurrent Engineering

    Product Development Time Reductions:

    40% to 67%

    Product Development Costs reductions:16% to 46% for Telecommunications

    55% to 95% for Aerospace

    Engineering Rework Reductions:

    50% to 54%

    -- Paul Collins Ph.D. University of Washington and Strategy Research Applications

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    50/263

    Early SupplierInvolvement

    Early Supplier Involvement

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    51/263

    Early Supplier Involvement

    Capture the vendors know how and experienceearly.

    Share a commitment to the product by workingtogether from the start.

    Optimize the part design to take advantage of the

    vendors capabilities and processes. Optimize the part design for ease of manufacture

    with input from the vendor on the emerging design.

    Set target cost for tooling and parts using costmodels to support the products cost goals. Usethis data to open communications with vendors.

    Early Supplier Involvement

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    52/263

    Early Supplier Involvement

    Our customers teach us to be good suppliers;perhaps our suppliers could teach us to be good

    customers. We realize that we are not taking full advantage of

    the benefits of supplier design expertise early

    enough in our design process. Many of ourcustomers have enjoyed these benefits for years.They know the value of supplier-customer designteams.

    Suppliers can help design in quality from thebeginning, and shorten the product developmentcycle time -- Gary Tooker, Motorola

    Early Supplier Involvement

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    53/263

    Early Supplier Involvement

    The early supplier involvement processrequires the trust and openness to share

    critical information between the customer andchosen supplier.

    A supplier must be prepared with personalcapable of responding to the customersrequirements.

    Early Supplier Involvement

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    54/263

    Early Supplier Involvement

    These questions should be asked:Do you have a standard item that can be

    substituted?What are the available manufacturing

    alternatives?

    Can you suggest a material alternative?

    Do you have any suggestions that would

    reduce processing?Are there any product design alternatives that

    can be made to assist you?

    Early Supplier Involvement

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    55/263

    Early Supplier Involvement

    These questions should be asked:Can you evaluate cost versus precision?

    Can you suggest procedures to detect andremedy deviations?

    Does your company have the technicalexpertise available in a time frame appropriateto the customer requirements?

    Do you have any further suggestions thatmight reduce lead time, simplify the part,and/or reduce cost?

    Early Supplier Involvement

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    56/263

    Early Supplier Involvement

    What are ways to insure 100% usablepurchased parts and materials?

    Cpk equal to or greater than 1.5

    Supplier specifications that reflect true critical

    valuesThe specs supplied by the customer mustallow the supplier to use the most efficient

    manufacturing process.Internal policies and procedures must conform

    to the above.

    Benefits of Early Supplier Involvement

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    57/263

    Benefits of Early Supplier Involvement

    Lower development and part cost

    Optimized manufacturability

    Improved part quality

    Improved delivery schedules

    Improved communications Optimized product design

    Benefits of Early Supplier Involvement

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    58/263

    Benefits of Early Supplier Involvement

    Minimized design changes

    Reduced product development time

    Optimized material selection

    Utilized supplier technology

    Standardized parts Calculated Six Sigma design

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    59/263

    Well DefinedDevelopment Process

    Well Defined Development Process

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    60/263

    Well Defined Development Process

    Be documented, graphically and textually

    Key terms are defined

    Documentation is distributed to and understoodby all involved parties

    Be detailed and specific enough to serve as a

    working development blueprint; yet flexibleenough to accommodate products of varyingcomplexity

    Minimize all opportunities for paralleldevelopment

    Well Defined Development Process

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    61/263

    Well Defined Development Process

    Define the items listed for each phase:

    Required inputs and sources

    Constituent steps and tasksPer step/task, roles and responsibilities

    Outputs, including documentation specifications

    Phase entry and exit criteria

    Necessary functional involvement

    Be enforced and monitored

    Well Defined Development Process

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    62/263

    Well Defined Development Process

    A formal review should occur at the end ofeach development phase in order to:

    Detect problems (potential defects) as close aspossible to their point of origin.

    Track and document sources of error and defects.

    Uncover errors, but NOT to fix them (during thereview)

    Confirm outputs that do not require

    improvements.

    Make projects more manageable.

    Characteristics of Formal Phase Reviews

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    63/263

    Cross functional representation, includingcustomers

    Material disseminated in advance Scope of material covers wide spectrum

    May need to occur over several meetings Coordinated by project leader

    Sign-off and follow-up report required

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    64/263

    Defining a Process

    Define the Process

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    65/263

    e e t e ocess The term process means different things to

    different people. So, it is important to clearlydefine what we mean by process.

    A process can be defined as the logicalorganization of people, materials,

    environment, equipment, and procedures intowork activities designed to produce aspecified end result.

    Elements of a Process

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    66/263

    Materials

    Equipment

    Procedures

    PeopleCustomer

    RequirementsProducts &Services

    Environment

    WorkActivities

    A key/critical process is basically a "valued-added" process in the Macro Map whichinhibits achieving 6 sigma quality in our products or services.

    Defining Process Parameters

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    67/263

    g

    Process

    Material

    Design Defects

    OutputParameter(s)

    InputParameter(s)

    ProcessParameters

    Variable

    Characteristics

    Defining Process Parameters

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    68/263

    Input ParametersA measurement system or a parameter in a process that is

    used in the creation of process output.

    Input parameters are materials, methods, measurements,machines, people, and environment.

    Process Parameters

    Steps or activities completed using the input parametersto generate a product or service.

    Output Parameters

    The end result of a process. It may include as little as onlyone specific output on only one product or it my include asmuch as all products and all outputs produced by themachine(s) and/or operation(s) included in the process.

    Identifying Parameters

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    69/263

    y g

    Choosing those parameters that will be the leadingindicators to the quality level being produced by the

    process.

    Those parameters that have the most

    significant impact to the next process,clients or our customer.

    Process

    Material

    Design Defects

    OutputParameter(s)

    InputParameter(s)

    ProcessParameters

    VariableCharacteristics

    Process Mapping

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    70/263

    Understanding the flow of the process, allinputs, outputs, of each process steps.

    Macro-Map : Macro-Mapping is the process ofcharting the coarse flow of an operation (such asa manufacturing line).

    Micro-Map : Micro-Mapping breaks down aprocess in the Macro-Map into severalconsecutive sub-steps (identifying all inputs andoutputs).

    ProcessA

    ProcessB

    ProcessC

    OutputProduct or

    Service

    InputParameter(s)

    Methods Used to Identify Parameters

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    71/263

    Brainstorming Techniques

    Prioritization Matrix

    Cause and Effect Diagrams (Fishbone)

    Modified Cause and Effect Diagrams

    Weighted Voting Affinity Diagrams

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    72/263

    Six Sigmaand

    Statistical Thinking

    ConditionConditionConditionCondition

    CapabilityCapabilityCapabilityCapability 1111 2222

    AAAA

    Condition 2Condition 2Condition 2Condition 2:

    Distribution AverageDistribution AverageDistribution AverageDistribution Average

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    73/263

    CCCC

    AAAA

    BBBB

    -6s -5s -4s -3s -2s -1s 1s 2s 3s 4s 5s 6s

    LSLLSLLSLLSL USLUSLUSLUSLNominalNominalNominalNominal

    CCCC pppp ==== ==== 2.02.02.02.0 2.02.02.02.0

    AAAA

    BBBB

    CCCC pkpkpkpk ==== ==== 2.02.02.02.0 1.51.51.51.5CCCC

    0.5 B0.5 B0.5 B0.5 B

    Condition 1: DistributionCondition 1: DistributionCondition 1: DistributionCondition 1: DistributionAverage Centered onAverage Centered onAverage Centered onAverage Centered on

    Normal SpecificationNormal SpecificationNormal SpecificationNormal Specification

    Distribution AverageDistribution AverageDistribution AverageDistribution Average

    Shifted 1.5s from theShifted 1.5s from theShifted 1.5s from theShifted 1.5s from theNominal SpecificationNominal SpecificationNominal SpecificationNominal Specification

    LCLLCLLCLLCLLCLLCLLCLLCL UCLUCLUCLUCLUCLUCLUCLUCL

    LSLLSLLSLLSLLSLLSLLSLLSL

    USLUSLUSLUSLUSLUSLUSLUSL

    What is Six Sigma?

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    74/263

    A discipline of continuous improvement toachieve Total Customer Satisfaction.

    Implement Permanent Corrective Actions

    Prevent Recurrence Control the Process Standardization Redesign

    4 - Action

    Define Goals and Targets

    Recognize Parameters Identify Key Opportunities Identify Key Processes

    Improvement Plan Select Project/Team1 - Plan

    Measure Improvement Assess Effectiveness Review Projects

    3 - Check Education and Training Implementation

    2 - Do

    Key Factors for Success

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    75/263

    Management LeadershipTop down

    Committed

    Clear & Aggressive Goals

    Breakthrough Thinking Training (Black Belt Program)

    Reinforcing Successes

    Drive Six Sigma Quality through StatisticalThinking and Analytical Problem Solving

    Six Sigma Key Initiative Challenges

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    76/263

    The achievement of Error Free Performance inProducts, Processes and Services

    Six Sigma Quality - 3.4 defects per million opportunities

    Total Cycle Time Reduction - 10x improvement every 2years

    Six Sigma Designs

    Process and Supplier CharacterizationVariation Reduction in Processes and Designs

    Cp/Cpk > 1.5

    Total Customer Satisfaction

    Software Quality - SEI

    Six Sigma is a highly disciplined and quantitative

    approach to improvements

    Five Myths of Statistical Thinking &

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    77/263

    Analytical Problem Solving Only works in manufacturing

    Is added effort, takes too long

    Requires large teams

    Creates a lot of bureaucracy

    Just another quality program

    The Role of Continuous

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    78/263

    Improvement To achieve consistency in our processes, we

    need to reduce variation. But, how do we:

    Measure the current levels of variation?

    Decide what to work on next?

    Know we have improved? To answer these questions, we must have a

    process and associated tools. It is here thatstatistics and statistical thinking play a majorrole.

    The Role of Statistical Thinking

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    79/263

    in Continuous Improvement Statistics: The science of turning data into information formaking business or engineering decisions in the presence ofuncertainty. The electronics business is a data-drivenindustry. We apply statistical methods to enable us to makequantitative statements in the presence of variability.

    Statistical methods are like a microscope is to a scientist.

    They help us focus our expertise on the solution of theproblem at hand.

    Why Does Statistical Thinking Work?

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    80/263

    Creates Bottom Line Results ($)

    Uses a Disciplined Approach

    Managed by Data Approach Sound Statistical & Problem Solving

    Approach

    Creates Proficient Quality Professionals

    Standardized Approach that works Across

    Processes, Products and Organizations.

    Statistical Thinking is

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    81/263

    Different and it Works Focused ApproachPhased Improvement Methodology

    Define, Measure, Analyze, Improve and Control

    Understanding and reducing variation are keys tosuccess.

    Statistical Thinking is a way of thinking, athought process, rather than a method ofcalculating.

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    82/263

    Process Variation

    Components of Variation

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    83/263

    ProcessProcessProcessProcess

    MaterialMaterialMaterialMaterial

    OperatorOperatorOperatorOperator

    EnvironmentalEnvironmentalEnvironmentalEnvironmental

    MeasurementMeasurementMeasurementMeasurement

    In all aspects of theprocessunderstand and control

    What Is Variation?

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    84/263

    Common CauseNatural, expected variation

    Difficult to identifyCannot be eliminated

    DOE can reduce Controllable Ex: Solder Paste Parameters,Temp, R/H, Lead Co-planar.

    Special CauseUnnatural, not expected

    Easily IdentifiedCan be eliminated Ex: Paste dried out onstencil, machine fail, settingchanged w/o OKNever change operatingparameters for special cause

    variation (do not tweak!!!)

    Types of DefectsSpecial & Common Causes

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    85/263

    SPECIALCAUSE!!

    COMMON

    CAUSES!!

    SPECIALCAUSE!!

    UCL

    LCL

    Identification of Special

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    86/263

    and Common CausesCorrective Action : SPC rule violations

    "Special Cause - changes, anomalies, unusual events

    "Common Cause - shift in mean, trend in mean,increased variability "

    Implement contaminate plan, and monitor for repeat

    occurrences.-Stop defects from escaping to next process-Keep process in operation while permanent corrective action isimplemented

    For repeat occurrences tie specific cause to corrective actionusing problem solving methods.

    Never change operating parameters

    for Special Cause Variations

    Process TweakingThe definition that best describes tweaking in the

    f

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    87/263

    electronics manufacturing industry is: To touch something up, fiddle with the finishing touches

    or make tiny little changes. In our industry, tweak is

    usually used in sentences such as I just have to tweak alittle bit here and there and it will be perfect.

    That usually leads to a statement such as "I just tweakedthis and THIS AND THIS AND THIS and this and OH NO

    now this...

    If we have done our formal process developmentand optimization, we are monitoring the process

    using statistical process control (SPC), andunderstand the concepts of common cause andspecial cause variation, we should be adamantabout NEVER tweaking the process.

    Process Tweaking What operating parameters should I allow my

    dj ?

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    88/263

    operators to adjust?NONE!!!!

    But my operators are very well trained andhave all worked with the process for manyyears. With their knowledge and experienceshouldnt they be given the authority to change

    operating parameters to optimizeperformance?

    NO

    No process operator, no matter howknowledgeable or how experienced, shouldever be allowed to adjust ANY operating

    parameter under ANY circumstances.

    The Funnel Experiment

    Th i ti f

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    89/263

    IndividualsIndividualsIndividualsIndividuals X CHARTX CHARTX CHARTX CHART

    8

    8.59

    7.5

    7

    0

    1

    2

    RANGE CHARTRANGE CHARTRANGE CHARTRANGE CHART

    Showing the spread of individualsShowing the spread of individualsShowing the spread of individualsShowing the spread of individualson and Xbar and R chart.on and Xbar and R chart.on and Xbar and R chart.on and Xbar and R chart.

    The variation of a processreacts to adjustmentsmade to improve the

    process.

    Dr. Deming discusses 4different methods thathave been commonly

    used to adjust processes.

    Rule 1

    L th f l fi d

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    90/263

    XXXX

    Rule 1Rule 1Rule 1Rule 1

    Leave the funnel fixed,aimed at the target, noadjustment.

    Results: this is by far thebest choice. Rule 1 will

    produce a stabledistribution of points. Itproduces minimumvariance on any diameter

    drawn through the target

    Rule 2

    Adj st for the error b

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    91/263

    XXXX

    Rule 2Rule 2Rule 2Rule 2

    Adjust for the error bymoving the target theerror distance in the

    opposite direction of itslast position.

    Tweaking! Never do it.Produces a stableprocess, but higher

    variance than rule 1.

    Rule 3

    Adjust for the error

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    92/263

    XXXX

    Rule 3Rule 3Rule 3Rule 3

    Adjust for the errorby moving the targetthe error distance in

    the oppositedirection of thetarget

    Worse than tweakingexplodes.

    Rule 4

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    93/263

    XXXX

    Rule 4Rule 4Rule 4Rule 4

    Set the funnel at eachdrop right over where

    it last hit.

    Explodes

    Relate to Traveling to Work:

    Goal 7 00 AM Arrival

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    94/263

    Goal 7:00 AM Arrival

    XXXX

    Rule 1Rule 1Rule 1Rule 1

    Rule 1: Choose a reasonable routeand consistently follow the route

    leaving your home at the same timeeach day.

    Day Departure Arrival

    1 6:30 a.m. 7:05 a.m.2 6:30 a.m. 6:58 a.m.3 6:30 a.m. 6:55 a.m.4 6:30 a.m. 7:00 a.m.

    5 6:30 a.m. 7:02 a.m.

    Rule 2

    Compensate the amount of time you

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    95/263

    XXXX

    Rule 2Rule 2Rule 2Rule 2

    Compensate the amount of time youarrived at work early or late byleaving your home that much earlieror later, and continue

    adjusting youre departure each daybased on the previous daysdeparture.

    Day Departure Arrival1 6:30 a.m. 7:05 a.m.2 6:25 a.m. 6:50 a.m.3 6:35 a.m. 7:15 a.m.4 6:20 a.m. 7:00 a.m.

    5 6:20 a.m. 6:50 a.m.

    Rule 3

    Compensate the amount of time you arrivedt k l l t b l i h

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    96/263

    XXXX

    Rule 3Rule 3Rule 3Rule 3

    Compensate the amount of time you arrivedat work early or late by leaving your homethat much earlier or later than the originaldeparture time, and continue adjusting your

    original departure time each day based onhow early or late you were the previous day.

    Day Departure Arrival

    1 6:30 a.m. 7:05 a.m.2 6:25 a.m. 6:50 a.m.3 6:40 a.m. 7:15 a.m.4 6:15 a.m. 6:40 a.m.5 6:50 a.m. 7:25 a.m.

    Rule 4

    Compensate the amount of time you arrived at

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    97/263

    XXXX

    Rule 4Rule 4Rule 4Rule 4

    Compensate the amount of time you arrived atwork early or late by leaving your homeat the previous days arrival time, and continueadjusting your departure time each day based on

    the time you arrived the previous day.

    Day Departure Arrival1 6:30 a.m. 7:05 a.m.

    2 7:05 a.m. 7:30 a.m.3 7:30 a.m. 8:15 a.m.4 8:15 a.m. 8:45 a.m.5 8:45 a.m. 9:20 a.m.

    What Process PerformanceMetric is Important

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    98/263

    The bottom line the only metric that measureshow well a process line is performing is how

    many good products are built each day.How many of what we build today can we ship toour customers?

    Good product is one built in an acceptable time thatpasses all required testing the first time without anyinspection, touch-up, or repair.

    Cycle Time/Throughput Balance

    There is a definite balance between product cycle

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    99/263

    There is a definite balance between product cycletime (how long it takes a product to get frombeginning to end of the manufacturing process) and

    the quality of that product.Producing defective product just to achieve somerequired cycle time is certainly not acceptable; nor is

    slowing the process unduly to minimize everypossible defect.

    We must understand and optimize this balance.

    I ti

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    100/263

    Inspection

    andTest

    Planning

    Inspection & Test Planning

    All inspection and test processes are NON

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    101/263

    All inspection and test processes are NONVALUE ADDED functions.

    Inspection and test processes should be keptto a minimum.

    Focus on capable, stable processes to

    produce products that will minimizes therequirement for inspection and test.

    Inspection & Test Planning

    Inspection and test planning is the activity of:

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    102/263

    Inspection and test planning is the activity of:

    Designating the stations at which inspection ortest should be performed.

    Establishing the effectiveness of each inspectionand test process.

    Identifying which process contributes the mostdefects.

    Inspection & Test Planning

    How can Inspection & Test Planning assist in

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    103/263

    How can Inspection & Test Planning assist inQuality Planning ?

    Knowing the observed defect level, inspectionand test effectiveness, we can estimate thesubmitted defects and escaping defects.

    Inspection & Test Planning

    For example:

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    104/263

    For example:

    Observed Defects = 0.25 dpu

    Insp. Or Test Effectiveness = 0.8Submitted Defects = 0.31 dpu (0.25/.8)

    Escaping Defects = 0.06 dpu (0.31 - 0.25)

    Inspection

    or Test

    Process

    Submitted Escaping

    Observed

    How can Defect Level Constraints be

    used in Process Design?C t t t d fl di m f th

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    105/263

    used in Process Design? Create a structured process flow diagram for theentire set of assembly operations for the product,

    identifying:All inspection/test points.

    Include the nonconforming product found at eachinspection/test point.

    Establish maximum defect/unit level for the deliveredproduct.

    Working from the start of the process to the end,estimate the defect/unit entering, escaping eachprocess step using actual factory data and theeffectiveness of the inspection or test process.

    How can Defect Level Constraintsbe used in Process Design?

    If th ti t d d li d f t/ it i

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    106/263

    If the estimated process delivery defect/unit isgreater than the maximum allowed:

    Revise the process flow where necessary by: Redesigning the operations for increased process

    capability to produce fewer defects.

    Implement Statistical Process Control and Design ofExperiments (DOE) to reduce process variation.

    Inspection or Test

    Process Effectiveness

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    107/263

    Inspection

    or TestProcess

    SubmittedDefects

    Escaping

    Defects

    Observed

    Defects

    Submitted Observed Escapes

    1,487 152 1,335

    0.1375 0.014 0.1235

    10.22 % = (152/1,487) * 100

    Defectsdpu

    Effectiveness

    Process Effectiveness

    Inspection & Test Planning

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    108/263

    Stencil Printing& Placement

    Process

    d0 Pre-ReflowInspection

    Reflow Process Post-ReflowInspection

    TestProcess

    d1 d2 d3 d4 d5

    dnSupplier0.030dpu

    0.1075dpu

    0.014dpu

    0.0528dpu

    0.029dpu

    0.1159dpu

    0.1375dpu

    0.1235dpu

    0.1763dpu

    0.1473dpu

    0.0314dpu

    Observed Escapes

    152 1,335

    0.014 0.1235

    10.22 %

    Defectsdpu

    Effectiveness

    Observed Escapes

    317 1,588

    0.029 0.1473

    16.64 %

    Observed Escapes

    1,251 340

    0.1159 0.0314

    78.62 %

    Pre-IR Inspection Post-IR Inspection Test Process

    Inspection & Test Planning:

    Summary Eliminating defects is the most important key

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    109/263

    Summary Eliminating defects is the most important keyto achieving a World - Class Manufacturing

    Operation. Defects per unit is the best measure of actual

    total product quality because it allowsprediction, analysis, planning andbenchmarking by product / process

    development teams

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    110/263

    Process

    Characterization

    Concepts

    Process Characterization

    Process Characterization is a technique to

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    111/263

    Definition

    Process Monitoring

    Process Stability

    Process Output

    1

    2

    45

    identify and minimize sources of variation inour processes and to obtain an understandingof the quantitative effects of the processinputs on the process outputs.

    Statistical methods are employed throughoutthe process characterization program toisolate sources of variation to meet stability

    and capability requirements.

    1

    Eight Steps to Process

    Characterization

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    112/263

    ProcessDefinitionProcessMonitoring

    Institutionalize andDocumentation

    Process Capability

    ProcessStability

    Measurement EquipmentAssessment

    Selection of

    Process Outputs

    1

    2

    3

    4

    5

    6

    8

    7

    Machine Acceptance

    Characterization

    Prevention vs. Reaction

    Machine Acceptance Studies

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    113/263

    Statistically confirms machine operation

    Reduces special cause variation due tomachine operation

    Minimizes loss of production time

    Minimizes machine down time

    Defect ReductionMethodology Process

    Characterization Approach

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    114/263

    Process

    MaterialDesign

    Defects

    OutputParameters

    1. Identified, Cpk=1.5

    2. Identified, Cant Measure

    3. Have Not Identified

    InputParameters

    DOEs;Optimization,

    Control

    Defects Are Caused ByMany Parameters

    Evidence of ProcessCharacterization Methodology

    Process Focus

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    115/263

    Attribute and Variable Data

    Terminology of Cp/Cpks

    Identifying Process Parameter to Study

    Performing Capability Studies

    Optimizing the Process

    Implementing Process Controls

    Identifying Additional Critical Parameters Reuse Of Other Facilities Findings

    Use of DOEs & Statistical Methods Apparent

    Correlating Parameters to Actual Process Improvement

    Process Characterization

    Methodology Is a way of understanding controlling and coping with

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    116/263

    gy Is a way of understanding, controlling and coping with

    variability - that is managing variability.

    Management Commitment to Statistical Data Analysis andProblem Solving

    Implement Statistical Process Control (SPC) to monitor keyprocess parameters

    Daily Quality Meetings

    Root Cause Corrective Actions

    Measurement Systems Analysis

    Design of Experiments

    Continuous Process Improvements

    SPC Audits

    Process Characterization

    Methodology Results:

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    117/263

    gy Results:

    Reducing Defect Rate (dpu), Cycle Time, Repair

    costs, and increasing Productivity.

    Increasing the time the process is in an ideal state.

    Decreasing the process variability.

    Increasing the time that the process characteristicsmean remains at its target value or remainsconstant at acceptable level.

    Reducing the number of out of control conditions onSPC .

    Intent and ExpectationQuality Goals

    Material Defects

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    118/263

    Process

    Material

    Design

    Defects

    OutputParameters

    1. Identified, Cpk=1.5

    2. Identified, Cant Measure3. Have Not Identified

    InputParameters

    DOEs;

    Optimization;Control

    2

    3

    1

    2

    1. Institutionalize statistical methods based problem solving techniques

    2. It is more important to identify (and control) additional parameters that have an impact on actualprocess performance than to pursue parameters that have a low impact on actual process performance .

    3. Quality reviews should address the impact of process characterization efforts on reducing DPU. Thisis expected to be qualitative at first and should become quantitative as time progresses.

    Evolution of Continuous Improvementin the Reduction of Variation

    Before Using

    Statistical Methods

    SPC

    Implementation

    Utilizing Design

    of Experiments

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    119/263

    LSL USL

    The Process is not incontrol, not predictable.

    USLLSL

    Using SPC, the process is in

    control, but its capability is poor.

    USLLSL

    Using DOE & problem

    Solving techniques, theprocess capability has improved.

    Link Process Characterizationto DPHU Efforts

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    120/263

    DPHU

    Initial CharacterizationActivity

    Additional Parameter(Identified, Optimized, Controlled)

    Additional Parameter

    Time

    Continuous ImprovementActivity in a Process

    Characterization Environment Involves:

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    121/263

    Involves:Reducing the number of out of control

    conditions.

    Increasing the time the process is in an ideal

    state.Decreasing the process variability.

    Increasing the time that the process

    characteristics mean remains at its targetvalue or remains constant at some acceptablelevel.

    Operations Macro Map Develop Required Process

    Procedures

    Define Statistical/Engineering objectives Identify Machine Response Parameter(s) Define Measurement Tech./Equipment Define Response Parameter(s) Tolerance Measurement R&R Studies Machine Capability , R&R studies, etc.

    MachineAcceptance Studies

    Define Response Parameter(s) Define Measurement Tech. / Equipment Define Response Parameter(s)

    Process

    Definition

    Selection ofProcess Output(s)

    Process

    CharacterizationProcess

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    122/263

    Repeatability andReproducibility

    Study

    ImproveTechnique

    orInvestigate

    ImprovedMeasurementDevice

    Fails

    p ( )Tolerance

    In Control

    Identify Potential Causes Develop Process Micromap Develop Cause & Effect Diagram Test each cause/solution through

    experimentation and statisticaldata analysis or pattern analysis.

    Develop / Revise Problem & Solutionmatrix to Out of Control

    Out of Control

    Identify Common&Special Causes

    Process Capability

    Cp & Cpk > 1.5Process 1.5.

    Process Stability

    Data Collectionfor SPC

    Establish "Best" operatingtarget and range for allcritical input parameters.

    Implement Control Strategyfor all Critical (input)

    Parameters and set totheir optimal levels.

    Achieve Quality Levelsthrough Improvement /

    Optimization Studies. Define Critical Process( input) Parameter(s)

    Process Monitoring(Documentation)

    Long Term Process Monitoring Process Capability Studies Document Process

    Characterization studies.

    Develop SPC Quality Plan

    Process Output(s)

    Set InputControls

    ProcessImprovement /

    Optimization Study

    Passes

    Passes

    Fails

    Requirement

    MeetsCapability

    Process

    To support the Process Characterization initiative, the following matrix of important characteristics should

    Printing Positrol Diagram

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    123/263

    o suppo t t e ocess C a acte at o t at e, t e o o g at o po ta t c a acte st cs s ou dbe available to process engineers for use in their respective processes as required to achieve defect reductions.

    Impor tant Character ist ic Process ToleranceSuggested Measurement

    Equipment

    Suggested Process

    Control

    Solder Paste Viscosity By paste type Viscometer X bar, R control charts

    Stencil Aperture WidthDependent upon Stencil

    Mfgr.Micro view system X bar, R control charts

    Facility Temperature & Humidity By paste type Temp./Humidity gage X bar, R control charts

    Time solder paste sits on stencil10 to 15 min.'s (Paste

    Dependent)

    Equipment's paste knead or

    double print next board

    Equipment's process

    software

    Stencil Wash: IPA - % flux on Board From supplier Omega Meter Process Log

    Stencil Wash: Saponifier - Tr itat ion From supplier Tr itat ion kit from supplier Process Log

    Stencil Quality (Dents, cleanliness, wear &

    tear)

    Not Applicable Visual Inspection Process Log & Audits

    Suppor t Tooling (Placement, Cleanliness,

    Wear & Tear)Not Applicable Visual Inspection Process Log & Audits

    INPUT CHARACTERISTICS

    Supplier materials, methods, machine parameters and environment

    Printing Positrol Diagram

    OUTPUT CHARACTERISTICS

    Produced by machine or operation

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    124/263

    Impor tant Character ist ic Process ToleranceSuggested Measurement

    Equipment

    Suggested Process

    Control

    Solder Paste Height 8 mil +/- 2 mils

    6 mil -1,+2 mils

    Solder Paste Coverage +/- 10% Target Equipment 2D systemEquipments 2D error

    detection system

    Process Defects & Errors Not ApplicableFactory Reporting System,

    Trend Charts

    U-Control chart by process,

    Pareto Charts,

    Solder Paste Volume +/- 30 % of Target CyberSentry or SVS system X bar, R control charts

    CyberSentry or SVS system X bar, R control charts

    Impor tant Character ist ic Process ToleranceSuggested Measurement

    Equipment

    Suggested Process

    Control

    Frequency of stencil wipingEvery 6 to 8 boards (Paste

    Dependent)Not Applicable

    Process audits or automatic

    wiping

    Solder Paste Handling from refr igerat ion Ambient for 24 hrs Not Applicable

    Process Log, date / t ime

    stamp paste container

    OPERATOR DEPENDENT CHARACTERISTICS

    Printing Positrol Diagram

    Impor tant Character ist ic Process ToleranceSuggested Measurement Suggested Process

    PREVENTATIVE MAINTENANCE CHARACTERISTICS

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    125/263

    Impor tant Character ist ic Process ToleranceEquipment Control

    Height of Support nest plate to base Screen printer mfgr. Height Gage PM Logs & Audits

    Stencil holder to base parallelism Screen printer mfgr. Height Gage PM Logs & Audits

    Blade Angle Screen printer mfgr. Calib. to 90 degrees PM Logs & AuditsForce applied to right/left side of print

    headScreen printer mfgr. Calibration on control cards PM Logs & Audits

    Printer Cleanliness (Nest, Stencil, base,

    height sensor, etc.)Not Applicable Visual Inspection PM Logs & Audits

    Squeegee Blade ( Dents and angle ) Not Applicable Visual Inspection Process Log & Audits

    Impor tant Character ist ic Process ToleranceSuggested Measurement

    Equipment

    Suggested Process

    Control

    Operator Certification Program Not Applicable Not ApplicableWrit ten and/or observation

    tests

    OTHER CHARACTERISTICS

    Stencil Design

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    126/263

    Ste c es g

    Paste Flow in Apertures

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    127/263

    OMNIX 5000 Poly Blade

    Type III Powder 25 mil Width

    1.5 in/sec Print Speed 1.5 lb/in Squeegee Pressure

    Solder Paste Release Performance

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    128/263

    10 mil Diameter Aperture

    0.1 in/sec Stencil Release Velocity

    Design Rules For Stencils

    There are two rules used in Stencil Design

    Aspect Ratio Rule

    The aspect ratio rule has been used for a great deal

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    129/263

    The aspect ratio rule has been used for a great dealof time in determining how well solder paste will

    transfer from the aperture to the surface of the printedcircuit board

    Area Ratio Rule

    As smaller components have been used inelectronics products requiring smaller stencilapertures the area of the opening of the aperture and

    the area of the walls of the aperture have becomecloser requiring the use of the area ratio rule in stencildesign

    Aspect Ratio RuleFor Optimal Transfer Efficiency

    Aspect Ratio Ensures that the aperture will allow the printed material to

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    130/263

    release onto the substrate.

    Aspect Ratio - W / t > 1.5 (chem-etch) For Example: 9 mil. aperture min. use 6 mil foil.

    Width > 1.5 x t

    Violation of Aspect Ratio Correct Aspect Ratio

    Reduce aperture size by 20% to your pad size,maintain a minimum of 1.5 aspect ratio of aperturewidth to stencil thickness (25mil pitch and Below)

    Stencils - Aperture DesignTypical Fine Pitch Apertures

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    131/263

    width to stencil thickness. (25mil pitch and Below).

    Minimum Aperture Design Guidelines:

    w

    t

    Aspect Ratio = W / t >1.5

    Width >= 4-5 Particle Diameters

    Design Rules For Stencils Aspect Ratio

    For Fine Pitch QFPs, Aspect Ratio Was The Limiting

    Factor for Printing:

    A t R ti i A t idth (W )

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    132/263

    Aspect Ratio is .. Aperture width (WA)

    Stencil Thickness (TS)A Typical 0.4mm (16mils) Pitch QFP Aspect Ratio is 9 = 1.8

    5

    However as the apertures have become smaller, thearea of the opening of the aperture and the area of theaperture walls have become very much the same.

    Aspect Ratio alone is not the only stencil designcalculation that must be used to insure an optimumstencil design. The Area Ratio must also be used.

    Area Ratio

    Design Rules For Stencils Area Ratio

    Area of the opening

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    133/263

    Area of the aperture walls

    The holding force of the solder paste to the

    printed circuit board pad must be greater thanthe holding force of the solder paste to the

    stencil aperture for the solder paste to release

    from the aperture and attach to the printed

    circuit board pad

    Area Ratio RuleFor Optimal Transfer Efficiency

    Area Ratio Ensures that the forces pulling a material onto the pad

    t th th f h ldi it i th t

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    134/263

    are greater than the forces holding it in the aperture.

    w

    TW

    L

    Pad Pulling Tension (P) Aperture (Length (L) Width (W))

    = 0.6Retaining Wall Tension (R) Stencil Thickness (T) Aperture Perimeter (2 (L+ W))

    Area Ratio for Square andRectangular Apertures

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    135/263

    Area Ratio for Circular Apertures

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    136/263

    Why is Wall/Pad Ratio Important?Area Ratio

    Key process feature for successful fine pitchprinting is paste release from stencil

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    137/263

    printing is paste release from stencil.

    1

    2

    Violation ofArea RatioRule

    Correct

    Area Ratio

    Comparing Aspect Ratio and Area Ratio

    1 mm

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    138/263

    0.25mm

    0.15 mm Stencil

    0.2 mm .(008)

    Circle

    Aperture Wall Area = 0.118 mm2

    Pad Surface Area = 0.049 mm2

    Aspect Ratio = 1.67

    Surface Area Ratio = 0.42

    Rectangle

    Aperture Wall Area = 0.36 mm2

    Pad Surface Area = 0.2 mm2

    Aspect Ratio = 1.34

    Surface Area Ratio = 0.56

    The circle is more difficult to print because of the lowerSurface Area Ratio.

    The aspect ratio is no longer a good indicator as here itsuggests that the circle would be easier to print - it isnt

    Sample Area Ratio Chart

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    139/263

    Relationship:

    Transfer EfficiencyArea Ratio

    Standard Deviation

    100.00%

    120.00%

    200.00

    250.00

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    140/263

    The higher the relative AR,

    the higher the relative FT,the lower the absolute SD

    0.00%

    20.00%

    40.00%

    60.00%

    80.00%

    0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

    Area Ratio (AR)

    TransferEfficiency(F

    0.00

    50.00

    100.00

    150.00

    200.00

    StandardDeviatio

    n(S

    Reduction of Aperture Size

    25 mil 20 mil

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    141/263

    10 mil15 mil

    Paste Release for a 15 mil (.015) Circle

    Paste A SnPb Paste A Lead Free

    15 mil (.38 mm) Dia. Circle (Area Ratio = 0.96)

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    142/263

    Paste B SnPb Paste B Lead Free

    Paste Release for a 10 mil (.010) Circle

    Paste A SnPb Paste A Lead Free

    10 mil (.25 mm) Dia. Circle (Area Ratio = 0.64)

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    143/263

    Paste B SnPb Paste B Lead Free

    Low Area Ratio Solder Paste Release

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    144/263

    High Area Ratio Solder Paste Release

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    145/263

    Print to Pad Ratio Gasketing The ratio between the aperture width and pad

    should be at least 1:1.2

    Often called Aperture Reduction

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    146/263

    EXAMPLE: 20 MIL (.5mm) Pitch Component

    SMT PAD

    12 x 0.80 = 10 mil aperture

    10 MIL

    12 MIL

    STENCILOPENING

    SMT PAD

    STENCIL

    Aperture to Pad Alignment PCB Pads Over-etched

    Making them smaller than the size in the Gerber data.

    For boards that are over-etched, Good gasketing isensured by reducing the size of the aperture to the pad

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    147/263

    ensured by reducing the size of the aperture to the pad

    Printed Circuit Board Tolerance

    Machine Alignment Tolerance Stencil to PCB

    Even the most accurate printing equipment has an

    alignment tolerance

    Stencil Tolerance

    Stencil Design

    Land Pattern & Aperture Design for 2-sided components

    Land Pattern

    Y YA

    Aperture DesignC = L(max) + 0.030

    A = L(min) - 2 x T(max)

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    148/263

    C

    B

    Y Y

    X

    A

    D

    C

    B

    Y Y

    X

    A

    F

    Y L(max) and (min) arethe part lengthtolerances

    W(max) is the partwidth tolerance

    T(max) is the partthickness tolerance

    The Home Plate design for chipswas created to assist in reducing theeffect of Solderballing when usingNo-Clean solder pastes, when toomuch paste is applied and too muchsolder is trapped beneath the part.

    X = W(max) + 0.010

    Y = (C-A) / 2D = 0.75 * Y

    F = X - 0.002

    B = pad pitch

    Aperture Modifications (examples)

    Shapes

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    149/263

    XA

    YA YP

    XP

    XA

    YA YP

    XA

    YA YPSize

    Exceptions

    Poor Gasketing: Stencil Design

    The speed at which squeeze out accumulates

    is dependent on the width of aperture relativeto the pad Apertures reduced relative to the pad width will minimize

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    150/263

    p p

    squeeze out and prevent bridging.

    Reduced

    Not Reduced

    Gasketing (Sealing)

    The contact of the PWB and stencil form agasket or seal between the stencil aperture andthe printed circuit board component pad.

    If the gasket is broken solder shorts will occur

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    151/263

    If the gasket is broken, solder shorts will occur.

    Stencil

    Board

    PadsGasketSolder Mask

    Pitch Pad Width Aperture Stencil thick A.R.

    Pitch Pad Width Aperture Stencil thick A.R.

    Pad & Aperture Size Recommendations

    English Units

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    152/263

    .025 .015 .012 .006 2.0

    .020 .012 .009-.010 .005-.006 1.7

    .016 .010 .007-.008 .005 1.4

    .012 .008 .005-.006 .004-.005 1.2

    .025 .015 .012 .006 2.0

    .020 .012 .009-.010 .005-.006 1.7

    .016 .010 .007-.008 .005 1.4

    .012 .008 .005-.006 .004-.005 1.2

    Pad & Aperture Size Recommendations

    Metric Units

    Pitch Pad Width Aperture Stencil thick A.R.

    64 38 30 15 2 0

    Pitch Pad Width Aperture Stencil thick A.R.

    64 38 30 15 2 0

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    153/263

    .64 mm .38 mm .30 mm .15 mm 2.0

    .51 mm .30 mm .23-.25 mm .127-.15 mm 1.7

    .41 mm .25 mm .18-.20 mm .127 mm 1.4

    .30 mm .20 mm .127-.15 mm .1-.127 mm 1.2

    .64 mm .38 mm .30 mm .15 mm 2.0

    .51 mm .30 mm .23-.25 mm .127-.15 mm 1.7

    .41 mm .25 mm .18-.20 mm .127 mm 1.4

    .30 mm .20 mm .127-.15 mm .1-.127 mm 1.2

    Common Resistor Sizes, Land Patterns, and Stencil

    Openings (from IPC-SM-782) specifications)

    Stencils Passive Devices

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    154/263

    Board / Mask Problems

    Paste Bleed out

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    155/263

    Solder Mask over Pads

    Silkscreen, and labels can prop up the

    stencil and prevents good gasketingwhich causes bleed out.

    Board Legends Labels or legends can also cause gasket

    problems

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    156/263

    ComponentReference ID (ink)

    Legend, Trace andSilkscreen is too high

    Cookson Stencil Design Principles1. Keep aperture shape the same as pad shape, unless

    otherwise required (by volume or process requirements) Maximized board to stencil alignment repeatability

    2. Apply absolute aperture reduction relative to pad Maximized board to stencil alignment repeatability (2x -1 mil around)

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    157/263

    Maximized board to stencil alignment repeatability (2x 1 mil around)

    3. Center aperture on pad Maximized board to stencil alignment repeatability

    4. When maximizing volume, use squares over circles Maximizes volume (4/ greater volume then circles) while

    minimizing pitch issues

    5. Area Ratio is main factor for paste release (see FIG 1) Highest Area Ratios ( 0.66) provide Lowest Standard Deviation on

    Transfer Efficiency

    Cookson Stencil Design Principles

    6. Medium taper gives best transfer efficiency (smallest

    standard deviation) Taper of 0.8 0.2 mil provide Highest Transfer Efficiency with the

    Lowest Standard Deviation.

    7. Aperture Design Modifications are independent from stencil

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    158/263

    manufacturing technique Recommend thinner foil thickness (-5%) for ALPHA FORM stencilsdue to increased Transfer Efficiencies.

    8. Component Technology 20 mil pitch and or StencilThickness 4 mil use ALPHA FORM Electroforming

    Technology Highest volume deposits with lowest standard deviations measured

    under these circumstances with POS

    9. Use Custom Shapes for discrete components

    A 66% home plate design to increase process window by improvingcomponent alignment & outgassing, reduce squeeze balls &tombstoning effects.

    Cookson Stencil Design Principles10.Area Array type of packages require Square Apertures

    Maximizes volume (4/ greater volume then circles) while minimizingpitch issues Different rules apply for fine feature BGAs

    11.Solder Spreading Characteristics require different aperturedesign modifications

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    159/263

    design modifications No aperture reductions for Lead Free Alloys and Water Soluble

    Pastes: they dont spread to the edges of the pads and will leaveexposed pad finish

    12.Stencil Thickness & Use of Steps will be determined by the

    smallest aperture and the largest aperture Using the stencil thickness look-up tables based on pad sizes andAspect Ratio (1:1.5)

    13.Large apertures require support bars to prevent scooping,squeegee damage and voids.

    Apertures 150 mil in X and/or Y require support bar 20 mil in Xand/or Y.

    Cookson Stencil Design Principles

    14. Stepped areas required offset angle to prevent squeegee

    damage Steps should be rotated using a -5angle

    15. Frame less stencils should be considered Consistent tension provides improved positional accuracy and

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    160/263

    Consistent tension provides improved positional accuracy and

    reduced variation Stencil storage space reduction

    16. Aperture Orientation is a factor in stencil design 45Is neutral, however, altering 0or 90apertures would be below

    manufacturing tolerances and is therefore not significant

    17. Squeegees and enclosed print heads is not a factor instencil design

    No data (yet) to design specific design rules

    18. Reversed Taper only for experimental use No data (yet) to design specific design rules

    Common Stencil Types

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    161/263

    Electroplated Laser cut Chemical etched

    Stencil aperture definition will impact paste deposition volume and defect rate

    Stencil aperture (0.007 X 0.0875) at 10X

    Conventional Stencil Technology

    ManufacturingManufacturingManufacturingManufacturing

    ProcessesProcessesProcessesProcesses

    ConcernsConcernsConcernsConcerns MagnifiedMagnifiedMagnifiedMagnified

    imageimageimageimage

    Chemically etchedChemically etchedChemically etchedChemically etched Isotropic etching

    produces

    Tapered sidewalls

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    162/263

    limiting pitch

    Laser CutLaser CutLaser CutLaser Cut Sequential process

    Laser-metal

    Interaction hencerough aperture

    sidewalls

    ElectroformedElectroformedElectroformedElectroformed Aperture size and

    shape varies

    Stencil Release Performance

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    163/263

    ElectroFormed Paste D

    20 mil Aperture

    Laser Cut Paste D

    20 mil Aperture

    Evaluating

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    164/263

    Printed Circuit BoardDesigns

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    165/263

    Classification ofElectronic Assemblies

    ANSI/J-STD-001 classifies three levels ofelectronic assemblies based on end-item use.The 3 classifications were established to reflect

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    166/263

    differences in producibility, complexity,functional performance requirements andverification frequency. They are as follows:

    Class 1- General Electronic Products:Consumer products, computer and computer

    peripherals, and hardware suitable forapplications where the major requirement is afunction of the completed assembly

    (Source: Printed Circuits Handbook, pp 36.3, Coombs, ISBN: 0-07-012754-9)

    Classification ofElectronic Assemblies

    Class 2- Dedicated Service Electronic Products:Includes communication equipment, sophisticatedbusiness machines, and instruments where high

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    167/263

    performance and extended life are required, and forwhich uninterrupted service is desired but notcritical

    Class3- High Performance Electronic Products:Includes equipment for commercial and militaryproducts where continued performance or

    performance on demand is critical

    Standard Multi-Layer Interconnection

    PTH

    Blind Via

    Line

    BGAPGA

    3. DH Dp + 4 mils, Max DH 2.5Dp

    4. Max Pad D < 3 DH

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    168/263

    PTH Land

    Buried ViaBuried Line

    SMT PadPassive Discrete

    PTH Used as

    Interconnect

    1. 0.25-0.5 mm clearancepin to hole

    General Requirements

    PCB Should have good rigidity, minimalrouting.

    PCB should have minimal warpage.

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    169/263

    Fiducials located on Breakaways ofpanelized boards may decrease accuracy.

    If aperture is not reduced, bridging and needfor wiping will be increased.

    Printed Circuit Board Size

    Maximum printed circuit board size (length,width, and thickness) determined by theparticular process equipment being used.

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    170/263

    Minimum printed circuit board size (length,width, and thickness) determined by theparticular process equipment being used.

    Boards smaller than the minimum size maybe panelized (two or more individual circuits

    per panel).

    Printed Circuit Board Size

    One factor that must be considered is the printedcircuit board fabrication vendors material usagefrom a single process sheet. Significant savings

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    171/263

    can be obtained by increasing the number ofboards that can be fabricated from a singleprocess sheet.

    It is important to understand the printed circuitboard suppliers guidelines and preferences andadhere to them in designing the board. This is

    an excellent example of early supplierinvolvement.

    Printed Circuit Board Shape

    Rectangular shaped boards with no cut outsor breakaways are always preferred.

    When breakaways are necessary, there are

    i

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    172/263

    two common options;The Route and Tab Method

    The V Groove Method

    Component Spacing

    There is no limit on maximum interpackagespacing

    Land to land spacing between adjacent

    t h ld b 1 25 l

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    173/263

    components should be 1.25 mm clear spaceall around the edges of the printed board ifboards are tested off the connector or 2.5 mmminimum if vacuum seal for testing is used.

    Source: IPC-SM-782A, Section 3.6.1.1, pp 20

    Component Spacing

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    174/263

    Source: IPC-SM-782A, page 21

    Lead Protrusions

    For single sided PCB Assembly, lead or wireprotrusion must be a minimum of 0.5 mm forall classes

    F d bl id d d ltil PCB

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    175/263

    For double-sided and multilayer PCBAssembly, in all classes, the minimum leadprotrusion is that the lead end be visible in the

    solder The maximum lead protrusion for Class 1 is

    that there should be no danger of shorts

    Lead Protrusions

    For Class 2, the maximum lead protrusion is2.5 mm and for Class 3 the maximum leadprotrusion is 1.5 mm

    For boards thicker than 2 3 mm the lead

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    176/263

    For boards thicker than 2.3 mm, the leadprotrusions may not be visible

    Source: Printed Circuits Handbook, pp 36.27

    Edge Clearance Example

    No SMT components should be placed within0.150 (3.81 mm) from the edges of a board.

    No traces or planes should be routed within

    0 050 (1 27 mm) from the edge of a board

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    177/263

    0.050 (1.27 mm) from the edge of a board.

    No via holes should be placed within 0.100

    (2.54 mm) from the edge of a board. No test points (pads or via holes) should be

    placed within 0.125 (3.18 mm) from the edge

    of a board.

    Component Hole Size

    Suppliers will have recommended hole sizesfor specific components

    If a hole size is not recommended; use a hole

    that is 015 ( 38 mm) larger than maximum

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    178/263

    that is .015 (.38 mm) larger than maximumlead diameter (round lead) or lead diagonal(square or rectangular lead).

    If the component is being automaticallyinserted, use the hole size recommended by

    the insertion equipment supplier.

    Tooling Holes

    Required for location and fixturing of theboards during the fabrication, assembly andtest processes.

    Requirements must be specified on a board

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    179/263

    Requirements must be specified on a boardoutline drawing.

    Specific quantity, size, location, clearance,etc. will be determined by theManufacturing/Process Engineer and

    specified in the printed circuit board designguidelines

    Tooling HolesRequirement Example

    Quantity 4

    Size (diameter) 0.159 +0.002/ - 0.001

    Location 4 corners

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    180/263

    Location 4 corners Plating Non plated

    Clearance (diameter) 0.25 from edge of hole

    Datum lower left corner hole

    Fiducial Marks

    Used by all automatic process equipment toprecisely locate each printed circuit board.

    Two types of fiducial marks are used;

    Board Level

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    181/263

    Board LevelComponent Level

    Board level are used on every board to adjust the

    location of the stencil in the printer and to modifyprograms in the other process equipment.

    Component level are used on boards with complex

    components for very precise alignment. Exact shape and location determined by process

    Board Level Fiducial Marks Example

    Quantity: 3 (minimum) Location: Corners of the board

    Size: .040 (1 mm) diameterpad

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    182/263

    pad

    Clearance: .120 (3 mm) diameter

    (no soldermask, traces,via holes, andlegend/silk-screening)

    Edge Distance: .250 (6.35 mm) minimum

    Board Level Fiducial Marks

    A test board displaying a variety of fiducial mark

    geometries that can be used for stencil to boardalignment

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    183/263

    Courtesy or Speedline Technologies

    Component Level Fiducial Marks Example

    Component Local Fiducial RequiredBGA No

    .025 (.65 mm) pitch or greater No

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    184/263

    .025 (.65 mm) pitch or greater No

    .020 (.5 mm) pitch less than 120 pins No

    .020 (.5 mm) pitch more than 120 pins Yes

    Less than .020 (.5 mm) pitch Yes

    Component Selection

    Always use existing components if possibleReduce component variety

    Reduce component cost

    Reduce material storage and handling

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    185/263

    Reduce material storage and handling

    Reduce feeder requirements

    Minimize required feeder carriage space

    Purchase larger component reels

    Component Selection

    Maximize use of SMT components (ABCCosting)

    Minimize use of manually inserted components

    Consider through hole connectors if the Pin in

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    186/263

    Consider through hole connectors if the Pin inPaste Process is used

    Use quality and cycle time data to influencecomponent selection on new products

    Understand the impact on the process of new

    components prior to approving for design

    Activity Based Costing Calculates the total cost of the assembly operation

    Equipment

    People

    Overhead (lights, heat, etc.)

    Calculates number of components to be inserted

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    187/263

    Calculates number of components to be inserted

    Divides the total cost by the total components todetermine the cost to assemble a component

    Automatically inserted components will have a muchlower cost than manually inserted components

    Cost of assembly + material = product cost

    Some operations consider the cost of test

    Slow Secondary Operations

    Avoid components that require slowsecondary operations that are longer than thecycle time of the SMT manufacturing process

    and/or cannot be done in the in line process.

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    188/263

    and/or cannot be done in the in line process.Undefill

    Incapsulant

    Hand soldering

    Wire bonding

    Flip Chip, Chip on Board (COB), some ChipScale Packages (CSP), TAB

    Passive Use Growth

    A billion hours ago the stone age was thefuture

    A billion minutes ago Caesar ruled Rome

    A billion passives ago was this morning!

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    189/263

    A billion passives ago was this morning!

    Every year enough are produced to give each

    man, woman and child on the planet 160passives

    Size of 01005 Component

    01005 Package Size = 10 mil (.010) X 5 mil (.005)

    Or

    0.25 mm X 0.125 mm

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    190/263

    Their width (5 mils) is only slightlylarger than the thickness of a humanhair and their length about thethickness of a sheet of resume paper!

    0603

    0402

    Imperial/Metric Component Sizes

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    191/263

    0201 01005

    Chip Component Size& Spacing Comparisons

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    192/263

    Houston et al; Implementation of 01005s: a Case Study; SMTAI-08

    Chip Size and Spacing Options

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    193/263

    Chen, et al.; ASSEMBLY PROCESS RESEARCH ON 01005 CHIP COMPONENTS IN LEAD-FREE SYSTEM; SMTAI-06

    Flip Chip

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    194/263

    Chip on Board (COB)

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    195/263

    FC = SMT Process

    Print Underfillor Dip Apply

    Underfill

    Print SolderPaste for SMT

    Assembly BGA

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    196/263

    SimultaneousSolder Interconnect Reflow and

    Underfill Cure

    Chip

    BGA

    Bare Chip Placement piercing

    underfill to form partial fillets

    Chip

    The Printed Circuit Design Guidelines must specifythe requirements for the placement of allcomponents used (refer to PCB Design Guidelinesfor exact values).

    Board side

    Component Placement

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    197/263

    Soldering process to be used

    Spacing between components for reflow soldering

    Spacing between components for wave soldering

    Spacing between components and test points

    Direction of travel through wave solder process

    Size and location of solder thief pads for wave soldering

    Component Footprints and Pads

    A library of component foot prints and pads isusually specified in the Printed Circuit Board DesignGuidelines and maintained in the CAD System usedto design the boards.

    There is an IPC Printed Circuit Board Design

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    198/263

    gSpecification (IPC781) that details componentfootprints and pad sizes.

    Reduce aperture size by 20% to your pad size,maintain a minimum of 1.5 aspect ratio of aperturewidth to stencil thickness. (.025/.64 mm pitch andbelow).

    Wave Soldering

    Printed Circuit Board Design

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    199/263

    Portions

    Board Design Considerationsfor Wave Soldering

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    200/263

    Board Design Considerationsfor Wave Soldering

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    201/263

    Board Design Considerationsfor Wave Soldering

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    202/263

    Board Design Considerationsfor Wave Soldering

    Preferred

  • 7/30/2019 smta-gdl_smta-gdl_DFM_presentation_2012-07

    203/263

    Not Preferred

    Board Design Considerationsfor Wave Soldering

  • 7/30/