Upload
emery-hopkins
View
220
Download
1
Embed Size (px)
Citation preview
SOC Consortium Course Material
On Chip BusOn Chip Bus
Speaker: 沈文中
National Taiwan University
Adopted from National Taiwan University
SOC Course Material
2SOC Consortium Course Material
Outline
AMBA Bus– Advanced System Bus– Advanced High-performance Bus– Advanced Peripheral Bus
IP Design flowFPGA design flow
3SOC Consortium Course Material
Bus Architecture
4SOC Consortium Course Material
Outline
AMBA Bus– Advanced System Bus
• High performance• Pipelined operation• Multiple bus master
– Advanced High-performance Bus– Advanced Peripheral Bus
IP Design flowFPGA design flow
5SOC Consortium Course Material
ASB characters
Negative edge triggerTri-state bus
– Drawback: More effort used to control timing– Advantage: cost less area
6SOC Consortium Course Material
Outline
AMBA Bus– Advanced System Bus– Advanced High-performance Bus
• High performance• Pipelined operation• Multiple bus master• Burst transfers• Split transactions
– Advanced Peripheral Bus
IP Design flowFPGA design flow
7SOC Consortium Course Material
AHB simple Arch.
8SOC Consortium Course Material
AHB Components
AHB Components– AHB master is able to initiate read and write operations
by providing an address and control information. Only one bus master is allowed to actively use the bus at any one time.(max. 16)
– AHB slave responds to a read or write operation within a given address-space range. The bus slave signals back to the active master the success, failure or waiting of the data transfer.
9SOC Consortium Course Material
AHB Components(ii)
AHB Components– AHB arbiter ensures that only one bus master at a time
is allowed to initiate data transfers. – AHB decoder is used to decode the address of each
transfer and provide a select signal for the slave that is involved in the transfer. A single centralized decoder is required in all AHB implementations.
10SOC Consortium Course Material
AHB Signals(i)
AHB Signals can be classified as– Clock (HCLK)– Address and read/write data (HADDR, HRDATA,
HWDATA)– Arbitration (HGRANTx, HMASTER, HMASTLOCK,…)– Control signal (HRESETn,…)– Response signal(HREADY, HRESP)
11SOC Consortium Course Material
AHB Signals(ii)
Transfer signals– HCLK
• bus clock. All signal timings are related to the rising edge.
– HADDR[31:0]• 32 bits system bus
– HWDATA/HRDATA [31:0]• 32 bits write/read data bus
– HWRITE• High: write data
• Low: read data
– HREADY• Transfer done
12SOC Consortium Course Material
AHB Signals(ii)Basic Transfer
Each transfer consists of– An address and control cycle– One or more cycles for the data
13SOC Consortium Course Material
AHB Arch.
14SOC Consortium Course Material
AHB Signals(iii)
Control signals– HTRANS[1:0]
• Current transfer type
– HBURST[2:0]• When sequential transfer, control transfer relation
– HSIZE[2:0]• Control transfer size=2^HSIZE bytes(max=1024bits)
– HPROT[3:0]• Protection data
15SOC Consortium Course Material
AHB Signals(iii)-HTRANS
HTRANS[1:0]– IDLE: master don’t need data to be transfered– BUSY: allows bus masters to insert IDLE cycles in the
middle of bursts of transfers.– NONSEQ: The address and control signals are unrelated
to the previous transfer.– SEQ: the address is related to the previous transfer.
16SOC Consortium Course Material
AHB Signals(iii)-HBURST
17SOC Consortium Course Material
AHB Signals(iii)-HBURST
18SOC Consortium Course Material
AHB Signals(iv)
Response signals– HREADY
• Transfer done, ready for next transfer
– HRESP[1:0]• OKAY transfer complete• ERROR transfer failure(ex: write ROM)• RETRY higher priority master can access bus• SPLIT other master can access bus
19SOC Consortium Course Material
AHB Signals(v)
Arbiter signals– HGRANTx
• Select active bus master
– HMASTER[3:0]• Multiplex signals that sent from master to slave
– HMASTLOCK• Locked sequence
20SOC Consortium Course Material
Master signal
21SOC Consortium Course Material
Arbiter signal
22SOC Consortium Course Material
Slave signal
23SOC Consortium Course Material
Outline
AMBA Bus– Advanced System Bus– Advanced High-performance Bus– Advanced Peripheral Bus
• Low power• Latched address and control• Simple interface• Suitable for many peripherals
IP Design flowFPGA design flow
24SOC Consortium Course Material
APB state diagram
25SOC Consortium Course Material
APB signals
APB character – Always two cycle transfer– No wait cycle and response signal
APB signals– PCLK Bus clock , rising edge is used to time all
transfers.– PRESETn APB reset 。 active Low.
26SOC Consortium Course Material
APB signals
PADDR[31:0] APB address bus.PSELx Indicates that the slave device is selected.
There is a PSELx signal for each slave.PENABLE Indicates the second cycle of an APB
transfer.PWRITE Transfer direction. High for write access,
Low for read access.PRDATA Read data busPWDATA Write data bus
27SOC Consortium Course Material
Outline
AMBA Bus– Advanced System Bus– Advanced High-performance Bus– Advanced Peripheral Bus
IP Design flow– Memory definition– IP design-SW– IP design-HW
FPGA design flow
28SOC Consortium Course Material
Memory definition
•Self-designed IP can be located in the Bus error response area
•Defined in AHBDecoder.v
29SOC Consortium Course Material
AMBA IP design (1/4)
Add an IP (MYIP) into the system which includes– a ZBT SSRAM controller– an AHB to APB bridge– an APB register peripheral– an APB interrupt controller– an address decoder
Slave #1
Slave #2 Logic Module
MYIPSlave #3
AHB APB
30SOC Consortium Course Material
AMBA IP design (2/4)
Supplied HDL file– AHBAHBTop.v– AHBDecoder.v– AHBMuxS2M.v– AHBZBTRAM.v– AHB2APB.v– AHBAPBSys.v– APBIntCon.v– APBRegs.v
Slave #2
Slave #1
Slave #3
31SOC Consortium Course Material
AMBA IP design (3/4)
Bus Interconnection
HSELHADDRHWDATA
HRDATA
HSELHADDRHWDATA
HRDATA
HSELHADDRHWDATA
HRDATA
Decoder
HADDR
HWDATA
HRDATA
Slave #1
Slave #2
Slave #3
Logic Module
Mux
HADDR
HWDATA
HRDATA
Master #1
Master #2HADDR
HWDATA
HRDATA
Arbiter
Mux
Mux
32SOC Consortium Course Material
AMBA IP design (4/4)
Software part– Write a function to control hardware– Delay number of clocks by NOOP (asm) instruction
Hardware part– Design your own IP module MYIP.v– Change AHBDecoder.v– Change AHBMuxS2M.v– Change AHBAHBTop.v to include MYIP into top module
33SOC Consortium Course Material
IP design-HW (1/4)
Design your own IP module MYIP.v– Write your own module MYIP.v with AMBA AHB Slave
interface
MYIP.v
HSEL
HADDRHWDATA
HRDATA
HCKLHRESETn
HREADYInHTRANS
HSIZEHWRITE
HREADYOutHRESP
MYIP circuit
AHB Slave Interface
READ WRITE
IDLE
34SOC Consortium Course Material
IP design-HW (2/4)
Change AHBDecoder.v– Add HSELMYIP signal to select MYIP to response– Address are defined in decoder
HSELHADDRHWDATA
HRDATA
HSELHADDRHWDATA
HRDATA
HSELHADDRHWDATA
HRDATA
Decoder
HADDR to all slaves
Slave #1
Slave #2
MYIP
Logic Module
HADDRHWDATA
HRDATA
Master #1
Master #2HADDR
HWDATA
HRDATA
MuxHADDR_M1[31:0]
HADDR_M2[31:0]
HSEL_S1HSEL_S2HSELMYIP
Address and control mux
35SOC Consortium Course Material
IP design-HW (3/4)
Change AHBMuxS2M.v– Use Mux to select slave which can use HRDATA
HSELHADDRHWDATA
HRDATA
HSELHADDRHWDATA
HRDATA
HSELHADDRHWDATA
HRDATA
Decoder
HRDATA
Slave #1
Slave #2
MYIP
Logic Module
Mux
MasterHADDR
HWDATA
HRDATA
36SOC Consortium Course Material
IP design-HW (4/4)
Change AHBAHBTop.v– Add your module in AMBA bus– Connect the above net connection
HSELHADDRHWDATA
HRDATA
HSELHADDRHWDATA
HRDATA
HSELHADDRHWDATA
HRDATA
Decoder
HADDR
HWDATA
HRDATA
Slave #1
Slave #2
MYIP
Logic Module
Mux
37SOC Consortium Course Material
Architecture
AHBDecoder AHBMuxS2M
AHBZBTRAM MYIP
ZBTSRAM
AHBAHBTop
AHB2APB
sel
APBIntCon
APBregs
AHBAPBsys
addr
38SOC Consortium Course Material
Files Description of Example
Hardware files .\Lab6\Codes\HW\Verilog\– AHBAHBTop.v– AHBDecoder.v– AHBMuxS2M.v– AHBZBTRAM.v– AHB2APB.v– AHBAPBSys.v– APBIntCon.v– APBRegs.v– MYIP.v
Software program files .\Lab6\Codes\SW\– sw.mcp– register.c – platform.h– rw_support.s
For FPGA synthesis tool to generate bitstream
For CodeWarrior to generate sw.axf
39SOC Consortium Course Material
Hardware file MYIP.v
MYIP.v– A simple IP template with 8 32-bit registers wrapped with
simple AHB slave interface– This file is modified from AHBZBTRAM.v
HSEL
HADDRHWDATA
HRDATA
HCKLHRESETn
HREADYInHTRANS
HSIZEHWRITE
HREADYOutHRESP
MYIP circuit
AHB Slave Interface
READ WRITE
IDLE
40SOC Consortium Course Material
Outline
AMBA Bus– Advanced System Bus– Advanced High-performance Bus– Advanced Peripheral Bus
IP Design flow FPGA design flow
– Compile flow & Download flow (Xilinx)– Compile flow & Download flow (Altera)
41SOC Consortium Course Material
Compile flow (1/2) (Xilinx)
All Verilog module must be synthesized by Xilinx Software
42SOC Consortium Course Material
Compile flow (2/2) (Xilinx)
Add register.ucf (define the pin assignment) into project
Double click generate programming file to generate *.bit (which can be downloaded into FPGA)
43SOC Consortium Course Material
Download flow (Xilinx)
Connect config link Connect Multi-ICE to Logic ModulePower onUse progcards.exe to download register.bit fileRemove config linkPower off
44SOC Consortium Course Material
Outline
AMBA Bus– Advanced System Bus– Advanced High-performance Bus– Advanced Peripheral Bus
IP Design flow FPGA design flow
– Compile flow & Download flow (Xilinx)– Compile flow & Download flow (Altera)
45SOC Consortium Course Material
Compile flow (1/2) (Altera)
All Verilog module must be synthesized by Altera Software (Quartus II)
46SOC Consortium Course Material
Compile flow (2/2) (Altera)
Modify Pinout.csf into ahbahbtop.csf to define the pin assignment
Push the Compile bottom to generate *.rbf (which can be downloaded into FPGA)
47SOC Consortium Course Material
Download flow (Altera)
Use the text-editor to produce a .brd file (configuration file for progcards.exe)
Power offConnect Multi-ICE to Logic ModuleSet the LM in Config ModePower onAuto-config again in the MultiICE Server programUse progcards.exe to download bitstream