Software Defined SiliconSoftware Defined Silicon

晶片功能的軟體化

Presented ByPresented By

謝啟東謝啟東 五子五 五子五 (1979)(1979)MSCSMSCS ，， Vanderbilt (1985)Vanderbilt (1985)副總，銳力科技副總，銳力科技

黃模淼黃模淼 五子五 五子五 (1979)(1979)MSEEMSEE ，交大光電，交大光電副總，銳力科技副總，銳力科技

OverviewOverview 30 min30 min Software Defined SiliconSoftware Defined Silicon 50 min50 min BreakBreak 5 min 5 min DemoDemo 20 min20 min Q & AQ & A 10 min10 min

OverviewOverview

Buy a ProductBuy a Product

CheaperCheaper

Easy to Use (User-Friendly)Easy to Use (User-Friendly)

BestBest

Product Development Steps

Product Spec / Features

System Spec

Hardware Spec Mechanical Spec Software Spec

Development DevelopmentDevelopment

System Integration

Product Product Spec / FunctionsSpec / Functions

Time Time CostCostPricePrice

Time to the MarketTime to the Market BOM CostBOM Cost

積體電路的變革Tube

Transistor

SSI

MSI

LSI

VLSI ASIC

Programmable IC ASSP

Shorter Development Time & Cheaper BOM Shorter Development Time & Cheaper BOM

Volume MarketVolume Market Niche MarketNiche Market

Product MarketProduct Market

Big VolumeCompetitive & Bloody

Small VolumeLess Competitive

ASICASSP

Standard Solution

Glue LogicProgrammable DevicesNon-Standard Solutions

To Design a Product ?To Design a Product ?

Glue LogicGlue LogicASIC / ASSPASIC / ASSPProgrammable ICsProgrammable ICsModules Modules Solution Boards…Solution Boards…

By HardwareBy HardwareBy SoftwareBy Software

Time to the Market BOM Cost

ASIC / ASSPASIC / ASSP FPGA / CPLDFPGA / CPLD

CheaperEasier

Specific

ExpensiveComplicate

Flexible

By HardwareBy Hardware By Software By Software

ExpensiveBetter Performance

CheaperPerformance?

ASIC / ASSP

Application Specific IC

Designed to Perform the Specific Function Designed to Perform the Specific Function

VGA ChipsVGA Chips Keyboard ControllerKeyboard Controller Mouse ICMouse IC

Wi-Fi ChipsWi-Fi ChipsDVD ChipsDVD Chips 3G Chips3G Chips

Its Specific Function Its Specific Function cannot cannot be Changed or Programmedbe Changed or Programmed

Programmable ICsProgrammable ICs

PAL / GALPAL / GAL Programmable Array LogicProgrammable Array LogicGate-BasedGate-Based

xROMxROM x Read-Only Memoryx Read-Only MemoryHard-WiredHard-Wired

CPLD CPLD Complex Programmable Logic DeviceComplex Programmable Logic Device

FPGA FPGA Field-Programmable Gate ArrayField-Programmable Gate ArrayFunctional BlockFunctional Block

uCuC Micro-ControllerMicro-ControllerCPU-BasedCPU-Based

Programmed for Functions : FlexibleProgrammed for Functions : Flexible

Programming a DeviceProgramming a Devicefor a Functionfor a Function

PAL / GALPAL / GAL Boolean Equation by PAL Programmer

ROMROM Programmer

CPLDCPLD JTAG Port (Joint Test Action Group)Proprietary In-Circuit Programmer

FPGA FPGA JTAG Port by Proprietary In-CircuitProgrammer + Proprietary Languages

uCuC Programmer + Languages

Example : KeyboardExample : Keyboard

What Kind of Keyboard?

Notebook PCKeyboard

Key Pad Few Keys Only

ASIC Keyboard IC

uC + GPIO Glue Logic

Medical Lab

Auto Feeding System&

Monitoring System

Non-Standard Product

Special Design

uC + Glue Logic

Manufacture

Product’s Testing Tool

Non-Standard Tool

Special design

PC + Glue Logic +IO Controller Cards

Any SiliconAny Silicon

Which Its Function Can BeWhich Its Function Can Be

Easily and Flexibly Easily and Flexibly

Defined byDefined by

CPU-Based CPU-Based

High-Level Languages High-Level Languages

Software Defined SiliconSoftware Defined Silicon

Programmed by High-Level LanguageProgrammed by High-Level Language

Flexibly Define a SiliconFlexibly Define a Silicon’’s Functions Function

SSoftware oftware

DDefined efined

SSiliconilicon

What’s SDS?What’s SDS?

Processor

Processor

Processor

Program Code

Why SDS?Why SDS?

Fast tune-cycles and market change“Scale” grows up exponentially

“Loading” & “risk” rises up

The Fact…

Processor…

Powerful

ReliableEconomic

How do you differentiate ?

What SDS should be?What SDS should be?

Direct & programmable I/O access

Programmable timing control

Independent & wide processing path

Inter-connection channel

Highly responsive processing

Reliable & convenient development tool

Is It Possible ??Is It Possible ??

Yes, Here is an example…Yes, Here is an example…

400MHz RISC Processor

8 threads per core

64K SRAM8K OTP

Up to 64 I/O pins

The advanced I/OThe advanced I/OTimed Output

Time-Stamped Input

PredicatedInput

Clocked Port with Data ready

Dedicated serialisationhardware

I/O Ports are tightly coupled to the core

Dedicated instructions for I/O port assignment

Has the concept of timing and may be synchronized to an internal reference clock or an external input clock

For “Timing”For “Timing”

In each core, Ten 100MHz timer public resource are available for any thread. (10 ns resolution)

“Timer” may link up with any event on I/O port and inter-communication channel.

Flexible “Processing Path”“Processing Path”

Eight independent threads in one core

Dedicated instruction for thread job assignment

Proprietary compiler to ensure 50 ~ 100 MIPS on each thread

Xlink switch are available for each thread to enable threads be parallel and/or serial chained processing

Highly Responsive

Xlink Switch for inter-connectionXlink Switch for inter-connection

Use “chan” to connect two “chanend”

“chanend” threads may be on same core, different core or different chip.

Accessible both online or on your desktopmachine using downloadable tools

Software design and debug flow is similar to other embedded tool chains – Focus on C/C++

Adds language support to simplify tasksrelating to concurrency and real-time control – XC

Complete set of tools from design capture toadvanced debugging

A lot of design template are available for reference

Design FlowDesign Flow

Communication

XC looks and feels like C

Support for :

I/O with timing

Event

What’s XCWhat’s XC

Multiple threads and cores

System job partition

Using threads as building blocks

The new concept for engineersThe new concept for engineers

Thread may be “Software task”, “Timing I/O”, “Data processing”, “State machine”

Example: Partitioning a UART

SDS usage Scenarios

Intelligent Bridge

I/O expansion or companion chip

SDS based ASSP

A workable example -- Real-time Audio Filter with Ethernet AV input

DemoDemo

Designing with SDS - 1

Toggle an LED and write a UART transmit function in XC:

Focus on:• ports

• timers

Designing with SDS – 1 (Cont.)

Step1 : Define BAUD_RATE & BIT_TIME

Step2 : Declare output ports for LED & TxD

Step3 : Use one Timer in main() routine to flash LED& send message to UART Txd port periodically

Step4 : Use another Timer resource on transmit() routine to control bit timing on UART port

Demo System

Summary :

SDS is possible indeed.

Using threads as building blocks of system

Pending issue

Is it possible to achieve Gbit/sec?How compiler work ?

Other ?

Competitive ?

Q & AQ & A

Thanks YouThanks You