J o u r n a l o f Electronic Mate r i a l s , Vol. 24, N o . 1, 1995 RegularIssuePaper
Solder Joint Reliability of Indium-Alloy Interconnection
KOZO SHIMIZU, TERU NAKANISHI, KAZUAKI KARASAWA,K A O R U HASHIMOTO, and K O I C H I NIWA
F u j i t s u Laboratories Ltd., 10-1 Morinosato-Wakamiya, A t s u g i 243-01, J a p a n
Recent high-density very l a r g e scale integrated (VLSI) interconnections inmultichip modules require high-reliability solder interconnection to enable us toachieve s m a l l interconnect sizea n d l a r g e n u m b e rofi n p u t / o u t p u t terminals, andto minimize soft errors in VLSIs induced by a-particle emission from solder.Lead-free solders such as i n d i u m (In)-alloy solders are a possible alternative toconventional lead-tin (Pb-Sn) solders. T o realize reliable interconnections u s i n gIn-alloy solders, fatigue behavior, finite element m e t h o d( F E M ) simulations, anddissolution and reaction between solder and metallization were s t u d i e d withflip-chip interconnection models. We measured the fatigue life of solder jo in t sand the mechanical properties of solders, and compared the r e s u l t s with acomputer simulation b a s e d on the FEM. Indium-alloy solders have b e t t e rmechanical properties for solder j o i n t s , and t h e i r flip-chip interconnectionmodels showed a l o n g e r fatigue life than t h a t of P b - S n solder in t h e r m a l shockt e s t s between l i q u i d nitrogen and room temperatures. The fatigue characteris-tics obtained by experiment agree with t h a t g i v e nby FEM analysis. Dissolutiont e s t s show t h a t P t film is r e s i s t a n t to dissolution into In solder, indicating thatPt is a n adequate b a r r i e rl a y e r material for In solder. This test also s h o w s thatAu dissolution into the I n - S n solder raises its m e l t i n g p o i n t ; however, Agaddition to I n - S n solder prevents m e l t i n gp o i n t r ise. Experimental r e s u l t s showt h a t In-alloy solders are suitable for fabricating reliable interconnections.
K e y w o r d s : Fatigue, flip-chip, In alloys, interconnection, solder
I N T R O D U C T I O NI n d i u m (In)-alloy solders, such as i n d i u m - t i n (In-
Sn) 1,2 and indium-lead (In-Pb)3,4 solders, are a pos-sible alternative to conventional lead-tin (Pb-Sn) sol-ders because they are reliable and have a relativelywide m e l t i n gp o i n t range. Step-soldering required forhigh-density packaging ofmultichip modules (MCMs)uses a n u m b e r of solders with m e l t i n gp o i n t s t h r o u g ha wide range. Lead-free solders such as In-alloy sol-ders are expected to decrease environmental pollu-tion and soft errors in very l a r g e scale integrated(VLSI) interconnections induced by a-particle emis-sion from the solder, because Pb generally containsimpurities such as U and T h element w h i c hrelease a -particle.~ Solder fatigue is caused by stress induced by
(Received March 25, 1994;revised September 16, 1994)
t h e r m a l expansion mismatch between LSI chip/com-p o n e n t and substrate d u r i n g t h e r m a l cycling. T oo b t a i n h i g h e r solder j o i n t reliability, solders must beable to w i t h s t a n d fatigue. The reliability decreaseswith the solder j o i n t s ize .6,7
Previously, the flip-chip interconnection technologyfor Si and GaAs chips operated in l i q u i dn i t r o g e ns wass t u d i e d because carr ier mobility in complementarymetal-oxide semiconductor9 and high electron mobil-ity t r a n s i s t o r1,11 devices becomes h i g h e r t h a n that a troom temperature. This s t u d ys shows that In solder issuitable for flip-chip interconnections subjected to al i q u i d nitrogen environment. Thermal shock t e s t sbetween l i q u i d nitrogen and room temperatures ex-h i b i t t h a t In solder has a longer fatigue life than Pb-Sn solder. The reliability of flip-chip interconnectionsis also affected by the m e t a l used for the b o n d i n gpads.Metallization materials must have good compatibil-
40 Shimizu, Nakanishi, Karasawa, Hashimoto, and Niwa
Chip: Si, GaAs
Fig. 1. Close-up view of flip-chip interconnection model. This modelconsists of a GaAs chip and alumina substrate.
A !iiiiiiiiiiii i!!i!i i! iii i!I iiiiiiii!i!iiiiiiiii !iiiiiiiiiiii!;a ; rai iiiiiii:Jiiii:i!i!!!iii':i s
Solder bump bump
bFig. 2.The three-dimensional FEMmodel for interconnection: (a) thethree-dimensional FEMmodel (1/4 Mpartion model), and(b) the three-dimensional FEM model (single bump model).
ity with solders, i.e. good wettability and m i n i m a lchemical reaction. If the m e t a l s dissolve into thesolder, intermetallic compounds may form and soldercharacteristics such as m e l t i n g p o i n t may change.Dissolution and reaction characteristics between thesolder and metallization materials are i m p o r t a n tfactors to o b t a i n reliable interconnections.
In this paper, the reliability of flip-chip i n t e r -connections u s i n g In solder was s t u d i e d inclusive of al i q u i d n i t r o g e n environment. T h e r m a l fatigue life
was analyzed on the b a s i s of mechanical properties ofI n solder, elongation, and tensile strength. T o predictt h e r m a l fatigue characteristics of flip-chip solderj o i n t s , simulations were performed on the mechanicaldeformation behavior of In and P b - S n solderjo in t s bym e a s u r i n g stress-strain curves for each solder andcalculating plastic s t r a i n and Von Mises' equivalentstress by the finite element m e t h o d (FEM). Plastics t r a i n and Mises' equivalent stress are closely relatedto the t h e r m a l fatigue life of solderj o i n t s .
T o clarify the reaction between In-alloy solder andAu metallization, change in m e l t i n g p o i n t of I n - S nsolder with Au dissolution was examined. Silver addi-tion to I n - S n solder was t r i e d to p r e v e n tm e l t i n gp o i n trise with Au dissolution, because the m e l t i n g p o i n tincrease with Au dissolution in this experiment.
Fatigue Life of Solder J o i n t
Four different solder alloys were examined: In, In-48%Sn, In-40%Pb, and Sn-37%Pb. U s i n g v a p o r depo-s i t i o n technique, solder b u m p s were formed on both Siand GaAs model chips and a l u m i n a substrates too b t a i n high solderability. The alloy composition of thesolder b u m p s was controlled by correcting the compo-s i t i o n of the m o t h e r alloy m e l t e d in a crucible becausethe v a p o r pressure is different b e t w e e nthe elementalmetals. TM
The flip-chip interconnection s a m p l e we made iss h o w n in Fig. 1. The bump diameter was 200 ~m, thep i t c h was 400 pm, and the bump h e i g h t was 130 pm.The metallization film for the b o n d i n g pads was goldover p l a t i n u m with a t i t a n i u m underlayer (Au/Pt/Ti)both on the Si, GaAs/alumina, and b u m p s are electri-cally interconnected in series.
For the t h e r m a l shock t e s t , the flip-chip i n t e r -connection sample was immersed in l i q u i d n i t r o g e nfor 30 s, then exposed to n i t r o g e n gas a t room tem-p e r a t u r e (20) for 30 s, then a g a i n immersed intol i q u i d nitrogen. The electrical resistance was mea-s u r e d a t room temperature (20C). If a crack occursand propagates in the solder b u m p , the electricalresistance increases. 13 T o m e a s u r e the resistance, afour-point probe m e t h o d was u s e d .
Tensile TestU s i n g I n s t r o n universal tester, tensile t e s t s were
done a t -196 (liquid n i t r o g e n temperature), -70, 20,and 125C. Tes t pieces were cas t with same coolingrate as the solder reflow process (lC/s). The cross-head speed was 0.5 m m / m i n . This is approximatelythe same s t r a i n rate t h a t will occur in solder jo in t sd u r i n g t h e r m a l cycle t e s t s .14
SimulationFor the simulation, the three-dimensional solid
models s h o w n in Fig. 2 were u s e d . Since the sizedifference between the flip-chip bump and LSI (Sichip) or substrate is large, the plastic s t r a i n andMises' equivalent stress were calculated by two-step
SolderJ o i n tReliability of In-Alloy Interconnection 41
analysis. We examined the bump located farthestfrom the n e u t r a l p o i n t . This bump is significantlyaffected by the t h e r m a l expansion mismatch betweenthe chip and the substrate. Here , the chip is Si and thesubstrate is alumina. U s i n g A B A Q U S15 FEM pro-g r a m , we calculated the elasto-plastic t h e r m a l stresswith the temperature dependency of the solder's me-chanical properties.
Dissolution in In SolderDissolution of m e t a l s into the In solder was ex-
a m i n e d by reflowing solder on a t h i n film of eachmetal, ofw h i c h measuring m e t h o d is s h o w n in previ-ous s t u d y .TM Two t y p e s of two-layer metallization filmwere studied: gold over nickel (Au/Ni) and gold overp l a t i n u m (Au/Pt). The film samples were 1000A thick.Metallization p a t t e r n s (3 x 3 mm) were vapor-depos-ited on glass substrates (10 x 20 x 1 mm). An In solders h e e t (3 x 3 x 2 mm) was placed on each film p a t t e r n ,then was m e l t e d with a m i l d l y activated r o s i n flux byh e a t i n g a t 220C for 720 s. U s i n g flip-chip i n t e r -connection samples with metallization f i l m s ofA u / N i /T i and Au/Pt/Ti, the difference between t h e s e filmswas also examined by analyzing the element (Pt, Ni)distribution in the solder b u m p .
Dissolution in I n - S n S o l d e r
Both Au(0. 1 pm)/Ni(2 ~m) thin Au films and Au(2~m)/Ni(2 ~m) t h i c k Au f i l m s were examined. Thesefilms were electroplated on phosphor bronze p i n s . T odissolve the fil