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– 1 – Advanced Analog IC Design Professor Y. Chiu EECT 7326 Fall 2013 SPICE Simulation of Generalized Return Ratio (GRR) vs. Loop Gain (LG)

SPICE Simulation of Generalized Return Ratio (GRR ) vs. Loop Gain (LG)

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SPICE Simulation of Generalized Return Ratio (GRR ) vs. Loop Gain (LG). Trans-Impedance Amplifier (TIA). I C1 = 1 mA R C = 10 k Ω R F = 20 k Ω β = 200 V A = 1000 V R μ = 1 M Ω C π = 0.3 pF C μ = 100 fF C CS = 100 pF. GRR Simulation w/ Output Break Point. RR V. RR I. - PowerPoint PPT Presentation

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Page 1: SPICE  Simulation of Generalized Return Ratio  (GRR ) vs. Loop Gain (LG)

– 1 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

SPICE Simulation ofGeneralized Return Ratio (GRR)

vs. Loop Gain (LG)

Page 2: SPICE  Simulation of Generalized Return Ratio  (GRR ) vs. Loop Gain (LG)

Trans-Impedance Amplifier (TIA)

– 2 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

VO

Q1

RF

RC

Iin

IC1 = 1 mA

RC = 10 kΩ

RF = 20 kΩ

β = 200

VA = 1000 V

Rμ = 1 MΩ

Cπ = 0.3 pF

Cμ = 100 fF

CCS = 100 pF

Page 3: SPICE  Simulation of Generalized Return Ratio  (GRR ) vs. Loop Gain (LG)

GRR Simulation w/ Output Break Point

– 3 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

RRV RRI

Vr VO

Q1

RF

RC

L

C

Vt

Q1

RF

RC

L

Ir

It

Page 4: SPICE  Simulation of Generalized Return Ratio  (GRR ) vs. Loop Gain (LG)

102

104

106

108

1010

1012

-200

-150

-100

-50

0

50

freq [Hz]

dB

Av (Output)

Ai (Output)

102

104

106

108

1010

1012

-200

-100

0

100

freq [Hz]

Deg

ree

Av (Output)

Ai (Output)

RRV & RRI w/ Output Break Point

– 4 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Page 5: SPICE  Simulation of Generalized Return Ratio  (GRR ) vs. Loop Gain (LG)

GRR Simulation w/ Input Break Point

– 5 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

VO VO

RC

Q1

RC

Vr

Q1

RF

C

Vt

L

RF

LIr

It

RRV RRI

Page 6: SPICE  Simulation of Generalized Return Ratio  (GRR ) vs. Loop Gain (LG)

102

104

106

108

1010

1012

-200

-150

-100

-50

0

50

freq [Hz]

dB

Av (Input)

Ai (Input)

102

104

106

108

1010

1012

-200

-100

0

100

freq [Hz]

Deg

ree

Av (Input)

Ai (Input)

RRV & RRI w/ Input Break Point

– 6 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Page 7: SPICE  Simulation of Generalized Return Ratio  (GRR ) vs. Loop Gain (LG)

102

104

106

108

1010

1012

-200

-150

-100

-50

0

50

freq [Hz]

dB

102

104

106

108

1010

1012

-300

-200

-100

0

100

freq [Hz]

Deg

ree

Gen. RR (Output)

Gen. RR (Input)

Gen. RR (Output)

Gen. RR (Input)

GRR (RR-1 = RRV-1 + RRI

-1)

– 7 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Page 8: SPICE  Simulation of Generalized Return Ratio  (GRR ) vs. Loop Gain (LG)

Loop-Gain Simulation

– 8 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Product of two voltage gains is the loop gain (why?)

Vt driving at Input Vt driving at Output

Vr

Q1

RF

RC

C

Vt

Vr Q1

RF

RC

C

Vt

Page 9: SPICE  Simulation of Generalized Return Ratio  (GRR ) vs. Loop Gain (LG)

102

104

106

108

1010

1012

-200

-150

-100

-50

0

50

freq [Hz]

dB

Gen. RR (Output)

Gen. RR (Input)Loop-Gain

102

104

106

108

1010

1012

-300

-200

-100

0

100

freq [Hz]

Deg

ree

Gen. RR (Output)

Gen. RR (Input)Loop-Gain

GRR vs. LG

– 9 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

Page 10: SPICE  Simulation of Generalized Return Ratio  (GRR ) vs. Loop Gain (LG)

-0.1 0 0.1 0.2 0.3 0.4 0.5

-1

-0.8

-0.6

-0.4

-0.2

0

RRO

RRILG

Nyquist Diagram

– 10 –

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013

-2 0 2 4 6 8 10 12-5

-4

-3

-2

-1

0

1

RRO

RRILG

Page 11: SPICE  Simulation of Generalized Return Ratio  (GRR ) vs. Loop Gain (LG)

Advanced Analog IC DesignProfessor Y. Chiu

EECT 7326Fall 2013*Generalized Return-Ratio Calculation

*Comparison of RR to Loop-Gain Simulation

*A simple model of BJT w/o capacitance.MODEL npn NPN+IS=1.0E-16 BF=200 VAF=1000 RB=0

*The basic TIA sub-circuit used in sim..subckt TIA V1 V2 V3 V4Q1 V2 V1 GND NPN M=1Rmu V1 V2 1xCpi V1 GND 0.3pCmu V1 V2 100fCcs V2 GND 100pRC VCC V2 10kRF V3 V4 20k*Bias up the circuit w/ ideal I and bypass CICC GND VCC 1.005mCCC GND VCC 1.ends TIA

*Calculate the gen. RR*Break loop open at output, voltage driveXOV OV1 OV2 OV1 OV4 TIALOV OV2 OV4 1e3COV OV4 OV3 1VOV OV3 GND AC=1*Break loop open at output, current driveXOI OI1 OI2 OI1 OI4 TIACOI OI2 GND 1LOI OI2 OI4 1e3IOI GND OI4 AC=1

*Break loop open at input, voltage driveXIV IV1 IV2 IV3 IV2 TIALIV IV1 IV3 1e3CIV IV1 IV4 1VIV IV4 GND AC=1*Break loop open at input, current driveXII II1 II2 II3 II2 TIALII II1 II3 1e3CII II3 GND 1III GND II1 AC=1

*Calculate the loop-gain w/ direct voltage driveXLI LI1 LI2 LI1 LI2 TIACLI LI3 LI1 1VLI LI3 GND AC=1XLO LO1 LO2 LO1 LO2 TIACLO LO3 LO2 1VLO LO3 GND AC=1

.op

.ac dec 10 1e3 1e12*Derive RR from the gen. RR's @ output terminal.probe ac RRO=par('(v(OV2)*i(COI))/(v(OV2)+i(COI))')*Derive RR from the gen. RR's @ input terminal.probe ac RRI=par('(v(IV3)*i(CII))/(v(IV3)+i(CII))')*Derive loop-gain by multiplying two gains.probe ac LG=par('v(LI2)*v(LO1)')

.option nomod nopage captab post acout=0 ingold=2

.temp 25

.end