Upload
sandeep-patil
View
212
Download
0
Embed Size (px)
Citation preview
Open-Silicon ConfidentialOpen-Silicon Confidential
Static Timing AnalysisJanuary 05
222Open-Silicon ConfidentialOpen-Silicon Confidential
Goals for today
►Introduction to STA and the basic idea behind the process.
►STA inputs and outputs.►Defining and applying constraints.►Analyze the results of STA.►Sample STA run and reports
333Open-Silicon ConfidentialOpen-Silicon Confidential
Synchronous Design
► In Synchronous Design Clock Controls the Dataflow???
► On Every Clock Tick data moves from one State to Another
► Logic Delay between two state has to be Less then clock Period
► Almost all ASICs are Synchronous Designs
444Open-Silicon ConfidentialOpen-Silicon Confidential
Synchronous Design: Example
► Out = 1’b1 if (A+B)>(C+D) else 1’b0
A
B
C
D
Clk
OutAdd
Add
Comp.
555Open-Silicon ConfidentialOpen-Silicon Confidential
Timing Analysis
► Logic delay between any two Flops need to be smaller then Clock Period
► There are Two ways to verify ― Dynamic Timing analysis― Static Timing analysis
666Open-Silicon ConfidentialOpen-Silicon Confidential
Dynamic Timing analysis
► Timing simulation with Series of Functional vectors
► Simulator will take in netlist, Gate delays
► Check if there is any Timing Violations
777Open-Silicon ConfidentialOpen-Silicon Confidential
Dynamic Timing analysis
► Weakness of DTA― It is difficult to generate vectors which
cover all combinations of logic― Requires huge CPU and Memory ― Time consuming
888Open-Silicon ConfidentialOpen-Silicon Confidential
Static Timing Analysis
► Design is broken down in sets of timing paths
► Delay of each path is calculated► Compare path delay to constraints
check if they have been met
► Why is it called STA?
999Open-Silicon ConfidentialOpen-Silicon Confidential
Static timing analysis: Advantages
► Do not require any vectors► Runs very fast► More efficient in CPU and Memory
usage
101010Open-Silicon ConfidentialOpen-Silicon Confidential
What STA checks
► If design Can work at given Max Frequency► If Design can work in different operating
(PVT) conditions► If Design Satisfies Electrical constraints
(Trans, cap, fanout etc)► Signal Integrity of routing
111111Open-Silicon ConfidentialOpen-Silicon Confidential
Timing Paths
► Design is broken down in sets of signal paths
► Each path has startpoint and Endpoint ► Startpoint is Primary Input or Clock
pins of Register► Endpoint is Primary output or D pins of
registers► Register is a cell with setup/Hold time
requirement e.g Flop, Memory etc.
121212Open-Silicon ConfidentialOpen-Silicon Confidential
Timing path Types
131313Open-Silicon ConfidentialOpen-Silicon Confidential
Timing path Types cont…
► Primary input to register― Start From Input Pin, Ends at Register― Example In1 to FF1― Requires Setting input delay at input
pin relative to clock
141414Open-Silicon ConfidentialOpen-Silicon Confidential
Timing path Types cont…
► Register to register― Start from Clock pin of Register― Ends at D pin of Register― Example: Path between FF1 to FF2― Constrained by specification of the
clock
151515Open-Silicon ConfidentialOpen-Silicon Confidential
Timing path Types cont…
► Register to output― Start from Clock pin of Register― Ends at Output Pin― Example: Path between FF2 to Out1― Constrained by specification Output
delay on output port
161616Open-Silicon ConfidentialOpen-Silicon Confidential
Timing path Types cont…
► Input to output― Start from Input Pin― Ends at Output Pin― Example: Path between In2 to Out2― Constrained by specification Output
delay on output port and input delay on input port
171717Open-Silicon ConfidentialOpen-Silicon Confidential
Path Groups
► Paths are grouped according to clocks controlling their endpoints
► Set of paths associated with a clock is called as path group
► All paths with no particular clock goes to default path group
181818Open-Silicon ConfidentialOpen-Silicon Confidential
Timing Checks
► Typical Timing checks done are― Setup and Hold― Recovery and Removal― Minimum pulse width― Glitch detection (clock gating)
191919Open-Silicon ConfidentialOpen-Silicon Confidential
Setup and Hold
► Minimum time that a data input pin of a Sequential cell must be stable Before Clock Transition.
► Minimum time that a data input pin of a Sequential cell must be stable After Clock Transition.
202020Open-Silicon ConfidentialOpen-Silicon Confidential
212121Open-Silicon ConfidentialOpen-Silicon Confidential
Recovery and Removal
► Recovery: Minimum time that an asynchronous control input pin must be stable after deserted and before next clock edge
► Removal: Minimum time that an asynchronous input pin must be stable before being deserted and after the previous clock edge
Reset
Reset
Clock
Clock
Recovery
Removal
222222Open-Silicon ConfidentialOpen-Silicon Confidential
Minimum Clock Pulse Width
► Minimum Amount of time between two consecutive Rise and fall edge of the clock
Minimum High Pulse width
Minimum Low Pulse width
232323Open-Silicon ConfidentialOpen-Silicon Confidential
Glitch Detection (Clock getting check)
1 Flip Flop
CLK
En
Clk
Clk
En
FF.Clk
242424Open-Silicon ConfidentialOpen-Silicon Confidential
Constraints
► Constraints are Designer’s goals► Restriction put by technology library
also qualify as constraints► STA measures if these goals are met.► Typical constraints are clock, input/out
put delays, design specific timing requirements
252525Open-Silicon ConfidentialOpen-Silicon Confidential
Types Of Constraints
262626Open-Silicon ConfidentialOpen-Silicon Confidential
Defining clock
► Defines which are the clock ports and the clock attributes
► create_clock –period 10n –waveform {0 5} –name clk
Waveform starts at 0 with 50% duty cycle
272727Open-Silicon ConfidentialOpen-Silicon Confidential
Generated/Derived clock
► Internal clock is divide by 4
► create_generated_clock
282828Open-Silicon ConfidentialOpen-Silicon Confidential
Virtual clock
► This path is constrained by a clock (clk) outside of chip
292929Open-Silicon ConfidentialOpen-Silicon Confidential
Clock Distribution
303030Open-Silicon ConfidentialOpen-Silicon Confidential
Clock Parameters
► Clock skew► Clock uncertainty► Clock insertion delay► Clock jitter► Ideal and propagated clock
► How this parameters affects
313131Open-Silicon ConfidentialOpen-Silicon Confidential
Clock skew
323232Open-Silicon ConfidentialOpen-Silicon Confidential
Clock jitter
333333Open-Silicon ConfidentialOpen-Silicon Confidential
Clock latency/delay
343434Open-Silicon ConfidentialOpen-Silicon Confidential
Ideal and computed Clock
► Off chip clock effects are fixed throughouta. Source latencyb. Jitter
► On chip routing is estimated for ideal clocka. Budgeted network latencyb. Budgeted skew
► On chip routing is computed after CTSa. Actual insertion delayb. Actual skew
353535Open-Silicon ConfidentialOpen-Silicon Confidential
Setting Input Delay
► Input signal arrives at 2.5ns after rising edge of CK
► Set_input_delay
363636Open-Silicon ConfidentialOpen-Silicon Confidential
Setting Output Delay
► Output signal needs to arrive time at O after xy ns
► Set_output_delay
373737Open-Silicon ConfidentialOpen-Silicon Confidential
Input Drive strength
► Along with timing constraints one needs to specify design environment
► Set_driving_cell
383838Open-Silicon ConfidentialOpen-Silicon Confidential
Output load
► Setting output load
► Set_driving_cell
393939Open-Silicon ConfidentialOpen-Silicon Confidential
Check – Check- Check
► Check_timing will check if every thing is constrained
404040Open-Silicon ConfidentialOpen-Silicon Confidential
Timing Constraints Tutorial
► Derive top Level SDC from Given Data
414141Open-Silicon ConfidentialOpen-Silicon Confidential
False Path
A false path is a timing path that cannot propagate a signal.
► A path may exist in the circuit but never be used
► A functional path may exist but the timing is very slow or irrelevant
► A path may exist in the circuit but no combination of input vectors may ever exercise it
424242Open-Silicon ConfidentialOpen-Silicon Confidential
False path Example
434343Open-Silicon ConfidentialOpen-Silicon Confidential
False path Example:Paths Between Two clocks
444444Open-Silicon ConfidentialOpen-Silicon Confidential
MultiCycle Path
► A multicycle path is a timing path that is not expected to propagate a signal in one cycle.
► Normally, all paths are constrained for single-cycle timing.
► Multicycle paths are exceptions to the default single-cycle timing..
► Multicycle paths are defined by command set_multicycle_path.
454545Open-Silicon ConfidentialOpen-Silicon Confidential
MultiCycle Paths
464646Open-Silicon ConfidentialOpen-Silicon Confidential
Functional Modes
► Complex Designs can have multiple Time paths that are dependent on the enabled functional modes
► E.g Normal Functional mode and Debug Mode
► Case analysis provides a means of setting constant paths that you want the tool to ignore during timing analysis
474747Open-Silicon ConfidentialOpen-Silicon Confidential
Operating Conditions
► The operating conditions of a design usually include the process, voltage, and temperature ranges a design encounters.
► Operating conditions are defined in a technology library in an operating_conditions group.
► You can choose operation condition by set_operating_condition
484848Open-Silicon ConfidentialOpen-Silicon Confidential
Specify Design data and libraries
Specify Interconnect
Specify Clocks
Specify Input/Output
Delays
Specify Timing
Exceptions
ASIC Netlist
ASIC Libarary
SPEF Wire Load Models
Back-annotated
STA Methodology
494949Open-Silicon ConfidentialOpen-Silicon Confidential
STA Methodology
Check Timing
Update Timing
Generate Reports
Constraints Violators
Path Timing
Bottleneck
Reports
505050Open-Silicon ConfidentialOpen-Silicon Confidential
Delays
► Total Delay = Cell Delay + Interconnect Delay
► Cell Delay depend upon Input transition and output cap.
► Interconnect Delay depends upon capacitance and resistance
► User need to provide Interconnect R, C
515151Open-Silicon ConfidentialOpen-Silicon Confidential
Specify Interconnect
► Standard parasitic Exchange format (SPEF) file― Extracted R and C
► Standard Delay Format (SDF)― Accurate timing information from Delay
calculation tool► Wireload Models
― Pre-layout net delay estimates
525252Open-Silicon ConfidentialOpen-Silicon Confidential
Path Delay
► Actual path delay is sum of net and cell delays along timing the path
535353Open-Silicon ConfidentialOpen-Silicon Confidential
Net Delays
► Is the total time need to charge or discharge all the parasites of a Net
► Net parasites depends up on― Net Length― Net Routing― Net Fanout
545454Open-Silicon ConfidentialOpen-Silicon Confidential
On-Chip variation
► Intra die variation and intra wafer process variations.
► Temperature and voltage variation on the die.
► Deration of the appropriate path for the analysis so that additional margin is obtained.
555555Open-Silicon ConfidentialOpen-Silicon Confidential
SI effects
► Effect of signal propagation on one net, affecting another adjacent net.
► Causes delay push out and glitch in the victim net.
► PT-SI analysis
565656Open-Silicon ConfidentialOpen-Silicon Confidential
STA walk through
575757Open-Silicon ConfidentialOpen-Silicon Confidential
Goals for today
►Introduction to STA and the basic idea behind the process.
►STA inputs and outputs.►Defining and applying constraints.►Analyze the results of STA.►Sample STA run and reports