Stop Watch Lecture #12

Stop Watch Design SpecificationStop Watch VHDL : Clock : 12MHz Key 2 : RESET, START_STOP

: 6 : Com0, Com1, Com2, Com3, Com4, Com5Segment LED 7 : A, B, C, D, E, F, G

Stop Watch Design Specification( Input Device )2 RESET, START_STOP 1 , 0 RESETSTART_STOP

Stop Watch Design Specification(Output Device)6 7 Segment LED .:2, :2, 1/100:2 1/100

Stop Watch Design SpecificationStop Watch (1) POWER ON RESET

- 00 : 00 : 00- START_STOP KEY

00000.00000000

Stop Watch Design Specification(2)

- 00 : 00 : 00 .. 00 : 00 : 99 00 : 01 : 00 .. 00 : 59 : 99 01 : 00 : 00 .. 59 : 59 : 99 00 : 00 : 00 - START_STOP KEY - START_STOP KEY 1/100 - RESET KEY 00:00:00 ,

=59590.99595999

Stop Watch

Stop Watch VHDL Top Diagram

Stop Watch VHDL Top DiagramENP 1 , 0 RESET Key 1 , Nclr Active Low. 6 FND . 6 1 0 1 .A,B,C,D,E,F,G Segment LED 1 LED . 2 , , 1/100 . 100Hz

Stop Watch Top Level Entitylibrary ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity stopwatch is port( clk: in std_logic; reset: in std_logic; start_stop: in std_logic; com0: out std_logic; com1: out std_logic; com2: out std_logic; com3: out std_logic; com4: out std_logic; com5: out std_logic; A : out std_logic; B : out std_logic; C : out std_logic; D : out std_logic; E : out std_logic; F : out std_logic; G : out std_logic );end stopwatch;

Stop Watch Top Level Entityarchitecture a of stopwatch iscomponent Hz100ctrl port( clk,nclr : in std_logic; Hz100 : out std_logic);end component;component keyif port( start_stop: in std_logic; clk, nclr: in std_logic; enp: out std_logic);end component;component timecontrol port( clk, nclr : in std_logic; enp: in std_logic; SSL : out std_logic_vector(3 downto 0); SSH : out std_logic_vector(3 downto 0); SECL: out std_logic_vector(3 downto 0); SECH: out std_logic_vector(3 downto 0); MINL: out std_logic_vector(3 downto 0); MINH: out std_logic_vector(3 downto 0));end component;component outputif port( clk, nclr : in std_logic; SSL : in std_logic_vector(3 downto 0); SSH : in std_logic_vector(3 downto 0); SEC: in std_logic_vector(3 downto 0); SECH: in std_logic_vector(3 downto 0); MINL: in std_logic_vector(3 downto 0); MINH : in std_logic_vector(3 downto 0); com_out: out std_logic_vector(5 downto 0); seg_out: out std_logic_vector(6 downto 0));end component;

Stop Watch Top Level Entitysignal nclr : std_logic;signal Hz100 : std_logic;signal enp: std_logic;signal SSL : std_logic_vector(3 downto 0);signal SSH : std_logic_vector(3 downto 0);signal SECL : std_logic_vector(3 downto 0);signal SECH : std_logic_vector(3 downto 0);signal MINL : std_logic_vector(3 downto 0);signal MINH : std_logic_vector(3 downto 0);signal com_out: std_logic_vector(5 downto 0);signal seg_out: std_logic_vector(6 downto 0);begin

nclr

Stop Watch 100Hz Gen.12MHz Clock(=clk) 1/100 100Hz(=Hz100) 100Hz 1/100 Stop Watch 1/100 . TimeControl KeyIF 12MHz:100Hz=120000:1 12MHz 120000 100Hz 1 . 12MHz

Stop Watch 100Hz Gen.library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity Hz100ctrl is port( clk, nclr : in std_logic; Hz100 : out std_logic);end Hz100ctrl;architecture a of Hz100ctrl issignal cnt : std_logic_vector(5 downto 0);signal sHz100 : std_logic;beginprocess(nclr,clk)variable cnt : integer range 0 to 65535;variable sHz100 : std_logic;beginif( nclr='0') thencnt := 0;sHz100 :='0';elsif (clk'event and clk='1') thenif (cnt=62915) thencnt := 0;sHz100 := not sHz100;elsecnt := cnt + 1;end if;end if;Hz100

Stop Watch Key InterfaceStart_Stop Stop Watch / ENP ENP 1/100 Hz100 Shift Register 100Hz ENP 1 , 0 Clk Clk Start_Stop 1 , StartStop

Stop Watch Key Interfacelibrary ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity keyif is port( start_stop : in std_logic;clk,nclr : in std_logic; enp: out std_logic);end keyif;architecture a of keyif issignal q : std_logic_vector( 1 downto 0);signal RisingShotPules : std_logic; signal s_enp: std_logic;Begin

process(nclr,clk) -- shift register 2bits :beginif( nclr='0') thenq

Stop Watch Key Interface

-- enp generationprocess(nclr,clk)beginif( nclr='0') thens_enp

Stop Watch Time Control ENP 0 , 1 00:00:00 .. 00:00:99 00:01:00 .. 00:59:99 01:00:00 .. 59:59:99 00:00:00 5900 00 00590.99ENP 1 , 0 100Hz

Stop Watch Time Controllibrary ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity timecontrol is port( clk,nclr : in std_logic; enp : in std_logic; SSL : out std_logic_vector(3 downto 0); SSH : out std_logic_vector(3 downto 0); SECL : out std_logic_vector(3 downto 0); SECH : out std_logic_vector(3 downto 0); MINL : out std_logic_vector(3 downto 0); MINH : out std_logic_vector(3 downto 0));end timecontrol;architecture a of timecontrol issignal s_SSL : std_logic_vector(3 downto 0);signal s_SSH : std_logic_vector(3 downto 0);signal s_SECL : std_logic_vector(3 downto 0);signal s_SECH : std_logic_vector(2 downto 0);signal s_MINL : std_logic_vector(3 downto 0);signal s_MINH : std_logic_vector(2 downto 0);begin Counter ENP=1 . 1/00

Stop Watch Time Controls_SSL_cnt: process(nclr,clk)beginif( nclr='0') thens_SSL

Stop Watch Time Controls_SECL_cnt: process(nclr,clk)beginif( nclr='0') thens_SECL

Stop Watch Time Controls_MINL_cnt: process(nclr,clk)beginif( nclr='0') then s_MINL

Stop Watch Output Interface, , 1/100 6 7 Segment LED a,b,c,d,e,f,g 6 7 Segment LED 6 6 7 Segment LED BCD-7 Segment Decoder 1 2 3 4 9 0 112340.90BCD-7 Segment Decoder 6 1 0 1 High FND Low FND

Stop Watch Output Interfacelibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity outputif is port( clk,nclr : in std_logic; SSL : in std_logic_vector(3 downto 0); SSH : in std_logic_vector(3 downto 0); SECL : in std_logic_vector(3 downto 0); SECH: in std_logic_vector(3 downto 0); MINL: in std_logic_vector(3 downto 0); MINH: in std_logic_vector(3 downto 0); com_out: out std_logic_vector(5 downto 0); seg_out: out std_logic_vector(6 downto 0));end outputif;

architecture a of outputif issignal muxout : std_logic_vector(3 downto 0);signal cnt : std_logic_vector(2 downto 0);signal dp: std_logic;signal fnd_clk : std_logic;begin

Stop Watch Output Interface-- clock divisorprocess(clk)variable cnt : integer range 0 to 65535;variable clk_out : std_logic;beginif (clk'event and clk = '1') then if cnt < 3300 then cnt := cnt + 1; elsif cnt = 3300 then cnt := 0; clk_out := not clk_out; end if;end if;fnd_clk

Stop Watch Output Interface

-- com signal gen : 3X8 decoder process(cnt)begincase cnt iswhen "000" => com_out com_out com_out com_out com_out com_out com_out muxout

Stop Watch Output Interface

-- BCD to 7 Segment gen process(muxout)variable seg_decode : std_logic_vector(6 downto 0); begincase muxout iswhen "0000" => seg_decode seg_decode seg_decode seg_decode seg_decode seg_decode seg_decode seg_decode seg_decode seg_decode seg_decode

FPGA Device Setting FPGA Assignment-deviceFamily: CyclonDevice: EP1C12Q240C8Device & Pin Options configurationConfiguration Scheme: Passive SerialUse Configuration Device : EPC2

FPGA Assign PinsFPGA VHDL PIN .Assignment - PinsTo: VHDL Location: FPGA Assignment - Pin Planner

FPGA-IOM.pdf FPGA FND, Clock FPGA

FPGA Bd

FPGA Bd

Pin Assignment

FPGA Configuration (1)Pin FPGA .Tools-ProgrammerHardware SetupAdd Hardware: ButeBlasterMV or ByteBlaster II , LPT1

FPGA Configuration (2)Tools-Programmer ByteBlaster . Auto DetectEPC2 EP1C6 .EP1C12 sof EP1C12 Program/Configure Start FPGA .

FPGA Configuration (3) FPGA .FPGA Flash .File-Convert Programming FilesConfiguration Device: EPC2 Add file sof .Generate EPC2 pof .

FPGA Configuration (4)Tools-Programmer ByteBlaster . Auto DetectEPC2 EP1C6 .EP2 pof EP2 Program/Configure Start FPGA . .