系系 統統 程程 式式System ProgrammingSystem Programming

BACKGROUNDBACKGROUND 1/31/3

1. What is system software ?2. Major topics about system software:

Assemblers, Loader and Linkers, macroprocessors, compilers operating systems, database management systems, text editors, interactive debugging systems.

3. What is the difference between AP and SP ?It is machine dependency.

BACKGROUNDBACKGROUND 2/32/3

4. Each system software is described by the following functions:

(1)fundamental features(2)machine-independent features(3)machine-dependent features(4)Major design idea(5)Example of implementations

BACKGROUNDBACKGROUND 3/33/3

5. Simplified Instructional Computer (SIC), SIC/XE (with extra equipment)(1)memory(2)registers(3)data formats(4)Instruction formats(5)addressing mode

SIC machine architectureSIC machine architecture 1/21/2

(1)Memory8-bit byte, 24-bit word, 32k memory size(=215)

(2)Instruction format8 1 15

(3)Data formatInteger: 24-bit binary numbers

(2’s complement for negative).Character: 8-bit ASCII codes.

opcode x address

SIC machine architectureSIC machine architecture 2/22/2

(4)Addressing modeDirect : X=0, target address = address Indexed : X=1, target address = address +(X)

(5)RegisterA: accumulatorX: index registerL: linkage registerPC : program counterSW : status word

SIC/XE machine SIC/XE machine architecture architecture 1/51/5

(1)Memery 1 M memory Size (=220)

(2)Instruction format8

8 4 4

6 1 1 1 1 1 1 12

6 1 1 1 1 1 1 20

opcode

opccode register register

opcode n i x b p e displacement

opcode n i x b p e displacement

SIC/XE machine SIC/XE machine architecture architecture 2/52/5

(3)Data format

Floatng-point : 1 11 36s exponent fraction

(4)Addressing modeProgram-counter relative :b=0, p=1, TA=(PC) + disp (-2048<=disp<=2047)Base relative :b=1, p=0, TA=(B) + disp (0<=disp<=4095)Direct : i=0, n=0, TA=(disp or addr)Index :X=1

SIC/XE machine SIC/XE machine architecture architecture 3/53/5

Immediate :i=1, n=0, operand=dispIndirect : i=0, n=1, TA’=(TA)Extended :i=1, n=1, e=1, TA=addr

SIC/XE machine SIC/XE machine architecture architecture 4/54/5

(5)RegisterB : base registerS : general working registerT : general working registerF : floating-point accumulator (48-bit)

SIC/XE machine SIC/XE machine architecture architecture 5/55/5

CPU MemoryCPU Memory

I / OI / O

PC

IR

Decoder

CUALU

instruction

Data

ACC

( T A )

( P C )

Data

(LDA)

LDA

Machine instruction

Hex Binaryop n i x b p e disp/address

(1)032600 000000 1 1 0 0 1 0 0110 0000 0000LDA:load address SIC/XE pc:program counter

Target address : 003000(program counter)+ 6 0 0= 3 6 0 0

Value loaded into register A: 103000 · ·p11. figure(a) : 3600 103000

000000 110010 0110 0000 0000 · ·Hex: 0 3 2 6 0 0

Hex op n i x b p e Hex op n i x b p e dispdisp/address/address(2)03C300 000000 1 1 1 1 0 0 0011 0000 0000(2)03C300 000000 1 1 1 1 0 0 0011 0000 0000

LDA:load address SIC/XE index baseLDA:load address SIC/XE index baseTarget address :Target address : 000090000090(index register) (index register) + 3 0 0+ 3 0 0

006000006000(base register)(base register)

= 6 3 9 0= 6 3 9 0

Value loaded into register A: 00C303Value loaded into register A: 00C303 ·· ···· ··

p11. figure(a) : 639p11. figure(a) : 6390 00C3030 00C303

·· ··000000 111100 0011 0000 0000 000000 111100 0011 0000 0000 ·· ··

Hex: 0 3 C 3 0 0Hex: 0 3 C 3 0 0

Hex op n i x b p e Hex op n i x b p e dispdisp/address/address(3)022030 000000 1 0 0 0 1 0 0000 0011 0000(3)022030 000000 1 0 0 0 1 0 0000 0011 0000

indirect pcindirect pcTarget address :Target address : 003000003000(program counter) (program counter) + 0 3 0+ 0 3 0

= 3 0 3 0 = 3 0 3 0 (indirect address)(indirect address)

load address:3 6 0 0load address:3 6 0 0 ·· ··Value loaded into register A: 103000Value loaded into register A: 103000 3030 003600 3030 003600

·· ··p11. figure(a) : p11. figure(a) : ·· ··

3600 1030003600 103000·· ··

000000 100010 0000 0011 0000 000000 100010 0000 0011 0000 ·· ··Hex: 0 2 2 0 3 0Hex: 0 2 2 0 3 0

Hex op n i x b p e Hex op n i x b p e dispdisp/address/address(4)010030 000000 0 1 0 0 0 0 0000 0011 0000(4)010030 000000 0 1 0 0 0 0 0000 0011 0000

immediateimmediateTarget address :Target address : ++ 00 3 03 0

= 3 0= 3 0Value loaded into register A: 000030Value loaded into register A: 000030

000000 010000 0000 0011 0000000000 010000 0000 0011 0000Hex : 0 1 0 0 3 0Hex : 0 1 0 0 3 0

Hex op n i x b p e Hex op n i x b p e dispdisp/address/address(5)003600 000000 0 0 0 0 1 1 0110 0000 0000(5)003600 000000 0 0 0 0 1 1 0110 0000 0000

SIC(direct)SIC(direct)Target address : (direct address) 3 6 0 0Target address : (direct address) 3 6 0 0

Value loaded into register A: 103000Value loaded into register A: 103000

·· ··p11. figure(a) : 3600 p11. figure(a) : 3600 103000103000

·· ··000000 000011 0110 0000 0000 000000 000011 0110 0000 0000

Hex: 0 0 3 6 0 0Hex: 0 0 3 6 0 0

(6) Hex op n i x b p e (6) Hex op n i x b p e dispdisp/address/address0310C303 000000 1 1 0 0 0 1 0000 1100 0011 0000 00110310C303 000000 1 1 0 0 0 1 0000 1100 0011 0000 0011

SIC/XE extendedSIC/XE extendedTarget address : 0 C 3 0 Target address : 0 C 3 0 33

Value loaded into register A: 003030Value loaded into register A: 003030 ·· ···· ··

p11. figure(a) : C303 p11. figure(a) : C303 003030003030

·· ··000000 110001 0000 1100 0011 0000 0011 000000 110001 0000 1100 0011 0000 0011

Hex:0 3 1 0 C 3 0 3Hex:0 3 1 0 C 3 0 3

Sample data movement operationsSample data movement operationsfor (a)SIC and (b)SIC/XEfor (a)SIC and (b)SIC/XE

LDA FIVESTA ALPHA

LDCH CHARZSTCH C1

.ALPHA RESW 1FIVE WORD 5CHARZ BYTE C ’ Z ’C1 RESB 1

LDA # 5STA ALPHALDA # 90STCH C1

.ALPHA RESW 1C1 RESB 1

Sample data movement operations for (a)SIC Sample data movement operations for (a)SIC CPU

A:

(ACC)

MEMORY

(word)

FIVE:

ALPHA:

(byte)

CHARZ:

C1:

(Z:character)

5

5

Z

Z

5

LDA FIVE STA ALPHALDCH CHARZSTCH C1.

ALPHA RESW 1FIVE WORD 5

CHARZ BYTE C ’ Z ’C1 RESB 1

Z

Sample data movement operations for (b)SIC/XESample data movement operations for (b)SIC/XECPU

A:

(ACC)

MEMORY

(word)

ALPHA:

(byte)

C1:

5

90->5A (ASCII CODE) =Z

5

LDA # 5 STA ALPHA LDA # 90 STCH C1 .

ALPHA RESW 1C1 RESB 1

90

Sample arithmetic operations for (a)SIC and (b)SIC/XESample arithmetic operations for (a)SIC and (b)SIC/XE

LDA ALPHA ADD INCRSUB ONESTA BETA BETA←ALPHA+INCR-ONELDA GAMMAADD INCRSUB ONESTA DELTA DELTA←GAMMA+INCR-ONE

.

. ONE WORD 1.ALPHA RESW 1BETA RESW 1GAMMA RESW 1DELTA RESW 1

INCR RESW 1 1 1/21/2

LDS INCR LDA ALPHAADDR S , ASUB # 1 STA BETALDA GAMMAADDR S , A SUB # 1 STA DELTA..

ALPHA RESW 1BETA RESW 1GAMMA RESW 1DELTA RESW 1INCR RESW 1

2/2

Sample arithmetic operations for (a)SIC and (b)SIC/XESample arithmetic operations for (a)SIC and (b)SIC/XE

Sample looping and indexing operation for (a)SIC,(b)SIC/XESample looping and indexing operation for (a)SIC,(b)SIC/XE

LDX ZEROMOVECH LDCH STR1 , X

STCH STR2 , X TIX ELEVENJLT MOVECH...

STR1 BYTE C ‘ TEST STRING ‘STR2 RESB 11..

ZERO WORD 0ELEVEN WORD 11

(a) 1/2

Sample looping and indexing operations for (a)SICSample looping and indexing operations for (a)SICCPU

X:

PC

ACC

Status word:

MEMORY

(word)

ZERO:

ELEVEN:

(byte)

STR1:

STR2:<

LDX ZEROMOVECH LDCH STR1 , X

STCH STR2 , X

JLT MOVECH.

STR1 BYTE C ’ TEST STRING ‘STR2 RESB 11.ZERO WORD 0ELEVEN WORD 11

0

11

T

T E S T S T R I N G

0

( test X=1 ,ELEVEN=11 )

TIX ELEVEN

0 ->1

( 1 < 11 )

T

MOVECH

LDT # 11LDX # 0

MOVECH LDCH STR1 , XSTCH STR2 , XTIXR T JLT MOVECH

.

.

. STR1 BYTE C ’ TEST STRING ‘STR2 RESB 11

(b) 2/2

Sample looping and indexing operation for (a)SIC,(b)SIC/XESample looping and indexing operation for (a)SIC,(b)SIC/XE

Sample looping and indexing operations for (b)SIC/XESample looping and indexing operations for (b)SIC/XECPU

X:

T:

PC

ACC

Status word:

MEMORY

(byte)

STR1:

STR2:

T E S T S T R I N G

T

LDT #11

MOVECH LDCH STR1 , XLDX #0

STCH STR2 , XTIXR TJLT MOVECH

STR1 BYTE C ’ TEST STRING ‘STR2 RESB 11

.

11

00 ->1( text X=1 ,T= 11 )( 1 < 11 )

<

T

MOVECH

Sample indexing and looping operation for (a)SIC,(b)SIC/XESample indexing and looping operation for (a)SIC,(b)SIC/XELDA ZEROSTA INDEX

ADDLP LDX INDEXLDA ALPHA , XADD BETA , X STA GAMMA , X LDA INDEXADD THREESTA INDEX COMP K300 JLT ADDLP.

INDEX RESW 1.ALPHA RESW 100BETA RESW 100GAMMA RESW 100.

ZERO WORD 0K300 WORD 300 1/2

(a)

LDS # 3 LDT # 300 LDX # 0

ADDLP LDA ALPHA , XADD BETA, XSTA GAMMA, XADDR S , X COMPR X , T JLT ADDLP ..

ALPHA RESW 100BETA RESW 100GAMMA RESW 100

(b) 2/2

Sample indexing and looping operation for (a)SIC,(b)SIC/XE

Sample input and output operations for SIC Sample input and output operations for SIC INLOOP TD INDEV

JEQ INLOOPRD INDEV ACC←INPUTSTCH DATA ACC→DATA.. .

OUTLP TD OUTDEVJEQ OUTLPLDCH DATA ACC←DATAWD OUTDEV ACC→OUTPUT...

INDEV BYTE X ‘ F1 ‘OUTDEV BYTE X ‘ 05 ‘DATA RESB 1

pooling busy waiting

Sample subroutine call and record input operations Sample subroutine call and record input operations for(a)SIC (b) SIC/XEfor(a)SIC (b) SIC/XE

JSUB READ. .

READ LDX ZERORLOOP TD INDEV

JEQ RLOOP RD INDEV STCH RECORD , XTIX K100JLT RLOOP RSUB..

INDEV BYTE X ‘ F1 ‘RECORD RESB 100.ZERO WORD 0K100 WORD 100

(a) 1/2

…

X=1 =2 … 100

RECORD

JSUB READ..

READ LDX # 0LDT # 100

RLOOP TD INDEVJEQ RLOOPSTCH RECORD , XTIXR TJLT RLOOPRSUB ..

INDEV BYTE X ’ F1 ‘RECORD RESB 100

(b) 2/2

Sample subroutine call and record input operations Sample subroutine call and record input operations for(a)SIC (b) SIC/XEfor(a)SIC (b) SIC/XE