TekStart HMCC Overview 2015-07

TekStart LLC- CONFIDENTIAL

TEKSTARTHybrid Memory Cube (HMC+) Controller IP

July 2015

®

TEKSTART Overview

� Leading value-added facilitator of technology development for hardware, system, semiconductor, EDA and IP solution companies

� Accelerating the time to enterprise development with experienced team facilitating initial business and market development.

� Providing partners a sales channel and know-how, to expedite revenue, initial funding and company build out.

Getting partners to market faster and more efficiently than left to their own devices

TEKSTART LLC - CONFIDENTIAL

Management Team� Howard Pakosh, Managing PartnerEntrepreneur and senior executive experienced in semiconductor intellectual property (SIP) and EDA. Highly motivated leader with an emphasis on partnerships, and strategic accounts with large, mutual upside.SONICS, Elliptic, Virage Logic, Synopsys, Magma, Avant!

� D. Christopher Keil, Managing PartnerSemiconductor professional experienced in Business Development, Strategic Marketing and Corporate Development. Skilled in market evaluation, and ability to provide partners guidance, knowledge and choices for development. RMI (Broadcom), LSI, Virage Logic, Kellogg MBA -Northwestern

TekStart LLC - CONFIDENTIAL

� Gregg Recupero, CTOSemiconductor and IP executive with history of company development, sales, and engineering know-how. Deeply technical professional with vast network of global contacts. Performance-IP, Vautomation, Boston Circuits and AMD.

� Phil Casini, AdvisorPhil is a Sr. VP at Cisco Systems. He is a recognized author, having published reports on a variety of topics from SoC architectures and semiconductor IP economics to IP Video trends. Phil has also pioneered a new analytical method for establishing product and service value and improving it communications with customers, which is called Visual Product Analytics. Phil has spent 26 years in the semiconductor industry, including 14 years as a Vice President, with companies such as Intel, Dallas Semiconductor, Cirrus Logic, Cradle Technologies and Sonics Inc.


Management Team

Current Market Conditions� “The goal of activities in a value chain is to add more value for the customer than the cost of carrying out the activity” –Michael Porter, 1985 best-seller, “Competitive Advantage: Creating and Sustaining Superior Performance”

� Shifts in value chains are happening within the semiconductor industry value chain

� Evolution in the embedded and memory industries is imminent

� Industry demanding more performance without sacrificing power (if not lower power)


TekStart Engineering� Design Center in Boston, MA � Staffed by a talented, proven team of professionals

� >100 years of IP development, marketing and sales experience� Engineering team has 5 staff engineers and 1 manager� All with ASIC design, IP design and application support experience

� Differentiation� Patent-Pending Memory Tracker TechnologyTM (MTT) is designed to recover lost system performance

� MTT is incorporated into the majority of the IP portfolio� Current customers

� Over 15 customers spanning the following markets:○ Consumer electronics○ Automotive○ Networking○ Government (special ops)

IP Product Portfolio

�Memory Request Optimizer (MRO)

� Level 2+ Cache (L2+)� High Performance DMA+ Controller

� SoC Subsystem Manager (SSM)� HMC+ Controller with Enhanced Latency Reduction (ELR)

Memory Tracker TechnologyTM

! Improves the spatial locality of a clients request stream! Greater efficiency! Patent-Pending

! Embedded in:! Memory Request Optimizer! L2+ Cache! HMC+

Memory Request Optimizer

MRO Optimization

Processor IPCImprovement

App1* App2* App3* App3**Mode 1 11.1% 14.0% 8.8% 17.6%Mode 2 13.0% 14.0% 14.1% 29.4%Mode 3 14.4% 15.5% 15.7% 35.29%

* 25 cycles of memory latency** 100 cycles of memory latency

� Incorporates Memory Tracker TechnologyTM � Patent-Pending� Design to recover lost system performance� Reduces memory latency� Sold as a separate macro for memory subsystem design

� DDR Performance Improvement Numbers

L2+ Cache� Leverages Memory Tracker TechnologyTM� Outperforms typical L2 Caches up to 2-4x the size

64KBx8 Traditional L2 Cache

64KBx8 L2+ Cache withMemory Tracker TechnologyTM

Application 1

Latency Reduction 82% 84%

Hit Rate 95.8% 99.5%

Memory Reads 4.2% 4.2%

Application 2


Hit Rate 92.9% 99.1%


Application 3


Hit Rate 45.0% 99.5%


HP-DMA Controller

� High-performance DMA engine

� Independent DMA channels

� Small RAM buffer� Low gate count� Configurable bus widths

� Scatter gather operation

DMA CH0

DMA CH1

DMA CH7

.

.

.

ReadComman

dFIFO

WriteComman

dFIFO

ARBITERS

AXIReadChannelMaster

RAMBuffer

AXI4-Lite

Slave I/F

ProgrammableControlRegisters

AXIWriteChannelMaster

12

SoC Subsystem Manager (SSM)Industry’s First Policy-Based System Management

Subsystem IP

• Dynamically Load Software Policies into Programmable SSM Controller

• SSM Controller Converts Software Policies to Hardware Signals and Routes to Connected Hardware Blocks via SSM Bus

• SSM Also Supports Message Passing to Hardware• Patent Pending

Core 1

Processor Subsystem

VideoProcessing

AudioProcessing

Core 2

I/O Subsystem

Global Interconnect

MemoryScheduler &Controller

COMProcessing

SSM

Controller

Power Management 1

Power Management 2

Security Policies

Reset Policy 1Reset Policy 2

Error Recovery 1Error Recoveryt 2

Soft Boot SequencingHard Boot Sequencing

Policies Host Processor Triggers Policy Changes

Video OptimizedPolicy Suite

13

SSM Dynamic System AdoptionReal Time System Management Based on User Behavior

Power Management 1

Video Optimized SecurityReset Policy 1

Error Recovery 1Soft Boot SequencingHard Boot SequencingStreaming Memory Schedules

Data OptimizedPolicy Suite

Power Management 2

Internet SecurityReset Policy 2

Error Recovery 2Soft Boot SequencingHard Boot SequencingPacket Memory Schedules Version Update

Policy SuitePower Management 1

Version Update SequenceOffline Sequencing

Testing SequencesSoft Boot SequencingHard Boot SequencingMemory Flush and Updating

Application Use TriggersOptimized Policy Suite Loading

Also Ideal for Controlled Version Update Sequencing


Hybrid Memory Cube (HMC)Introduction

HMC – An Introduction


Hybrid Memory Cube – An entirely new leap forward in memory technology

�Better Performance� 15X the performance of DDR3 results in greater throughput (bandwidth)

�Lower Power� 70% power reduction (per bit) as compared to DDR3

�Smallest Footprint� Up to a 90% area reduction than comparable RDIMM’s

�Facilitates market growth � 100G and 400G networks � High-resolution (high bandwidth) digital video

HMC Consortium

� Hybrid Memory Cube (HMC) members include:� Micron, Samsung, SK Hynix, Xilinx, Altera, ARM, TekStart, and 120+ other companies

� HMC first announced in February 2011 � HMC 1.0 Spec publicly released in April 2013 � HMC 2.0 Spec publicly released in October 2014 � HMC (SR-15) parts now available from Micron


HMC Benefits

� Pros� Higher Performance� Better Power Efficiencies

� Board Space Reductions


� Cons� Parallel vs. Serial� Higher Average Latency

TekStart is a proud Member of the Hybrid Memory Cube Consortiumwww.hybridmemorycube.org

Market Opportunity

� Target customers� Storage� Networking/Communication� Cloud computing

� Average annual shipments � Approx. 1M per device/design start� Annual ASIC design starts in above markets equal 200-250 worldwide

� Penetration� If just 10% market acceptance would equate to 20M devices per year with HMC ‘inside’


Market Opportunity



HMC Technology

HMC Construction

�DRAM Stack � Consists of DRAM arrays connected using Through Silicon Vias (TSV)

�Logic Base � Manages DRAM Stack (self test & repair, command reordering, error correction, refresh, scrubbing, etc.)

� Hides complexity of DRAM Stack from the user

� Provides high speed, SERDES-based interface to DRAM Stack


HMC (SR-15) Overview�Components have 2 or 4 links

� Each link has 16 Tx & 16 Rx lanes ○ Supports full-width link (16 lanes) and half-width link (8 lanes) operation

� Lanes can run at 10, 12.5 or 15 Gbit/s ○ Compliant with CEI-11 SERDES standard

�Supports 2 or 4 GB of memory � Comparable in size to a DDR4/3 DIMM � Devices can be chained for additional density

�High bandwidth � 1 Half-width Link = 2 * 8 lanes * 10 Gbit/s = 20 GB/s � 1 Full-width Link = 2 * 16 lanes * 10 Gbit/s = 40 GB/s � 4 Full-width Links = 4 * 2 * 16 lanes * 10 Gbit/s = 160 GB/s � 4 Full-width Links = 2 * 2 * 16 lanes * 15 Gbits/s = 240 GB/s


Micron HMC MemoryComparison to DDR4/3



TekStart HMC+ ControllerTechnical Advantage

TekStart HMC+ Benefits

� Pros� Higher Performance� Better Power Efficiencies

� Board Space Reductions� Lower Average Latency


� Cons� Parallel vs. Serial

Standard HMC 1.1/2.x Controller


TekStart HMC+ Difference


Memory Request Optimizer� MRO Benefits:

� Recover lost system performance� Reduces memory latency

� Patent-Pending� DDR Performance Improvement Numbers

MRO Optimization

Processor IPCImprovement

App1* App2* App3* App3**Mode 1 11.1% 14.0% 8.8% 17.6%Mode 2 13.0% 14.0% 14.1% 29.4%Mode 3 14.4% 15.5% 15.7% 35.29%* 25 cycles of memory latency** 100 cycles of memory latency

HMC+ ASIC Solution

� Complete ASIC (digital) core solution� SERDES Partners include:

�Avago Technologies (30G, HMC 2.0 compliant)�OmniPHY(15G, HMC 1.1 compliant)�More to come…

HMC+ Key Features�HMC 1.1 Spec Compliant

� Full-width Link and Half-width Link support � 10, 12.5, 15 Gbit/s lane support

�ASIC & FPGA support � Delivered integrated with target PHY

�1024 and 512 bit Core Width options � Enables clock frequency to be tailored to target technology, easing timing closure

�MultiPort AXI-4 Interface option� AXI-4 widths: 1024, 512, 256, 128, 64 bits � Up to 32 ports� AXI-3 Support provided with wrapper file


HMC+ Key Features …

�High performance � Maximizes system throughput

�Control & Status Registers (CSR) support via � AXI-4 Lite or AXI-3 I/F

�Optional memory test package � Useful for bring-up/production testing and throughput characterization

�Delivered with AXI Interface Testbench �Customization services available


HMC 1.1 Spec Compliance�All HMC Controller Abstraction Layers

� Transaction Layer � Link Layer � Logical Sub-block of Physical layer

�Link initialization and training �Retries �CRC generation and checking �Link management and monitoring �Link layer flow control �Support for HMC device chaining �Low power mode support �Atomic command support �Bit write commands


Target Clock Frequencies (ASIC)

LinkLane Rate (GB/s)

Core Width (Bits) Core Freq (MHz)

Full 15 1024 234Full 10 1024 156

Full 15 512 469Full 10 512 313Half 15 512 234Half 10 512 156

HMC v2.2 spec under review. Major change noted to date is in the SERDES performance bump from 15GBPS to 30GBPS

TekStart HMC+ ASIC Controller�Availability

� ASIC Release○ Available Now !○ Support for FPGA Prototyping

�Validated on FPGA platforms supporting HMC � Xilinx Ultrascale EX-850 Pico Computing Board� Altera Stratix-V EX-800 Pico Computing Board

HMC+ ASIC SERDES Support

�HMC+ SERDES Validation� Fully integrated and validated with the target SERDES

� Adds approx. 2-3 weeks to the delivery schedule� Licensing options available upon request

�Support & Maintenance� TekStart provides full support for the controller or the integrated controller/SERDES solution

� SERDES vendor collaboration ensures all customer questions are addressed

HMC+ ASIC Controller Deliverables

�HMC+ Controller Core� RTL Source Code� Integration with target HMC SERDES � FPGA targeted deliveries available if required

�Memory Test Package Option� RTL Source Code� Memory Test Core� Memory Test Analyzer Core

�Testbench � Self-checking Verilog Source Code

�12 Months Support & Maintenance

HMC+ ASIC Controller Summary

�25-35% Lower Memory Latency �As compared to all other HMC Controllers on the market

�Design dependent�Single Clock Domain Solution�Support for industry standard bus I/Fs

�AXI & OCP�Complete integrated solution�FPGA-proven Design

TEKSTART Overall Summary� TEKSTART is an "adventure capital" firm that provides interim sales, marketing and business development services to start-up companies

� The company was founded in 1997 and headquartered in Palo Alto, CA staffed by a talented team with >100 years business, sales and marketing experience

� Most TEKSTART clients have been from the Enterprise Software, IT Services, Electronic Design Automation (EDA), Semiconductor and Consumer Electronic industries. These markets share the followingcharacteristics:� Complex, highly technical products and services � Major corporate customers (Fortune 500, Global 1000, FTSE 100, Asia Week 1000)

� Long sales cycles with many competitive technical and business hurdles � Multiple levels of decision making, and complex customer-vendor relationships

TekStart Contact Page

www.chip-start.com

TekStart LLC228 Hamilton Avenue 3rd FloorPalo Alto, CA 94301Telephone: +1.650.461.9194Email: [email protected]

Documents

TekStart HMCC Overview 2015-07