Thin Film Technologies for Millimeter-Wave Passives … · Thin Film Technologies for Millimeter-Wave Passives and ... – Congestion of lower frequency bands ... (weapon detection),

Thin Film Technologies for Millimeter-Wave Passives and Antenna Integration

G. Carchon, S. Brebels, A. VasylchenkoIMEC, Kapeldreef 75, B-3001 [email protected]

Geert Carchon, PhDEuMW 2008, Amsterdam 2

Outline

• Introduction– RF Challenges & Millimeter-Wave Applications

• 60GHz Millimeter-Wave IC & Antenna Constraints• Antenna Interface Technology Options

– PCB Technology

– Thin-film Technology with Embedded Passives

– MEMS Technology

• Conclusions


Wireless communicationsSo many applications …

Broadcasting

WLAN

• Mobile handsets• Global positioning systems

• Earth observ. sat.• Fixed and mobile radio services• …

f [GHz]

50402010 30 60 70 80

Long Range Radar (ACC)

Mm-wave imaging

…

Short Range Radar

Large increase in mm-wave applications


Introduction: RF Packaging driversMiniaturisation of RF/mm-wave Electronic Systems

RF packaging needs– Lower Cost

– Further miniaturization: size, thickness

– Solve interconnect/packaging bottleneck

– Higher functionality

– Lower power

Enabling Technologies:– IC-integration: RF-SOC

– High density interconnection and packaging technologies: RF-SIP

- Si interposer technology

- 3D Integration (TSV, embedding)

- Passive Integration (R, L, C, MEMS)

- Reconfigurable Functions (MEMS)


The Chip-Package “Interconnect Gap”

• Improvement in density of standard interconnection and packaging technologies is much slower than the IC trends

IC scaling

Time

Size

sca

ling PCB scaling

Interconnect Gap

Advanced PCB

Laser via


Connecting high density IC’s

PCB•Laminate technology

•Coarse contact pitch :800→300 μm

IC• Peripheral

Pad pitch :100→ 20 μm

• High speed• Cu/low-k

“Interposer”

High densityinterconnect

substrate

IC

InterconnectBoard

Package –“Interposer”


Heterogeneous 3D RF System Integration Examples

10GHz Si-IC embedded in Si interposerPurdue Univ.

Reconstructed WaferInfineon

Flex foil (RF foil, UTCP) laminated in flex PCBIMEC

Autonomous wireless modules - IMEC WL-SiP concept - NXP


Large increase in mm-wave applications

• Main mm-wave applications– High speed data transfer – indoor/outdoor ( 60 GHz, 80 GHz )

– Typical application scenarios

• Fast download of content from devices such as Wireless Digital Cameras, PDAs and Portable Audio Players

• Streaming uncompressed video: Wireless HDMI• Kiosk downloading, Wireless Desktop• Wireless backhaul networks

– Car radar (77 GHz) – long and short range radar

– Imaging (94 GHz)

• Main drivers towards mm-wave– Congestion of lower frequency bands

• Compared to low-GHz frequency bands, mm-wave offers– more bandwidth, less interference– more antenna gain/unit area thanks to small wavelength & antenna scaling

– Cost reduction enabled by

• CMOS technology allows high integration levels & mass production• Advanced packaging technologies for high level SiP integration

– Specific mm-wave properties

• mm-wave allows seeing through fog (ACR), clothes (weapon detection), …


Outline



– PCB Technology


– MEMS Technology

• Conclusions


60 GHz might become an established RF frequency for many applications

• Currently foreseen– Wireless HDMI

– Wireless PC interfaces

– Mobile device sync, upload, download

– more applications can evolve

• Several consortia and standardization efforts are active– IEEE802.15.3c

– ECMA TC48

– IEEE802.11-VHT

– Wireless HD

– CoMPA

– NGmS


Implementation technologies for mm-wave60 GHz application case

• Should be oriented to the mass market– low cost

– low power

– small form factor

• III-V: very fast, very expensive, limited complexity– e.g. IEDM 2007: fT of 600 GHz, 1 THz

• SiGe(:C) BiCMOS (180–130nm): fT/fmax around 200 GHz• Advanced CMOS: fast and compatible with digital

26533545nm

17524565nm14023090nm

fT (GHz)fmax(GHz)

node low power

many 60 GHz publications show:90nm CMOS consumes lesspower than nowadays’ BiCMOS

from IBM VLSI Symp. 2007


Is 90 nm CMOS a viable solution for a 60GHz radio?

• Pros– 60 GHz circuits in 90 nm offer good performance

– 90 nm cheaper than 65, 45, … nm

• Cons– the complexity of the digital modem will demand the most advanced

CMOS technology (= beyond 90 nm)

– the analog and digital baseband part requires very fast transistors

• 90nm implementation will consume (much) more power than e.g. 45nm implementation


Single chip versus multi chip version(RFBW ≥ 1 GHz)

―

dig. BB

ADC, dig. BB

analog baseband (BB) + dig. BB

chip 2 (in “beyond 90nm”) remarkschip 1 (CMOS or BiCMOS)

if respin needed for analog/RF, everything must be redesigned

everything in “beyond 90nm”

chip 1 requires beyond 90nm; high datarate at chip1-chip2 interface

RF (+IF), analog BBincl. ADC

chip 1 also requires beyond 90nm

RF (+ IF),analog BB w/o ADC

output of chip 1 sensitive to interference

RF (+IF)


Beamforming with a multiple antenna phased array system

• Benefits for RX:– Immunity against interfering signals

– SNR improvement

• Benefit for TX: relaxed requirement for POUT of PA– MM-wave CMOS PA has low output power and low efficiency

• Implementations: phase shift in signal path or in LO path

Δφ1

Δφ2

Δφ3


Boundary conditions of beamforming

• Narrowband transceiver: Time delay compensation approximated with phase shift

• Solution for beamforming required that is compact, low power, modular in #antennas

Programmabletimedelay

signalcombination


Antenna & Antenna Interface Problem

System definition

Data rate, range, QoS,Max. output power,

Battery life, Cost & size, Temperature, Lifetime, …

Antenna concept

Antenna type (dipole, patch, Vivaldi, …),

fixed beam/phased array, brick/tile assembly, …

Antenna & Package Technology

Lowcost PCB (FR4, BT, …),μwave PCB (Rogers, …),

LTCC, Thin-film,Antenna on chip, …

Antenna specs

Gain, polarization,bandwidth,

# of beams, …

Package specs

Thermal performanceMechanical performance, Electrical performance, Interconnect density, …

?


Antenna & Antenna Interface Requirements

• Millimeter-wave applications use advanced CMOS & SiGe processes– ICs have high IO density and mechanically fragile low K and ultra low-K back-end

– Module implementation may be SoC or SiP approach

• Antenna & Antenna interface requirements– Must be low cost

– IC needs to be close to the antenna to minimize interconnect losses

– Should solve interconnect bottleneck (small pitch connections)

• Should not pose interconnect reliability problems due to CTE mismatch– Should allow low power solutions

• Low interconnect losses, high efficiency antennas• Better antenna interface performance allows to reduce # on-chip power amplifiers• High density flip-chip connections allow to reduce die size

– Ideally offers a scalable solution

• Scalable to larger arrays• Compatible with SOC and SiP approach (multiple Si die, external PA & switch, …)

– Results in miniature, very thin modules

• Offered by high density integration & 3D technology• Embedded passives providing decoupling close to the IC

– Should solve antenna – IC interference problem

– Should take the heat out of the ICs


Integrated 60 GHz antenna array architecture

• Brick concept– Greater depth (more room for circuits

or thermal management)

– Higher cost but lower yield allowed (replacement of failing devices)

– Compatible with antennas with larger bandwidth (dipole and flared types of elements)

– Weak compatibility with single RF-IC

– Limited scaling for single RF-IC case

• Tile concept– Higher integration density

– Lower cost when high yield can be realised (e.g. wafer level processing)

– Relatively narrow-band antennas (patch and printed dipole)

– Better compatibility with single RF-IC

– Limited scaling for single RF-IC case

Preferred


Integrated planar 60 GHz antenna array

• Why we prefer a low dielectric antenna substrate (air, styrofoam, teflon, quartz, …)– Best bandwidth-efficiency product

– Low surface wave loss and hence a larger scan range

– Problem: have good radiation efficiency & broadband operation @ low cost

Efficiency of square patch antenna Bandwidth of square patch antenna


Patch antennas are narrowband

• How to realize a 20% bandwidth while preserving efficiency?– Stacked patch topology

– Low dielectric substrates

• Homogeneous low–dielectric substrate: – e.g. Rogers Duroid 5880 (epsr=2.2), quartz etc …

• Higher dielectric substrate (e.g. Silicon) with air cavities

[Gauthier G. et al., A 94-GHz Aperture-CoupledMicromachined Microstrip Antenna]


Outline



– PCB Technology


– MEMS Technology

• Conclusions


Antenna design on PCBMany material possibilities

• PCB materials for antenna with high bandwidth-efficiency product require– Low dielectric substrate (εr<4)

– Low dielectric losses (losstangent <0.01)

– Antenna feeding using microstrip lines (substrate height<λ/10)

260 μm0.0083.750 μmNelco *

…

0.0009

0.0027

0.0013

Losstangent@ 10 GHz

337 μm2.2127 μmRogers RT5880

272 μm3.38203 μmRogers RO4003C

289 μm3127 μmRogers RO3003

λ/10 @ 60GHz

εr@ 10 GHz

Minimum substrate height

Substrate

* Dielectric properties are dependent on actual laminate build-up (resin content)


• Single element on Rogers RT5880 @ 61 GHz– Matching

– H-plane radiation pattern Radiation efficiency= 81%

Antenna design on PCBVarious performances


Antenna design on PCBVarious performances

• Slot coupled patch antenna with two stacked patches on Nelco@ 61 GHz– Matching

– H-plane radiation pattern Radiation efficiency= 50%


Interconnect design on PCBDifferent constraints

• Manufacturability of routing layers on PCB materials selected as antenna material– A potential problem is the different thermal expansion of CMOS

chip (CTESi=3 ppm/oC) and the PCB material

6012-15.512-15.5Nelco

48

14

17

CTE y [ppm/oC]

23748Rogers RT5880

4614Rogers RO4003C

2417Rogers RO3003

CTE z [ppm/oC]

CTE x [ppm/oC]

Substrate



• Manufacturability of routing layers on PCB materials selected as antenna material– Not all PCB materials allow manufacturing of 100 um diameter

substrate vias

• minimum via diameter is typically larger than substrate height

50 μmNelco

127 μmRogers RT5880

203 μmRogers RO4003C

127 μmRogers RO3003

Minimum substrate height

Substrate



• Manufacturability of routing layers on PCB materials selected as antenna material– Adding microvia layers could be a solution for realizing smaller

diameter vias. Teflon based materials are however not compatible with standard microvia layers.

NoNelco

YesRogers RT5880

NoRogers RO4003C

YesRogers RO3003

Teflon based ?Substrate


Measurement result on PCB interconnect

• Low loss microstrip interconnections possible– 0.35dB/mm interconnect loss in microvia/core layers

– 0.45dB/mm interconnect loss for CPW

– Better performance possible on Rogers

Prepreg μvia

Core

18 um Cu metallization Plated Au finish6mm line


Outline



– PCB Technology


– MEMS Technology

• Conclusions


Thin Film Integrated Passive Devices (IPD)

• Several Technologies Possible:– Ceramic / Laminate / Thin-film / … -based MCM

• IMEC Thin film MCM-D offers– 8” Wafer-level Processing

– Photo-lithography defined features

• Excellent control over lateral dimensions• High repeatability• High degree of miniaturization

– Thin film deposited resistor & dielectric layers

• High density• High precision, repeatable, small tolerances

– IC design style possible

• Substrate choice– AF45 Glass

• low cost, good RF properties– HR-Si

• thermal advantages• micro-machining (cavities, TSV)

Glass SiPBeyne, ISSCC2004


RF-IPD Technology Multilayer Thin Film with Integrated Passives

• Substrate: glass or HR-Si (8”)

• 3 metal planes : Al / Cu / Cu-Ni-Au

• Coplanar waveguide (CPW) lines– Electroplated Cu : 3-5 μm thick

– Smallest feature size : width/spacing: down to 5 μm / 7.5 μm

• Resistors : TaN (25 Ω/ )

• Capacitors : Ta2O5 (0.75 nF/mm2) & BCB (6.5 pF/ mm2) & interdigital

• Inductors : 0.6 to 80 nH, Q : 30 - 150

• Flip-chip / wirebond interconnections

• Integrated vias on HR-Si

2 m metalμ Ti/Cu 5 m μ BCB

5 m μ BCB3 m metalμ Ti/Cu/Ti

1 m bottom Alμ contact metalTaN- resistor

Ni/Au component layer

700 m substrate

μ Glass 1 m top Alμ contact metal

Ta O capacitor2 5

Main Features


RF-IPD on AF45 Passive Circuits & Demonstrator Modules

31-60GHzCoupler

3-5GHz Balun

5.2GHz BPFilter

30GHz BP Filter

2.45GHzBP Filter

Passives

2.4GHz RF Radio 5.2GHz WLAN Front-End

Modules


1990 1995 2000 2005 2010 2015

Roadmap RF-IPD technology

Ceramic20µm

Glass20µm Glass

10µm GlassHigh-ρ Si

10µm

Laminate20µm Laminate

10µm

3D

Increasing frequency

5µm

High-K caps

Embedded Actives

Integrated RF-MEMS


RF-IPD Technology with Through-Si vias

•RF-IPD with Through Si-Vias–Dimensions :

• Bottom D=100µm• Top D=50µm

–Allows for :• Use of substrate back-side as ground-

plane• Microstrip line configurations

100um HRSi

C R L

Via

Cu/Ni/Au Cu Al

HR-SI RF-IPDwafer (100µm)

SiO2 layer

Metal 1RF-IPD(1µm Al thick)

Polymerlayer

Electroplated Cu layer


RF-IPD on HR-SiSurface passivation improves performance

• Surface passivation oxide-HRSi interface– fixed charges in oxide cause DC dependancy & performance spread

– Ar implantation

• increased performance• lower spread• lower DC-bias dependancy

+30V

+20V-30V-20V

0V

CPW on HR-Siwithout implantation

CPW on HR-Siwith Ar implantation

HRSi

SiO2

Best Student PaperEuMIC 2006


Multiple RF feedthrough optionsCPW to CPW / MS to CPW / Vialess

• CPW to CPW– CPW on BCB 50um/25um

• 0.14dB/mm• Backside CPW probably lower loss

(75um/30um)– <0.1 dB per transition @40GHz

• MS to CPW– MS line

• 0.07dB/mm @ 40GHz– CPW on BCB

• 0.14dB/mm @ 40GHz– ~0.1dB per transition @40GHz

• CPW to MS vialess– Narrowband transition, only for micro/mm-

wave

– Size related to frequency

– <0.1dB per transition @ 40GHz

0.4mm 0.4mm0.3mm

0.5mm 0.5mm0.3mm

400x400um

0.4mm 0.4mm0.3mm


Filters at various frequencies (measurements) demonstrated

Initial measurements – no parylene


RF-IPD on HR-Si Coupled line & cavity filters at 60GHz

• Coupled line filter– 4.2% BW

– 2dB IL

• Cavity filter– 6.4% Bandwidth

– 1.6dB Insertion loss

RL (dB)IL (dB)

Measurement

Simulation


Antenna Design

• Micromachined Si antenna– Allows high radiation efficiency as ultra low loss material is used (air)

– No stacked patches needed to obtain sufficient bandwidth

– BUT: expensive substrate

• HR-Si with air cavity (simulated)– Slot coupling to primary rectangular patch

– 10dB Return loss, Gain 7.1dB

– Backward radiation through coupling slot to active circuits

– Efficiency > 90%


Si Interposer advantages for mm-wave applications

• Si interposer advantages– Solves interconnect bottleneck (compatible with small pitch connections

according to ITRS roadmap)

– Results in low power IC solutions by using

• High efficiency antennas (decoupling interconnect & antenna substrate for larger arrays)

• Lower interconnect losses (reduced pad pitch, higher quality substrate)• Lower IC power (ant. interface improves IC Tx/Rx chain constraints)

– Results in smaller ICs

• Better antenna interface performance allows to reduce # on-chip power amplifiers

• High density flip-chip connections allow to reduce die size– Results in scalable solutions

• Scalable to larger arrays• Compatible with SOC and SiP approach (multiple Si die, external PA &

switch, …)– Results in miniature, very thin modules

• Offered by high density integration & 3D technology• Embedded passives providing decoupling close to the IC


Outline



– PCB Technology


– MEMS Technology

• Conclusions


RF-MEMS

• Possible applications– Adaptive antenna matching

– Phase shifters

– Adaptive antenna

– Micromachined cavities for high Q resonators

• Potentially tunable– Micromachined antennas Slot

coupling

Carrier substrate

GND

Feeding line GND via

SiSiVtune


Mm-wave Hybrid Integration on HR-Si MCM-D

• 0/1-level packaged 3mm 50ΩCPW line

• 0/1-level packaged 3mm 50ΩCPW line with embedded SPST

Cap

4 k .cm SiΩ

MEMS

-40

-30

-20

-10

0

0 20 40 60 80 100

Frequency (GHz)

Ret

urn

Loss

(dB

)

-4

-3

-2

-1

0

Insertion Loss (dB)

-40

-30

-20

-10

0

0 20 40 60 80 100

Frequency (GHz)

Ret

urn

Loss

(dB

)

-4

-3

-2

-1

0

Insertion Loss (dB)

• mm-wave packaging using BCB-bonding


Conclusions

• Large increase in millimeter-wave interest due to– Continued CMOS scaling

– Advanced packaging technology

• Antenna & antenna interface– PCB

• allows high performance antennas & interconnects (low K, low tanδ)• has lower density interconnects, relatively large microvias and limited

passive integration (interconnect bottleneck) (150um pitch FC IO)• low K and low loss PCB <> dense interconnect PCB <> low cost PCB

– Si interposer

• Allows high performance antennas & interconnects• Interconnect bottleneck can be solved, hence, scalable to SoC and SiP

integration• Passive integration for reduced size• Potential cost issues


Acknowledgement

• IMEC thin-film integration team• IMEC assembly team• IMEC antenna design team• IMEC IC design team

• European Space Agency – 3D Microwave module packaging (contract number 19346/05/NL/Sfe)

• 3DμTune– EU 6th FW project number 027768


Documents

Thin Film Technologies for Millimeter-Wave Passives … · Thin Film Technologies for Millimeter-Wave Passives and ... – Congestion of lower frequency bands ... (weapon detection),