1

LCD TV 及 HDTV 整合方案

PY TsaiJan 2007

2

HDMI Switch

TMDS341

Video BufferTHS7353

Tuner

HDMIReceiver

ADC LVDS

Scaler

Lip Sync Delay TPA5050/ 51/52

Audio DACPCM1754

Audio AmpTPA3120D2TPA3100D2

I2S

Analog

I2S

PFCUCC28051UC2853A

Green Mode Cont.UCC28600

AC24V12V5V

DC-DC ConverterTPS54383/54386TPS54283/54286

4.5V ~ 28V

3.3v

EN

TPS2041/2051

Control ASIC

Video

ACDC/DCDC

Card Reader Power

Audio

TMDS141HDMI Side connector

Panel

1M Twist Cable

HDMI

Ti Solutions for LCD TV

3

CAN TunerTVP9900VSB/QAMDe-mod

Cable

Antenna

IFTS

ATSC Add On Module

Ti solution for ATSC

TV Mother Board

Mainchip

3 ADC3D Video DecoderAudio

Decoder

YPbPr16/24BitYUV

Scaler De-Interlace

MCU

I2C/RS232

TVP9000

De-MUX MPEG2DecoderAC3

Decoder

CPUVideoProcDAC

L/RAudio SIF CVBS

4

TVP9000 – Digital TV Processor

High Definition and Standard Definition MPEG-2 Video Decoder –supports all ATSC DTV formatsAudio Decoder: Dolby AC-3, MPEG-1/MPEG-2 Layer I and IIDisplay Format Conversions: 3D deinterlacing, Scaling, Gamma CorrectionVideo Outputs Supported: • 480i, 480p, 720p, 1080i• Common display resolutions (max: 1366x768)

CableCard Support SmartCard/Common InterfaceNTSC/PAL Video EncoderDDR Memory InterfaceUART interfaces, IR input/output ports, OSD, S/PDIF Output, and picture controlsIntegrated Arm9 CPU

5

TVP9900 – VSB/QAM De-ModTSC 8-VSB Demodulation and FEC

ITU-J.83B compliant 64/256 QAM demodulation and FEC

Direct 44MHz IF input

Integrated digital filter relaxes external tuner filters

Integrated high-speed 10-bit AD converter

Full digital clock and carrier recovery

Sigma-Delta DAC for AGC control

Direct tuner control interface

EIA/CEA-909 antenna control interface

On-chip ARM7 32 bit RISC microprocessor

6

Equalizer covers echo profile required ATSC A.74 guideline

Superior multipath performance demodulating all Brazil ensembles

Cost-effective solution targeted for low-cost DTV receivers

Integrated solution minimizes system cost

• 4MHz clock input driven by MOP IC in the tuner saves a quartz crystal for demodulator.

• Integrated high speed ADC and Digital adjacent filter potentially reduce one or two external SAW filter and IF amplifier.

• External DAC and VCXO for clock recovery not required.

• Direct IF sampling eliminates external downconverter.

TVP9900 – VSB/QAM De-Mod

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HDMI Switch and Repeater

TMDS341TMDS141

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HDMI Configuration

9

TM

DS141

TMDS341A

HDMI Connectors Configuration

10

Digital Interface and Major Vendors

EDIDDDC (I2C 100KHz)

DigitalT.M.D.S.

DVIHDMI

Tx(HDCP)

DVIHDMI

Rx(HDCP)

+5V

Hot Plug Detect

CEC

DVI HDMI

DV

I/ H

DM

Icon

nect

ors

DV

I/ H

DM

Icon

nect

ors

TI DVI Tx/Rx : TFP513 and TFP503

HDMI Tx/Rx : Silicon Image, Philips, Mstar, ADI

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HDMI A-type Connector Pin Definition

高速信號組

低速控制信號組

狀態信號組

18+5V

16SDA

14NC

12C-

10C+

8shield

6D1-

4D1+

2shield

19HPD

17GND

15SCL

13CEC

11shield

9D0-

7D0+

5shield

3D2-

1D2+ 3.3V Differential Signal

TMDS 1.65Gbps

DDC (Digital Display Control) : 5V I2C Control Line 100KHz

CEC (Consumer Electronic Control) : 3.3V High-level Control 1KHz

+5V : 5V SignalHPD (Hot Plug Detect): 5V TTL 訊號

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HDMI Basic Operation

Hot Plug DetectH

DM

I con

nect

ors

HD

MI c

onne

ctor

s

Source Display

Connection Building Process

1. When Source is ON +5V = HIGH2. Display’s E-EDID is Ready HPD=HIGH

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+5V

13

HDMI Basic Operation

EDIDDDC

+5V

Hot Plug DetectH

DM

I con

nect

ors

HD

MI c

onne

ctor

s

12

3

Transmit Display Setting

3. Source read EDID (display setting) from Display via DDC

Source Display

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HDMI Basic Operation

EDIDDDC

TMDSHDMI

Tx(HDCP)

HDMIRx

(HDCP)

+5V

Hot Plug DetectH

DM

I con

nect

ors

HD

MI c

onne

ctor

s

12

34a. Source and Display exchange HDCP Golden Key through DDC 4b. Source transmit media signal via TMDS channels

4a 4a

4b

Source Display

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FET-SWITCH Buffered-SWITCHInput EQ=8dBOutput DE=0dB

Buffered-SWITCHInput EQ=8dBOutput DE=3dB

DUTHDMI Cable 1 HDMI Cable 2

Agilent 812503.35GHz VXI

systemTektronix TDS7404

oscilloscope5m 28AWG 1m 28AWG

觀測點

Eye Diagrams @ 1.65Gbps

TI CONFIDENTIAL

16

FET-SWITCH Buffered-SWITCHInput EQ=8dBOutput DE=0dB

Buffered-SWITCHInput EQ=8dBOutput DE=3dB

DUTHDMI Cable 1 HDMI Cable 2

Agilent 812503.35GHz VXI

systemTektronix TDS7404

oscilloscope10m 30AWG 1m 28AWG

觀測點

Eye Diagrams @ 1.65Gbps

TI CONFIDENTIAL

17

HPD outputs are 3.3V TTL drive

SCL/SDA and pins are 5V tolerant

HPD_SINK inputs are 5V tolerant

SCL_SINK/SDA_SINK pins are 5V tolerant

TMDS inputsStandard TMDS terminations are integratedInput equalization circuits allow 5m or longer cable lengthsAC-coupled inputs

TMDS outputsSupport 1.65Gbps data rateVSadj pin adjust Vod to meet TMDS voltage swingOutputs are high impedance when OEB is HIGHSelectable de-emphasis (PRE) allows pre-conditioning losses of interconnections

A24B24

A23B23

A22B22

A21B21

HPD1HPD2HPD3

SCL1SDA1

SCL2SDA2

SCL3SDA3

SCL_SINKSDA_SINK

HPD_SINK

Y4

Z4

Y3

Z3

Y2

Z2

Y1

Z1

S1S2S3

ControlLogic

Vcc (3.3V)

RINT

RXw/EQ

Vcc

RXw/EQ

Vcc

RXw/EQ

Vcc

RXw/EQ

RINT

RINT

RINT

A34B34

A33B33

A32B32

A31B31

PRE

VSadj

Vcc (3.3V)

RINT

RXw/EQ

Vcc

RXw/EQ

Vcc

RXw/EQ

Vcc

RXw/EQ

RINT

RINT

RINT

OEB

TMDSDriver

TMDSDriver

TMDSDriver

TMDSDriver

3-to-1MUX

. . .

TMDS341A Key Features

All pins 4kV & TMDS inputs 5kVHBM ESD protection80-pin TQFP package

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Signal Decline When Transmission

NormalTransmitter

Receiver underheavy loss

• High-frequency signal decline more than low-frequency signal –> because conductor need time to absorb and release energy.

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Internal signalafterequalization

Boost highfrequencycontent

• Re-judge the signal level by using equalizer

Input Equalization

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TMDS341A is an one chip solutionTMDS and DDC are flow-throughWithout vias

TMDS341 Layout Example

21

TMDS141HDMI Hider

TI CONFIDENTIAL

22

De-emphasisTransmitter

Receiver underheavy loss

• Change signal’s amplitude in advance -> to offset the interconnect loss when transmission in high frequency.

Pre-Emphasis When Output

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Cables (28AWG):•Amphenol Spectra-Strip:

168-2832-20 Shielded•Belden:

8138 Shielded•Amphenol Spectra-Strip:

132-2801-016 No Shield

Connectors:•DF14-25p-1.25H

TMDS141 Cable Test Report

TMDS141 Driving TMDS341 with Cheap cable

Gen

141 EVM

341 EVM5m HDMI

1m 3M flat ribbon

With pre-emphasisNo pre-emphasis

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Video Amp/ Mux

THS7353THS7316

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Common Video Characteristics

SR = 2 Pi Vpk (1Vpk) x 0.707 (-3dB) x 2 (to ensure no problems)

Format Standard / Display Resolution

Signal Element

Analog Bandwidth

(MHz)

Ideal Min. SR

(V/us)

H. Sync Width (us)

Max. Video Amplitude

(Vpp) CVBS CVBS 4.2* ;

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DAC Reconstruction / ADC Anti-Aliasing

Aliasing / Images• All ADC’s and DAC’s have images !!!• Sampling artifacts at n*fs on Both Sides • Remove Images with Analog Low Pass

Filter• Must have good Group Delay

Response

DAC and ADC Performance• Resolution?• (Over-) sampling frequency?• DAC Sin X/X Roll-Off

Sin X/X Roll-Off

13.5-MHz Sampling Frequency

Analog LPF Analog LPF ResponseResponse

27-MHz Sampling Frequency w/SDTV Signal

Data Converter Images

LPF Eliminates LPF Eliminates DAC and ADC DAC and ADC

ImagesImages

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Traditional Fix Filter Traditional Fix Filter

Selectable Filter BW Selectable Filter BW

SDTVSDTV

EDTVEDTV

HDTVHDTV

frequencyNoise/DAC ImageNoise/DAC Image

NoiseNoise frequency

frequencyFilter BW

SDTVSDTV

EDTVEDTV

HDTVHDTV

Noise/DAC ImageNoise/DAC Image

NoiseNoise

Filter BW

frequency

frequency

frequency

Filter Filter ResponseResponse

Filter Filter ResponseResponse

Analog Video Filtering

f1 f3f2

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Video Amp – Loading and Configuration

LoadingLoading

OP ConfigurationOP Configuration

Input BufferThe loading is usually from Video ADC. 5pF + 10kohm in parallelRs is for OP stabilization (optional)

As an Output Buffer As an Input Buffer

Output BufferThe loading is usually depends on the terminator and the cable. (~150ohm)

Out75

75

Input BufferGain = 1Some OP with gain adjust pin for cable skin effect loss compensation (THS7353)

Output BufferGain = 2 (Sometimes More)

As an Input BufferAs an Output Buffer

Out75

75

-

+

R

R -

+1uF

DC Clamp

DVD Player

In 0.1uF

TV

10kohm

Video ADC

5pF

Rs

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Video Amplifier – Signal Bias

DC Modes

AC Modes

DC

DC+SHIFT

ACSTC

ACBIAS

1.65V3.3V

AC BIAS

AC Sync Tip Clamp

250mV0V

DC + Level Shift

250mV0V

DC

0V

Make Sure Input Signal is >50mV or Output Clipping May Occur

Allows Input Signal to go to 0V without Output Clipping Problems

3.3V

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LDOLDO

Competitor Competitor

TI TI

5V I/P3.3V O/P Digital Core Digital Core

ProcessorProcessor

THS7303

3.3V I/PDigital Core Digital Core

ProcessorProcessor

High VCCMore heat consumptionHigher temperature, lower long term reliabilityExtra power management IC neededViolate Energy Star/Green Policy regulation of STB

Low VCC CapabilityLess heatBetter reliabilitySave the needs of LDOEnergy saving

Note : Built-in Charge Pump Solutions = NOISE

Low Supply Rail

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THS7353 SDTV/EDTV/HDTV/RGB Input Buffer w/2:1 MUX

Features• 2:1 Input MUX• Selectable 5-Pole Low Pass Filter :

– 9-MHz (480i/576i/NTSC/PAL)– 16-MHz (480p/576p/VGA)– 35-MHz (720p/1080i/SVGA/XGA)– Bypass (1080p/SXGA/UXGA) 150MHz, 300V/us

• 2.7V to 5V operation• External Resistor to Fine Tune Gain or Frequency

Compensation for Cable Losses• Mute Function• Selectable Input : DC / DC + 250mV / AC -Internal

Bias / AC - Sync Tip Clamp• I2C Control with 4 Selectable Addresses• 20-pin TSSOP Package – Lead Free (RoHS)• 16.2-mA Total IQ Current (54mW @ 3.3V)•

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TIV7316: 3-Ch. HDTV Output Video Buffer with 5th-Order LPF

Features (Target Specs)•• LOW COSTLOW COST - Budgetary Pricing = $0.70 @ 1ku$0.70 @ 1ku• 3V to 5V operation• 5-Pole Butterworth Low Pass Filter @ 36-MHz• Input Allows DC Coupling with Internal Level

Shifter• Input also has Transparent STC / DC Restore

for AC Coupled Applications if Desired• Fixed +6dB Gain • 18-mA Total Quiescent Current (60mW @ 3.3V) • Rail-to-Rail Output – DC or AC Coupled• VICR Includes Ground• SOIC-8 package – Lead Free (RoHS) and Green• Improved Replacement for FMS6363

Applications• Set-Top-Box DAC Output Buffering• DVDR / PVR DAC Output Buffering• Low Power for Portable / USB Powered Systems

SOIC-8

Channel 1Input

5-Pole36-MHz

LPF

Channel 2Input

Channel 3Input

+2.7V to +5V

Channel 1Output6dB

+-

+Vs

Sync-Tip Clamp

(DC Restore)

gm

+140-mVLevel Shift

800k

5-Pole36-MHz

LPF 6dB

+-

+Vs

Sync-Tip Clamp

(DC Restore)

gm

+140-mVLevel Shift

800k

5-Pole36-MHz

LPF 6dB

+-

+Vs

Sync-Tip Clamp

(DC Restore)

gm

+140-mVLevel Shift

800k

Channel 2Output

Channel 3Output

34

Power Solution

TPS54383 (3A, 300KHz)TPS54386 (3A, 600KHz)TPS54283 (2A, 300KHz)TPS54286 (2A, 600KHz)

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TPS54383/386 Key Features• VIN 4.5V to 28V• Internally set switching frequency

– TPS54386= 600kHz– TPS54383= 300kHz

• ~ 85 mOhm Integrated High Side FET• 0.8V 1.5% Reference• Ch 1 Internally Set Current Limit (~4.2A)• Ch 2 Three Selectable Current Limits

~(4.2A, 2.9A, 1.7A)• Internal 2.2ms Soft Start• Thermal Shutdown at 145ºC• Current Mode Control

– Sense FET Implementation• Internal Slope Compensation• Pulse by Pulse Over-Current Protection• Output UV Detection with Hiccup Restart

from Over-Current Faults• Built in single pin sequencing options• Vout1 180º out of phase with Vout2• 14 lead TSSOP PowerPADTM packaging• Power consumption: ~0.318W/Ch

TPS54386 Efficiency 600kHz at VIN = 12V

60.0

70.0

80.0

90.0

100.0

0 0.5 1 1.5 2 2.5 3 3.5Iout, A

Effic

ienc

y, %

(5.03V)(3.32V)

36

TPS54383/386 Key Features

37

Audio Design in Digital TV

TPA3100D2TPA3120D2PCM1754

38

TPA3100D2 20W Stereo Class-D

• Eliminates need for heat sink• Eliminates need for DC-DC converter;

operates from 24V LCD backlight supply

• Eliminates four external resistors• Excellent reliability and robust

operation• Allows processor to reset the device

after an over current event

• Efficient Class-D operation• Wide 10V to 26V supply voltage

Operation• Four integrated gain settings• Thermal and short circuit

protection• Fault reporting

Tuner StereoClass-D Amp

7x7 QFN, SMT Package

48pin QFN 7mmx7mm

39

TPA3120D2

• Eliminates external heat sink• High output power from standard supply• Eliminates need for DC-DC converter;

operates from 24V LCD backlight supply• Eliminates 1 LC filter• Excellent reliability and robust operation• No audible clicks and pops • SMT and thru-hole packaging

• Up to 90% Efficient Class-D operation (4-Ω)• 20W, 4-Ω, 24V (THD+N=10%)• Wide 10V to 30V supply voltage

operation• Single-ended output • Thermal and short circuit protection• Popless startup/shutdown• Small, 24-pin TSSOP, 20-pin DIP package

• CRT, DLP-TV, LCD-TV and PDP

Tuner

40

PCM1753/54/55 Stereo DAC

Cost Effective 24-bit 106dB Stereo Audio DACFeatures

PCM1753: PCM1742/48 compatiblePCM1754: Hardware controlPCM1755: Open drain zero flagDynamic Range: 106dB TypTHD+N: 0.002% TypFull-Scale Output: 4.0Vp-p TypSampling Frequency: 32k - 192kHzSystem clock: up to 1152fsSingle power supply operation :

+5V for Analog and Digital5V tolerant Digital input16 pin SSOP Package

BCK

DATA

LRCK

DGND

NC

Vcc

Vout L

Vout R

SCK

ML

MC

MD

ZERO L / NA

ZERO R / ZERO A

Vcom

AGND

PCM1753 / PCM1755

41

Lip Sync Delay IC

TPA5050/51/52

42

TPA5050/5051/5052Digital Audio “Lip Sync” Delay IC

4x4 QFN

• 16-24-bit I2S Input (fs = 32kHz-192kHz), Right-Justified, Left-Justified Audio Formats• 2-ch,170ms/ch@48kHz Programmable Delay: TPA5050• 4-ch,85ms/ch@48kHz Programmable Delay: TPA5051• I2C Bus Delay Control: TPA5050, TPA5051• Hardware Delay Control: TPA5052• Cascadable for Longer Delay Time• SMT, 4mm x 4mm, 16-pin QFN

• Supports all standard audio formats • Compatible with all standard bit clock rates• >100ms of delay optimized for 2-channel system• 4-ch option available for second audio source (PIP)• Allows fine adjustment (1 sample resolution)• No software support required • Add more devices if needed• Smallest solution size in market

• DLP-TV, LCD-TV and Plasma Displays

43

Total Solution from TICategory Product Focus Device

Video Video Decoder TVP5146/TVP5147/TVP5160

VSB/QAM Demodulator TVP9900

HDMI Switch TMDS341

HDMI Repeater TMDS141

Video Buffer/ Mux THS7353/THS7316

Audio Audio Amp TPA3100D2, TPA3120D2

Audio DAC, ADC PCM1754/PCM1801

Lip Sync Delay IC TPA5050/5051/5052

Power DCDC TPS5438x/TPS5428x

Card Reader Power Switch TPS2041/ TPS2051

PFC UCC28051/UC2853A

Green Mode Controller UCC28600

TVP9000 – Digital TV Processor HDMI Switch and Repeater� �TMDS341�TMDS141HDMI A-type Connector Pin DefinitionHDMI Basic OperationHDMI Basic OperationHDMI Basic OperationSignal Decline When TransmissionInput EqualizationPre-Emphasis When OutputTMDS141 Driving TMDS341 with Cheap cableVideo Amp/ MuxCommon Video CharacteristicsDAC Reconstruction / ADC Anti-AliasingPower Solution��TPS54383 (3A, 300KHz)�TPS54386 (3A, 600KHz)�TPS54283 (2A, 300KHz)�TPS54286 (2A, 600KHz)�TPS54383/386 Key FeaturesTPS54383/386 Key FeaturesAudio Design in Digital TVTPA3100D2 20W Stereo Class-DTPA3120D2PCM1753/54/55 Stereo DACLip Sync Delay ICTPA5050/5051/5052�Digital Audio “Lip Sync” Delay ICTotal Solution from TI