Trend towards the design of embedded DC–DC converters

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Published in IET Power ElectronicsReceived on 26th July 2011Revised on 4th November 2012Accepted on 30th November 2012doi: 10.1049/iet-pel.2011.0277

T Power Electron., 2013, Vol. 6, Iss. 8, pp. 1563–1574oi: 10.1049/iet-pel.2011.0277

ISSN 1755-4535

Trend towards the design of embeddedDC–DC convertersKaushik Bhattacharyya

Analog and Mixed Signal Division, Applied Micro Circuits India Pvt. Ltd., Bangalore-560103, Bangalore, India

E-mail: [email protected]

Abstract: These days, embedded DC–DC converters are paying a remarkable attention to the research and consumer domain. Theconcept is basically conceived into the need of miniaturised, lightweight, highly power dense solution. This study surveys theDC–DC converters aiming towards the trend of design of embedded converters. Starting from the conventional inductor-based converters to the present trend of design of embedded DC–DC converters are discussed here. Here, all the issues whichmay play important role during the design of above converters are elaborated and possible remedies to mitigate the issues toachieve the better performance are also illustrated. A brief idea towards the possible future research direction on embeddedconverters is also discussed here.

1 Introduction

Power supply and power management units are the mostfundamental and indispensable components found in anyintegrated circuit (IC). The supply voltage needs to bestable, constant and accurate to ensure proper operation ofthe analogue, digital and mixed signal circuits in the IC.Such stable voltages are obtained from the powermanagement unit, which is powered from the main inputsupply like a battery or an AC−DC regulator.The power management circuit does the job of conversion

of the input voltage level to the desired level and alsomaintains its output level independent of the load currentand input fluctuations. There is a constant endeavour tobuild a highly power-efficient converter with smaller insize, low weight with high-power density. Low-voltagepower converters are indispensable to develop handhelddevices [1]. With the progress of technology the requiredinternal supply voltage is continuously decreasing. This ismainly to reduce the dynamic power loss of a system inquadratic manner (CVdd

2 ) [2]. In these portable systems,DC–DC voltage conversion is required to generate differentvoltage levels from a single external battery source. Hencethe DC–DC converter is actually intermediate module ofthe battery and the core circuits. The core circuits aretreated as load for the converter.Efficiency (η) is an important performance metric of a

converter. High efficiency conversion helps to increase thelife time of the battery. It is basically the ratio of the outputpower delivered to the load to the total amount of powerdrawn from the input supply. The efficiency term isgenerally expressed in percentage. If IL and Vout are the loadcurrent and the output voltage and Vin and Isup are the inputsupply voltage and the supply current drawn by a converter

then the power efficiency, η can be expressed as below

h = Vout ILVin Isup

× 100% (1)

Supply current, Isup corresponds to the sum of the currentdrawn for faithful functioning of the converter. It alsoincludes different type of power losses.Normally, there are two major components of power losses

in the switching transistors of a converter viz., conductionloss and dynamic loss. The conduction loss is due to thefinite on-resistance of the switching transistor in its linearregion of operation. Where the on-resistance is given by

R = L

mCoxW VGS − Vth

( ) (2)

where µ is mobility, Cox is the oxide capacitance per unit area,W is the width of the transistor, L is the length of thetransistor, VGS is the gate-to-source voltage and Vth is thethreshold voltage of the transistor. The conduction loss pertransistor is given by

Conduction loss = RI2tx (3)

= L

mCoxW VGS − Vth

∣∣ ∣∣ I2tx (4)

Here, Itx is the current through the transistor and R is theequivalent resistance of the channel.Now, considering the dynamic loss because of the charging

and discharging of parasitic gate capacitance of a switchtransistor, the loss per transistor at the switching frequency f

1563& The Institution of Engineering and Technology 2013

Fig. 1 Basic schematic of inductor-based buck converter

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is given by
CgV2ddf = wLCoxV

2ddf (5)

The reduced voltage swing may reduce the dynamic powerloss and thereby the power efficiency can be increased. Inaddition to the reduction of switching power loss, the lowswing control signals help to use smaller switches [3].It may be observed from the (4) and (5) that the conduction

loss is inversely proportional to the width of the transistor,whereas the dynamic loss is directly proportional to thewidth of the transistor. Hence, there exists a tradeoffbetween dynamic loss and conduction loss.There is another type of loss named by ‘Bottom Plate

Parasitic Loss’ [4] may play an important role in on-chipswitched capacitor-based converters. This loss can bereduced by using p-channel metal-oxide semiconductor(PMOS) device to realise on-chip flying and load capacitorsand proper biasing of bulk terminal [5].Based on the basic requirement of DC–DC voltage

conversions, there are mainly two classes of converters.One class is used for stepping up the voltage level and theother class of converter is for stepping down the inputsupply voltage. The DC–DC converter which does thestep-down job is popularly known as ‘buck converter’whereas the other one is widely called as ‘boost converter’.Based on implementation there are three major categoriesof step-down DC–DC converters viz., inductor-based,switched capacitor-based and linear regulator.Inductor-based converters are obvious choice to provide

high-power efficiency but the presence of inductor makesthe converter bulky and noisy. On the other hand linearregulators are compact, on-chip implementation is alsopossible and output voltage is free from ripple butlow-power efficiency prevents the regulators to use inpower efficient application.Looking at the pros and cons of the usually available

converters the present trend is to design embedded DC–DCconverters, where all the components are located within adie. As a result, it may miniaturise the board size but thereare lot of issues automatically come into the picture todegrade the performance metrics of the embedded converters.This paper reviews the different type of available DC–DC

converter topologies by targeting towards the design ofembedded DC–DC converters. All the notable topologies ofDC–DC converter starting from the bulky inductor-basedconverters to dynamically reconfigurable embedded DC–DC converters are discussed here. The problems to designan embedded DC–DC converter are mentioned in the paperand the possible solutions are also elaborated. Followed bythe Introduction the available DC–DC converters aresurveyed in the Section 2. Section 3 is dedicated toelaborate the survey and design of embedded DC–DCconverters. An outline of the future research work isprovided in Section 4. Finally, Section 5 followed by thereferences concludes the paper.

2 DC–DC converters

The development of the monolithic regulators started in thelate 1960 [6]. Thereafter a considerable effort has beenmade for the improvement of their performance metrics viz.,power efficiency, output voltage ripple, supply and loadregulations etc. It is already mentioned that there are threemajor categories of step-down DC–DC converters viz.,


inductor-based, switched capacitor-based and linear regulatorare available. These are described in the following sections.

2.1 Inductor-based DC–DC converter

Inductor-based converter is the first choice to make a highlyefficient buck converter. Basic schematic of inductor-basedbuck converter [7, 8] is shown in Fig. 1. There are twocomplementary switches, S1 and S2, which are turn on andoff depending on the state of the given input pulse to theswitches. The inductor L and capacitor CL basically form alow-pass filter. The input supply voltage, Vin is chopped byS1 and S2 and produces a rectangular voltage havingaverage level of the defined output voltage. Thesecond-order low-pass filter comprised of L and CL passesthe DC voltage to the load. The duty cycle of therectangular input pulse to the switches actually determinesthe average output level. There may be severalarrangements of switches and filter components to producedifferent output voltages, which may be lower or higher andsame or opposite in polarity with respect to the inputsupply voltage. For achieving > 95% of power efficiency atheavy load (i.e. maximum load current) and light load (i.e.minimum load current) condition, different control schemesviz., pulse width modulation (PWM) and pulse frequencymodulation (PFM) are used, respectively. The width of theon or off time of a pulse is varied in PWM mode ofoperation whereas the period of the clock pulse is fixed. Onthe other hand, the frequency of the clock pulse in PFMmode can be scaled by keeping the duty ratio remainedfixed. In this mode, when the output voltage falls below thereference voltage the power PMOS device is turned on tocharge the filter capacitor and the n-channel metal-oxidesemiconductor power device is turned on for a short periodof time after turning off the PMOS device to discharge theinductor [9].It is observed that PWM is usually advantageous in terms

of good regulation and power efficiency when the converteris in heavy load of operation whereas using the PFMtechnique is beneficial in light load of operation [10]. Onemajor drawback of PFM control is that the switching period(the time between charge bursts) is a function of load.Thus, the converter appears almost chaotic and theswitching noise is unpredictable. However, PFM mode canbe cleverly used during the periods of inactivity [11].The TPS43000 IC is basically a high-frequency,

voltage-mode, synchronous PWM controller which can beflexibly used for buck, boost and buck–boost etc.topologies. A high efficiency, low-voltage synchronousbuck converter is designed with the use of above mentionedcontroller. The converter can step-down the 3.3 V of mainsupply to 1.2 V of regulated output voltage with the powerefficiency of > 90% and nominal load current of 3 A. Theoff-chip passive components of 3.3 µH of inductance and 2V/180 µF of output capacitor are used there [12].

IET Power Electron., 2013, Vol. 6, Iss. 8, pp. 1563–1574doi: 10.1049/iet-pel.2011.0277

Fig. 2 Basic schematic of linear regulator

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In this context, a point to be added that there are different
parameter sensing techniques in the different modes ofcontrol are evolved. Forghani-zadeh et al. [13] hadreviewed six available current-sensing techniques and theyalso introduced a new scheme to measure the current moreaccurately. Fai Lee and Mok had introduced a monolithiccurrent-mode complementary metal oxide semiconductor(CMOS) DC–DC converter with integrated power switchesand a new on-chip current-sensing technique for feedbackcontrol. The sensed inductor current, which is combinedwith the internal ramp signal, can be used for current-modeDC–DC converter feedback control with the help ofproposed scheme. In addition, Fai Lee and Mok [14] hadimplemented the scheme without any extra input/output pinfor current-mode controller. Chang and Chang [15] hadachieved 98.2% accuracy of current-sensing whereas thecore circuit power loss is within 90 mW.The research in multiphase voltage regulator module

(VRM) to provide load current with higher rating is alsobeing advanced forward. Dancy et al. [16] had designed ahigh efficiency multiple output DC–DC converter, wherethe key features of that design are its low-power dissipationand re-configurability. Peterchev et al. [17] had developedPWM architecture in multiphase VRM. The power losseswhich are incurred by the different ways at the timeof operation of the buck converter are modelled by Zhouand Rincon-Mora [18]. Different techniques have beenmathematically formulated and implemented to minimisethose losses there. Kursun et al. [19] proposed low-voltageswing metal-oxide semiconductor field-effect transistortechnique to enhance the power efficiency of high-frequency switching DC–DC converter.However, the main disadvantage of the inductor-based

buck converters is the presence of their off-chip inductors.It makes the converter bulky and noisy. It also increasesthe board size. An effort is given to bring the inductorwithin the chip by Makharia and Rincon-Mora [20] butlow-quality factor (Q) value of the inductor limits it on-chipimplementation. There the efficiency is deteriorated becauseof high parasitic resistance and the skin effect in theinductor windings and the parasitic capacitance towards thesilicon substrate [21].There are some techniques to reduce the electromagnetic

interference (EMI) of the inductor [22]. Alarcon andcoworkers [23] had designed a three-level buck converter. Itoffers reduced size of magnetic components, fewer amountsof switching ripple and switching losses in comparison withany standard or two-level buck converter, but still the sizeof the inductor is high which restricts to embed the entiremodule within the chip. On the other hand, on-chip,inductor-less and power-efficient DC–DC converter withlow-output voltage ripple applicable for the analogue-embedded applications is in high demand particularly inbattery-operated compact system. Further miniaturisation ofthe converter is a challenging research item to embed itwithin its application chip. The obvious advantages of suchembedded converters are reduced size, weight and low EMI.

2.2 Linear regulator

Another option of on-chip voltage conversion is throughlinear regulator with zero output voltage ripple andcapability of on-chip implementation. The basic schematicof linear regulator is depicted in Fig. 2. It is made of anerror amplifier followed by a pass transistor. The mainsupply voltage Vin is stepped down to the specified output


voltage of the regulator, Vout. The output voltage, Vout iscompared with the reference voltage Vref by the erroramplifier and the corresponding error voltage at the outputdetermines the amount of current flow through the device,MPass which basically act as the ‘mother’ of all currentsources. The difference of voltage in between Vin and Vout

is actually called as the ‘dropout’ voltage of the amplifier.A fast dynamic response can also be provided by thisregulator [24]. These features make linear regulator suitablefor analogue and embedded application. den Besten andNauta [25] developed a 5 V to 3.3 V linear regulator, whichcan supply > 200 mA of current whereas the output withina margin of 10% of its nominal value. There was anattempt by Ahmadi et al. [26] to develop a linear regulatorin 0.18 μm CMOS process. Linear Technology’s LT1580IC can deliver maximum 3 A of current at 1.3 V ofregulated supply voltage from the 1.8 V of main inputsupply at the cost of 100 µF of off-chip load capacitor [27].The power efficiency is high for a low dropout (LDO)

regulator, where the difference between an input and thecorresponding output voltage is very small. The TexasInstrument’s TPS728xx series IC of LDO linear regulators,with a selectable dual-voltage level output, is designedespecially for applications that require two levels of outputvoltage regulation. The available fixed output voltages arefrom 0.9 to 3.6 V. It can provide 200 mA of load currentwith the use of 1 µF of load capacitor [28]. Endoh et al.[29] have used a flexible control technique to improve thecurrent efficiency of the linear regulator and thereby thepower efficiency at light load condition is improved.Frequency compensation strategy for an error amplifier in

particular type of linear regulator is also a challenging task.Leung et al. [30] had developed a capacitor-free CMOSLDO for system on-chip application to reduce the boardarea and the number of pin counts. A robust frequencycompensation strategy is demonstrated by Chava andSilva-Martinez [31], where the authors generated a ‘zero’internally rather than depending on the zero developed bythe load capacitor. Fan et al. [32] have also contributedin the compensation of LDO with a motivation for researchon high-gain wide-bandwidth amplifiers driving largecapacitive loads.However, the power efficiency of the regulator reduces

linearly with the increase of input and output voltagedifference. This becomes a major concern for battery-operated system, where the battery voltage remains same


Fig. 3 Schematic of an n-stage switched capacitor-based buckconverter [36]

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whereas the required internal voltage reduces with progress ofIC fabrication technology.Looking into the need of embedded power management

unit, a new era of switch capacitor-based converters isemerged for overcoming the drawbacks of inductor-basedconverters [33, 34]. These types of converter topologiesmay be meaningful to achieve high-power efficiency. Theyalso possess the advantage of reduced size and weight. Onecan also reduce EMI in an embedded switched capacitor-based converter by using interleaving configuration withappropriate interleaving time [35, 36]. The necessarydiscussions on the operation of the switched capacitorconverters are given in the following section.

Fig. 4 Phases of the control signals of the mentioned converter inthe Fig. 3 [36]

2.3 Switched capacitor-based DC–DC converter

Capacitive converters have been in use for a long time [37].Here, the basic idea is to use switches and capacitors forcontrolling the energy transfer. Monolithic integration is alsopossible through it. The basic schematic of the switchedcapacitor-based buck converter and the corresponding statesof the control signals and the different node voltage across thecapacitors are shown in Figs. 3 and 4, respectively. Whenthe switches S1 and SD1–SDn− 1 are closed the capacitorsare charged in series from the main power supply, Vin. Onthe other cycle the aforementioned switches are off and theremaining switches are turned on and the stored charge isdelivered to the load through S2. The switches and capacitorscan be arranged in different fashions depending on thestep-down fractions needed from the main input supply.There is an inductor-less DC–DC converter which uses the

flying capacitors of 1 µF can step-down the input supplyvoltage from 2.4–6 V to constant 1.8 V with the feature of82.9% of peak power efficiency and up to 100 mA of loadcurrent driving capability. There, the output voltage rippleis reduced to 25 mV with the help of 10 µF of loadcapacitor [38]. National Semiconductor’s LM2771 chip can

Table 1 Comparison table of the conventional converter topologies

Convertertopologies

Passive compone

Input andoutputvoltage

Inductorsize

Capacitor size M

inductor-based[42]

input:3–5 Voutput:1–0.2 V

10 µH(off-chip)

22 µF (off-chip)

switchedcapacitor-based[43]

input:2.5–5 Voutput:3.6 V

notneeded

1 µF of each ofthe flying andload capacitors

(off-chip)

16s

8.3

liner regulator [44] input:1.2 V

output:0.9 V

notneeded

0.6 nF (off-chip)


reduce the 2.5–5.5 V of input supply voltage into 1.5 Voutput with maximum load current of 250 mA and peakpower efficiency of 81%. The flying capacitors with each of1 µF and load capacitor of 4.7 µF can limit the ripple by12 mV when the load current is below 40 mA in thatchip [39].However, smaller size of capacitors may lead to a

considerable amount of switching noise and this restricts itsanalogue application. The switching noise can be reducedby using large capacitor(s) (may be of the order of μF) [40],but it may not be possible to implement it within a chip.Moreover, embedded switched capacitor-based convertershave low current driving capability. Although the approachproposed by Han et al. [36, 41] has not been implementedfor embedded DC–DC conversion, but it was a newtechnique to reduce the output ripple in switchedcapacitor-based DC–DC converters. It uses a new methodcalled as interleaved discharging to reduce ripple andimprove power efficiency. The advantages anddisadvantages of the usually available converter topologiescan be summarised in Table 1.

nts and performance parameters

aximum loadcurrent

Powerefficiency

Output ripplevoltage

Technologyused

60–140 mA 90% 300 mV whenthe supply

voltage rippleis 200 mV

0.18 µmCMOS

.8 mA (for 5 Vupply) andmA (for 2.5 Vsupply)

75% (for 5 Vsupply) and

70% (for 2.5 Vsupply)

40 mV (for 5 Vsupply) and40 mV (for

2.5 V supply)

0.35 µmCMOS

100 mA 70.07% at100 mA of load

current

no 90 nmCMOS


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It is transparent from the Table 1 that the power efficiency
of the usually available converters is high and the ripplebecomes low with the use of off-chip passive componentsand hence the system-level components are increased.Looking at the pros and cons of the usually available

converters, there is a recent trend of combining a switchingregulator (inductor-based or capacitor) with a linearregulator to achieve good power efficiency with low outputripple in high-dropout mode. For instance, combining aswitched capacitor converter and a linear regulator gives ahigh-dropout converter with good power efficiency [45]. Inthese hybrid converters the output ripple is kept low byusing external capacitor. The linear regulator in the hybridconverter also helps to achieve better load and lineregulation. A pre-specified regulated output voltage levelmay be achieved by it. In the next section, the descriptionon the design and development of embedded DC–DCconverters where load and switching capacitors are withinthe chip are elaborated.

3 Embedded DC–DC converters

There is a steady development on the research of embeddedDC–DC converters, where load and flying capacitors arewithin the die (total capacitance < = 1 nF) is going on. Anoverview of this development is given below.Patounakis et al. [46] and Mandal and Bhattacharyya [47]

had designed and implemented a hybrid DC–DC converter,which is a combination of switch–capacitor converter and alinear regulator, suitable for ‘high dropout’ conversion withgood power efficiency. In this hybrid converter the outputripple is high as the flying capacitors are on-chip implementable range and load capacitor is also within the die (i.e.<= 100 pF) [48]. The main problem of the embedded DC–DC converters is the low current driving capability. With afixed switching frequency and on-chip capacitance (i.e.< = 1 nF) to drive a particular value of load current thepeak-to-peak output voltage ripple is high but Patounakiset al. [46] did not concentrate on the ripple reduction issue.The ripple can be reduced by increasing the switchingfrequency but at the cost of power efficiency.There is a hybrid converter topology, which can be

implemented on-chip without any external capacitor, and itsoutput ripple is maintained within acceptable level [49].The converter consists of a switching circuit module

cascaded with a linear regulator (refer to Fig. 5). Linerregulator consists of ‘error amplifier’ and the pass device,

Fig. 5 Complete schematic diagram of a dual-switchedcapacitor-based DC–DC converter


M0. Unlike the conventional linear regulator the sourcenode of the pass device is not connected to the main powersupply but to the output of the switching circuit module.The switched capacitor circuit module, which is made ofswitches and capacitors, is responsible for stepping downthe input supply voltage to half of its value withhigh-power efficiency. However, this introduces asignificant amount of output voltage ripple. This ripple isreduced by the linear regulator based on its power supplyrejection ratio. Apart from the ripple reduction, the linearregulator is necessary to achieve line and load regulation ofthe converter.In addition, the dual-switched capacitor-based regulator is

analysed to predict two important performance metricsnamely ‘power efficiency’ and ‘output voltage ripple’. Thesmall signal analysis and reduction of the ripple originatedat the switched capacitor output by the linear regulator arepresented in [47, 49, 50]. From the derived expression ofsupply-to-output ripple rejection, it is transparent that theattenuation offered by the linear regulator is high for thelow-frequency ripple. However, the amount of ripple atthe output of the regulator is still alarmingly because of thepresence of high-frequency ripple (say, beyond 50 MHz).This is because of the bandwidth limitation of theregulation loop in the linear regulator. Motivated by thisurgency, a new technique for further reduction ofhigh-frequency ripple is introduced in [50, 51]. A signal,synchronous to the original ripple (which comes from theswitched capacitor module) is synthesised and it is fed intothe linear regulator in such a way that its effect at theoutput node counters the original ripple and hence, reducesthe net output ripple. The small signal analysis of the ripplesynthesiser is carried out to formulate the expression of thesynthesised ripple current needed to cancel out the rippleoriginated from the switched capacitor converter [49–51].The embedded DC–DC converter system with the proposedripple reduction is implemented and characterisedsuccessfully [50, 52].In case of embedded switched capacitor-based DC–DC

converters, during switching transition a short-circuit pathfrom output to ground and Vdd to ground is created becauseof the use of overlapping clocks. This eventually degradesthe power efficiency of the converter in the form ofshoot-through current [49, 50, 53]. This shoot-throughcurrent can be reduced by using non-overlapped clockssuch as break before make mechanism [49, 53]. However,in embedded applications where the load capacitor is verysmall, non-overlapped clocks results in dip in the outputvoltage because of temporary shortage of charge at theoutput. The dip can be reduced by using an extra transistorto compensate this momentary deficiency of charge at thecost of reduction in power efficiency [49].In addition to shoot-through current the short-circuit paths

also create ‘dip’ at output voltage. This is more prominent incase of on-chip DC–DC converters for embeddedapplications, where the load capacitance is within on-chipimplementable range (within 100 pF) [48]. It may be shownfor a given capacitance that the ripple voltage increaseswith the increase of output current. This ripple can bereduced by increasing the clock frequency of the converter.However, this increases the switching loss and shoot-through currents and degrades the power efficiency.Time-interleaving switching scheme for switching

converters [54] was proposed to reduce output voltageripple. The same scheme is utilised in the dual-switchedcapacitor converter to achieve smaller output voltage ripple


Fig. 6 Ten-element time-interleaving switched capacitor-based DC–DC converter

Fig. 8 Basic schematic of three-element NRTI switched capacitorconverter

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(refer to Fig. 6). The corresponding control signals are alsoshown in Fig. 7.In case of time-interleaving converter with 2N number of

elements, the N elements are in charging phase and theremaining are in charge-recycling phase and each element isdriven by one of the 2N clock phases. At each switchingtransition one pair of flying capacitors change their phaseswhereas all the other remain in their respective phases. Forthe same output current the dual-switched capacitorconverters output voltage ripple is reduced by N times. Inaddition, as the size of each switching transistor is decreasedby N times, the shoot-through current at each transitiondecreases by N times. This reduction in shoot-through currentreduces the dip at the output, thus further reduction in ripple.In time-interleaving converter, although the switching andshoot-through current losses at each transition are scaleddown by N times, the total loss per clock period remainssame because of 2N transitions per clock. It is true that thetime-interleaving scheme reduces the output voltage ripplebut it suffers from shoot-through current loss duringswitching transitions. Motivated by the aforementionedshortcomings, a new switching scheme called asnon-overlapped time interleaving (NRTI) switching scheme isproposed and implemented in [50] and [55].The working principle of the proposed NRTI switching

scheme [50, 55] can be explained using three-elementswitched capacitor converter. Fig. 8 depicts the basicschematic diagram of three-element NRTI switchedcapacitor-based DC–DC converter. Where, transistors M1,M2 … M12 act as switches and Cf1, Cf2, Cf3 are three flyingcapacitors of element-1, element-2 and element-3,respectively. Fig. 9 illustrates the timing diagram ofdifferent control signals used in three elements of theconverter. It is understood from the Fig. 8 that before the

Fig. 7 Control signals for ten-element time-interleaving switchedcapacitor-based DC–DC converter


state transition-1, Cf1 is connected between Vdd and outputthrough M1 and M4, Cf3 is connected between output andground through M10 and M11. Whereas, Cf2 is floating (M5,M6, M7 and M8 are ‘OFF’). At state transition-1, thecharging phase is transferred from element-1 to element-2,that is, M1 and M4 are entered into the ‘OFF’ state whereasM5 and M8 entered into the ‘ON’ state. So, for a shortperiod of time there is simultaneous conduction of thetransistors viz., M1, M4, M5 and M8. However, throughoutthis state transition, the transistors M2, M3, M6 and M7

remain in ‘OFF’ state. Thus, there is no direct conductionpath from output to ground or output to Vdd. As there areno short-circuit paths during this transition, theshoot-through current is eliminated. Although the

Fig. 9 Timing diagram of NRTI clock signals for three-elementswitched capacitor converter


Fig. 10 Eleven elements NRTI switched capacitor-based DC–DC converter

Fig. 11 Control signals for 11-element NRTI switchedcapacitor-based converter

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simultaneous conduction of M1, M4, M5 and M8 maymomentarily increase the charge from supply to the outputnode, but it is to be noted that it does not deteriorate powerefficiency.After the first transition T-1, Cf1 is in floating state, Cf2 is

connected between Vdd and output through M5 and M8 (i.e.charging state) and Cf3 in element-3 remains incharge-recycling phase. Similarly, at state transition-2, Cf1

changes from floating state to charge recycle phase and Cf3

goes from charge-recycling phase to floating state. That is,M10 and M11 go to ‘OFF’ state whereas M2 and M3 enterinto ‘ON’ state. So, for short period of time all of thetransistors M2, M3, M10 and M11 may simultaneouslyconduct. Similar to transition-1, this transition does notcreate any short-circuit paths as M1, M4, M9 and M12

remain in ‘OFF’ state throughout this transition. Similarly,at state transition-3 Cf3 changes from floating state tocharging phase and Cf2 goes from charging phase tofloating state and the rotation continuous. Thus, one caneliminate shoot-through current during phase transfers byensuring the phase acquiring capacitor enters from floatingmode at the phase transition.From the above discussion it is observed that each element

provides current for four parts of the cyclic period and itremains idle for two parts of cyclic period. So, at anysteady instance, two elements are active and remaining oneis in idle state. This means, effectively one-third of the totalflying capacitance is unused for eliminating the short-circuitcurrent. This capacitor overhead can be reduced byincreasing the number of elements. If we have total(2N + 1) elements then at any instant of time 2N elementssupply the current (active) and one element is left idlepreparing for next phase transition. Among the 2N activeelements half of the elements are in charging phase and theremaining half elements are in charge-recycling phase. Nowthe capacitor overhead is 1/(2N + 1)th of the total flyingcapacitor. In addition, increment in the number of elementsincludes the advantages of time-interleaving converter. Toillustrate the advantages numerically a 11-element NRTIswitched capacitor has been designed. It may be noted thatthe extension to higher number of elements is notstraightforward and the control signals with a duty cycle ofN/(2N + 1) needs to be given in a particular way.The 11-element NRTI switched capacitor converter and its

corresponding control signals are shown in Figs. 10 and 11,respectively.


Here, the supply current variation is also negligible sincethe shoot-through current is eliminated in the NRTIconverter. This unique feature of the converter eliminatespossible ground bounce effect of the converter.NRTI scheme can also be applied to the step-down

converters, where the output is the fraction of two-third,one-third and half of main supply voltage [56].It is to be noted that the output voltage of a switched

capacitor network is a fraction of its input voltage and thatfraction is a function of load current and switchingfrequency. Thus, a closed-loop control is essential forregulation. Hence, following regulation scheme may be used.

3.1 Current control regulation

Fig. 12 shows block diagram of current control regulationused in standalone switched capacitor-based DC–DCconverter [55]. The regulation loop consists of an erroramplifier, pass transistor and NRTI switched capacitorconverter as shown in the figure. In current control


Fig. 12 Block diagram of current control regulation

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regulation scheme, switching frequency of the convertercircuit is kept constant. The error amplifier senses thedifference between the reference voltage and the output ofthe converter and adjusts the gate voltage of the passtransistor to reduce the difference.As it is in negative feedback mechanism, the error gets

reduced to input referred offset voltage of the erroramplifier. Hence, to achieve very small error, the amplifiershould have high gain. In addition to this, with the highgain of the error amplifier itself one can achieve goodregulation even the pass transistor enters in triode region ofoperation. As the power consumption of the error amplifierreduces the power efficiency of the hybrid converter, theerror amplifier should consume as less power as possible.

3.2 Frequency control regulation

The notable disadvantage of the current control regulation isthe switching frequency of the converter remains constantirrespective of load current and it is known that in switchedcapacitor-based converter the switching loss is a majorcomponent of the total power loss and it is directlyproportional to the switching frequency. Hence, the powerefficiency is poor at low load current. To alleviate theproblem there is a proposal to change the switchingfrequency continuously by monitoring the load current.

Fig. 13 Block diagram of frequency control regulation


In frequency control regulation, the regulation loopconsists of an error amplifier, a voltage control oscillator(VCO), a duty cycle changer and a switched capacitorconverter as it is shown in Fig. 13 [50]. Motivation offrequency control regulation is to precisely maintain outputvoltage over wide range of load current by changing theswitching frequency of switched capacitor circuit. Switchedcapacitor converter takes supply voltage as direct input andconverts it to precise voltage level by self adjusting theswitching frequency of switched capacitor circuit.

3.3 Hybrid control regulation

Schematic diagram of hybrid control regulation is shown inFig. 14 [50]. Hybrid or mixed control regulation consists ofcurrent regulation loop and frequency regulation loop. Thecurrent regulation loop is made faster compared with thefrequency regulation loop. Current control regulationconsists of error amplifier, pass transistor and switchedcapacitor converter, whereas frequency regulation consistsof error amplifier, VCO, duty ratio changer and switchedcapacitor converter. Depending upon the load current, thefaster loop adjusts the input of pass transistor such thatoutput settles to pre-specified voltage level. Output of theerror amplifier also goes to the frequency regulation loop.Error signal of the error amplifier output act as a control


Fig. 14 Block diagram of hybrid control regulation

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voltage of the VCO, which in turn decide the frequencyof the VCO.In other way it can be mentioned that the bias voltage of

current starved VCO is decided by the error signal of erroramplifier and adjust the switching frequency of theswitched capacitor converter.For example, if the load current requirement is low, the

error amplifier pulls up its output voltage such that Vout,settles at a voltage close to the reference voltage. This loadinformation is used to reduce the oscillation frequency ofthe VCO. Reduction of the oscillation frequency of VCOreduces switching power loss of the switched capacitorconverter. As a result, overall switching loss of theconverter is decreased. Significant efficiency improvementis achieved in low load current regime with this hybrid ormixed control regulation scheme [57].

3.4 Voltage control regulation

The block diagram of NRTI switched capacitor DC–DCconverter with voltage control regulation scheme is depictedin Fig. 15 [58]. Here, the ‘error amplifier’ along with thepass device, Mp forms the linear regulator. The output of

Fig. 15 Block diagram of voltage control regulation


the NRTI switched capacitor converter is fed to the sourcenode Mp. The output voltage of the integrated converter,Vout is fed back to the non-inverting input of the erroramplifier. This voltage is compared with the Vref and theerror signal is fed to the source node of the pass device.However, the switched capacitor architecture in [49] and

[55] has only Vdd/2 option. Therefore it suffers from powerefficiency degradation particularly for the generation of theother fraction of output voltage.On the other hand it is shown in [59] and [60] that same

flying capacitors are used to provide three differentstep-down fractions of its input supply (Vdd) to meet thedifferent technology nodes. This reutilisation property ofthe same capacitor helps to improve the area efficiency ofthe converter.A NRTI switching-based dynamically reconfigurable

switched capacitor (S−C) topology is presented in [61]. Incombination with the current control loop its output voltagecan be adjusted dynamically over a wide range. It has aload sensing circuit which helps to dynamically reconfigurethe switched capacitor module based on the instantaneousload requirement (refer to Fig. 16). This feature enables toextend the load current range to a higher limit and at thesame time improves power efficiency in low load currentregime [61].The overall performance of the dynamically reconfigurable

DC–DC converter of [61] is compared with the contributionof the articles [60] and [62]. Although the comparison ofthat work is with the silicon measured performance of the[60] and [62], but one can get an idea of trend ofimprovement of the performance parameters in that part ofwork. It is observed that the power density of the proposedconverter is better than [62]. Moreover, the powerefficiency of the converter in [61] is improved by usingNRTI switching scheme and the ripple is also withinacceptable range. Le et al. [60, 63] had taken the advantageto integrate large value of capacitances with the use ofadvanced short-channel devices within the die.

4 Outline of the prospective research

Improvement of power efficiency is still a major concern to beconsidered. In the near future, new power saving methodsmust be explored to enhance the power efficiency of theembedded converters. The bottom plate parasitic loss can bealleviated with the use of upgraded isolated well


Fig. 16 Block diagram of dynamically reconfigurable hybrid DC–DC converter [60]

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technology. Moreover, each of the bulky power switches canbe assumed as a composite switch of so many small switchesand portion of the switches may be off depending on therequirement of the load current. This can improve thepower efficiency by reducing the corresponding losses butat the cost of a bit complicated controller design. Thepower density and power efficiency can also be improvedby integrating a large amount of capacitor with theaggressive scaling of the CMOS technology. Enhancementof load current driving capability and improvement of thetransient response of the embedded converters can be twokey research problems for the prospective researchers. TheMOS devices with ‘high-K’ dielectric gate oxide canprovide large MOS capacitance with a comparatively lessamount of area and hence the current driving capability ofthe switched capacitor-based converters can be increased.As a noteworthy alternative, the parasitic packaginginductor can be used to provide fully-integratedinductor-based solution with high load current drivingcapability. The inductor which is comprised of a packagelead and bonding wire can be used there. It may have muchhigher Q factor than the best on-chip inductorsimplemented on silicon.

5 Conclusion

This paper reviews the available DC–DC converters bytargeting towards the design of embedded DC–DCconverters with a motivation to achieve miniaturised, lightand highly power dense solutions. Starting from theconventional bulky inductor-based converters the authorfinally concluded to the present trend towards the design ofembedded DC–DC converters. A brief theoretical detail,related control techniques, a comprehensive overview of thestate-of-the-art practices and practical considerations todesign the embedded converters are illustrated here.Different issues and their mitigation techniques forachieving on-chip solution are also provided here. Finally,


an overview on the prospective research items ishighlighted in the paper.

6 Acknowledgments

The author thankfully acknowledges to his Parents Mr. AshimBhattacharyya and Mrs. Alpana Bhattacharyya and hisProfessors Dr. Pradip Mandal and Dr. Anindya SundarDhar of E&ECE Department, IIT-Kharagpur, India for theirinspiration, encouraging support and blessings.

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Trend towards the design of embedded DC–DC converters