BO CO PROJECT 2 GVHD: Ths.Dng Thanh Phng

BO CO PROJECT 2 GVHD: Ths.Dng Thanh Phng

TRNG I HC BCH KHOA H NIVIN IN T VIN THNG====o0o====

BO CO PROJECT 2 TI: H THNG GIM ST,TRUYN PHT NHIT S DNG SNG RF TN S 2.4GHZ

GVHD : Ths.Dng Thanh Phng

Sinh vin : To Tun Mnh TTT7-K56 20111842 Trn Th Minh Tuyn TTT8-K56 20112466

H Ni,12/2014

LI NI U

Ngy nay phng thc truyn nhn d liu khng dy ang ngy cng pht trin v c ng dng rng ri trong khoa hc k thut, trong cuc sng. Cc h thng khng dy thng nh gn, tit kim chi ph do khng phi s dng dy ni. Cc h thng khng dy thng s dng sng wifi, sng RF. Nhng ng dng, h thng c nh, trung bnh th s dng sng wireless truyn nhn d liu l mt la chn hp l.Mt h thng khng dy khng ch nh gn n cn i hi phi tit kim nng lng h thng c th s dng trong thi gian di vi cc ngun cp c lp nh pin, nng lng mt tri. V vy,chng em la chn ti H thng gim st, truyn pht nhit s dng sng RF tn s 2.4GHz .Do kin thc cn hn ch nn bi bo co khng trnh khi cn nhiu sai st, chng em mong nhn c s gp ca thy bi bo co hon thin hn.

Li ni u1Chng 1M t ti51.1.Yu cu chc nng51.2.Yu cu phi chc nng51.3.S khi chc nng5Chng 2Thit k phn cng52.1.Khi x l : vi iu khin MSP430G255352.2.Khi truyn pht : Module nRF24L01102.3.Khi cm bin : DS18B20132.4.Khi hin th : LCD 16x215Chng 3Hon thin sn phm173.1.S layout Master173.2.S layout Slave183.3.Hnh nh tht sn phm19

DANH MC HNH NH

Hnh 1.1. S khi chc nng..........4 Hnh 2.1. S khi vi iu khin MSP430x2xx..............................................................5 Hnh 2.2. S chn MSP430G2553................................................................................6 Hnh 2.3. S cc thanh ghi trong CPU MSP430...9 Hnh 2.4. S khi module nRF24L0............................................................10Hnh 2.5 S chn nRF24L01.....11Hnh 2.6. S nguyn l module nRF24L0.................................................................12 Hnh 2.7. S khi DS18B20..12Hnh 2.8. S chn ca DS18B20...................................................................................13 Hnh 2.9. S khi hin th LCD.....................................................................................14 Hnh 2.10. LCD 16x2.15Hnh 3.1. Layout Master.....................................................................................................16 Hnh 3.2. Layout Slave.......................................................................................................17Hnh 3.3. Hnh nh sn phm.............................................................................................18

DANH SCH BNG BIUHnh 2.1. T chc b nh...........10 Hnh 2.2. iu kin lm vic ca nRF24L01.12Hnh 2.3. Cc ch hot ng cu nRF24L01.................................................................12

NI DUNGM t ti0. Yu cu chc nngGim st, truyn pht song song gia mt Master v mt Slave,hin th nhit ln LCD0. Yu cu phi chc nng1. S dng dng vi iu khin MSP430 ca Texas Instrument,c th l MSP430G25531. Module thu pht sng RF nRF24L01 ca Nordic1. Cm bin nhit DS18B201. PCB nh gn1. Ngun p thp 3.3V1. Khong cch truyn nhn d liu ca cc module t 30m 40m.0. S khi chc nng

KHI HIN THKHI X LKHI CM BINKHI TRUYN NHN

Hnh 1.1 S khi chc nng

Thit k phn cngKhi x l : vi iu khin MSP430G2553a)Gii thiu v dng VK MSP430 ca TI.MSP430 l mt h vi iu khin 16 bit c cu trc RISC ca Texas Instrument.y l dng vi iu khin s dng in p thp 1.8V-3.6V, tiu th dng thp. N kt hp cc c tnh ca CPU hin i v cc thit b ngoi v. Vi CPU s dng ngun xung dao ng ni nn kh nng x l CPU nhanh v tin li cho vic thit k mch.MSP430 h tr cc chun giao tip : UART, SPI, I2C, IrDA VK MSP430 c th giao tip vi cc thit b ngoi vi, cc b nh ngoi, cc vi iu khin khc.Bn trong VK cn tch hp mt cm bin nhit .Ngoi ra n cn h tr b chuyn i ADC, DAC ni tch hp trong VK.MSP430 l mt la chn hp l cho cc ng dng nh gn, tit kim nng lng.b)VK MSP430G2553.b1)Thng s k thut ca MSP430G2553.+Ngun in th s dng trong khong t 1.8V n 3.6V.1. Ch hot ng: 270 A ti 1MHz v 2.2V.1. Ch ng: 0.7 A.1. Ch khng hot ng: 0.1 A.1. Thi gian thc dy t ch ng t hn 1s.+Cu trc RISC 16 Bit, mi chu k lnh hot ng mt 62.5ns.+H tr cc giao din giao tip nh: UART, SPI.+H tr mt timer A.+B chuyn i ADC 10-Bit vi tc chuyn i ln n 200ksps.+B nh flash 16KB.+B nh RAM 512B.

Hnh 2.1: S khi vi iu khin MSP430x2xx Hnh 2.2 : S chn MSP430G2553.-DVCC(Pin 1):1. Ni vi ngun cung cp1. P1.0/ TA0CLK/ ACLK/A0/CA0(Pin 2):1. Chn chc nng vo/ra s. 1. Timer0_A, tn hiu clock ng vo TACLK .1. Ng ra xung ACLK.1. Ng vo tng t A0 ca ADC10.1. B so snh Comparator_A+, ng vo CA0.1. P1.1/ TA0.0/ UCA0RXD/ UCA0SOMI/ A1/CA1 (Pin 3):1. Chn chc nng vo/ra s.1. Timer0_A, capture: ng vo CCI0A, compare: Out0 ng ra / BSL transmit.1. USCI_A0 ng vo nhn d liu trong ch UART.1. USCI_A0 D liu ra Slave/ vo Master trong ch SPI .1. ADC10 ng vo tng t A1 (1).1. Comparator_A+, ng vo CA1.1. P1.2/ TA0.1/ UCA0TXD/ UCA0SIMO/ A2/CA2 (Pin 4):1. Chn chc nng vo/ra s1. Timer0_A, capture: CCI1A ng vo, compare: Out1 ng ra.1. USCI_A0 ng ra truyn d liu trong ch UART .1. USCI_A0 D liu vo Slave/ra Master trong ch SPI.1. ADC10 ng vo tng t A2 (1)1. Comparator_A+, CA2 ng vo.1. P1.3/ ADC10CLK/ A3/VREF-/VEREF-/ CA3/CAOUT( Pin 5):1. Chn chc nng vo/ra s .1. ADC10, ng ra xung nhp chuyn i ADC10 ng vo tng t A3 (1).1. ADC10 in p tham chiu m.1. Comparator_A+, CA3 ng vo.1. Comparator_A+, ng ra.1. P1.4/ SMCLK/ UCB0STE/ UCA0CLK/ A4/VREF+/VEREF+/ CA4/TCK (Pin 6):1. Chn chc nng vo/ra s.1. SMCLK tn hiu ng ra.1. USCI_B0 Cho php Slave truyn.1. USCI_A0 clock ng vo/ng ra .1. ADC10 ng vo tng t A4 (1).1. ADC10 in p tham chiu dng.1. Comparator_A+, CA4 ng vo.1. JTAG xung nhp kim tra, ng vo ni tip cho thit b np v kim tra chng trnh.1. P1.5/ TA0.0/ UCB0CLK/ UCA0STE/ A5/CA5/TMS (Pin 7):\1. Chn chc nng vo/ra s.1. Timer0_A, compare: Out0 ng ra / BSL nhn .1. USCI_B0 clock ng vo/ng ra.1. USCI_A0 cho php slave truyn.1. ADC10 ng vo tng t A5 .1. Comparator_A+, CA5 ng vo.1. JTAG la chn ch kim tra, ng vo ni tip cho thit b np v kim tra chng trnh.1. P2.0/TA1.0 (Pin 8):1. Chn chc nng vo/ra s.1. Timer1_A, capture: CCI0A ng vo, compare: Out0 ng ra.1. P2.1/TA1.1 (Pin 9):1. Chn chc nng vo/ra s.1. Timer1_A, capture: CCI1A ng vo, compare: Out1 ng ra.1. P2.2/TA1.1( Pin 10):1. Chn chc nng vo/ra s.1. Timer1_A, capture: CCI1B ng vo, compare: Out1 ng ra.1. P2.3/TA1.0 (Pin 11):1. Chn chc nng vo/ra s.1. Timer1_A, capture: CCI0B ng vo, compare: Out0 ng ra.1. P2.4/TA1.2( Pin 12):1. Chn chc nng vo/ra s .1. Timer1_A, capture: CCI2A ng vo, compare: Out2 ng ra.1. P2.5/TA1.2 (Pin 13):1. Chn chc nng vo/ra s .1. Timer1_A, capture: CCI2B ng vo, compare: Out2 ng ra.1. P1.6/ TA0.1/ A6/ CA6/UCB0SOMI/ UCB0SCL/TDI/TCLK (Pin 14):1. Chn chc nng vo/ra s .1. Timer0_A, compare: Out1 ng ra .1. ADC10 ng vo tng t A6 .1. Comparator_A+, CA6 ng vo.1. USCI_B0 ng ra slave/ng vo master trong ch SPI USCI_B0 xung nhp SCL I2C trong ch I2C.1. JTAG kim tra d liu ng vo hoc kim tra xung nhp ng vo trong khi chy hoc kim tra chng trnh.1. P1.7/ A7/ CA7/CAOUT/ UCB0SIMO/ UCB0SDA/ TDO/TD I (Pin 15):1. Chn chc nng vo/ra s 1. Chn chc nng vo/ra s.1. ADC10 ng vo tng t A7 1. Comparator_A+, CA7 ng vo 1. Comparator_A+, ng ra1. USCI_B0 Ng vo slave, ng ra master trong ch SPI1. USCI_B0 SDA I2C d liu vo trong ch I2C1. JTAG JTAG kim tra d liu ng ra hoc kim tra xung nhp ng vo trong khi chy hoc kim tra chng trnh.1. RST/ NMI/SBWTDIO( Pin 16):1. Reset1. Ngt ng vo khng che1. Spy-Bi-Wire kim tra d liu ng vo/ng ra trong khi chy v kim tra chng trnh1. TEST/SBWTCK( Pin 17):1. La chn ch kim tra chn JTAG trn Port 1. 1. Cu ch bo v thi b n TEST.1. Spy-Bi-Wire kim tra xung nhp ng vo trong khi chy v kim tra chng trnh1. XOUT/P2.7( Pin 18):1. Ng ra ni ca b giao ng thch anh1. Chn chc nng vo/ra s1. XIN/ P2.6/TA0.1 (Pin 19):1. Ng vo ni ca b giao ng thch anh1. Chn chc nng vo/ra s 1. Timer0_A, compare: Out1 ng ra1. DVSS (Pin 20) :Chn ni mass.

b2)Tm hiu CPU ca MSP430G2553.CPU ca vi iu khin MSP430g2553 c kin trc RISC 16 Bit (Reduced Intruction Set Computer) l mt kin trc vi x l theo hng n gin ha tp lnh. Cc lnh c xy dng c th thc hin vi ch 1 chu k my. Mt khc, bus d liu v bus a ch (c rng 16 Bit) tch ri nhau iu ny gip cho qu trnh c d liu v m lnh c th din ra ng thi do nng cao hiu sut lm vic ca vi iu khin.CPU ca vi iu khin MSP430g2553 gm 16 thanh ghi 16 Bit. Trong R0 n R3 c cc chc nng c bit nh: thanh ghi m chng trnh, thanh ghi con tr, thanh ghi trng thi, thanh ghi hng. Cc thanh ghi cn li c s dng vi mc ch chung.

Hnh 2.3: S cc thanh ghi trong CPU MSP430 T chc b nh.Bng 2.1: T chc b nh.B nhDung lnga ch

ROM:+ B nh vector ngt+ B nh chng trnh16kB

0xFFFF to 0xFFC00xFFFF to 0xC000

RAM512 Byte0x03FF to 0x0200

Ngoi vi:+ 16 bit.+ 8 bit.+ 8 bit FSR.0x01FF to 0x01000x0FF to 0x0100x0Fh to 0x00

Khi truyn pht : Module nRF24L01a) Gii thiunRF24L01 l mt trong nhng dng sn phm ca nh sn xut Nordic (Nauy), c chcnng thu pht tn hiu qua sng RF s dng in p thp (3.3V).Mt vi im chnh ca chip nRF24L01:1. Thc hin chc nng thu pht d liu bng sng RF tn s 2.4GHz.1. S dng dng sng iu ch GFSK.1. Tc truyn ti d liu trong khng kh 1Mbp 2Mbp.1. Tiu th nng lng thp, s dng in p thp (3.3V).1. S dng giao thc phn cng Shockburst.+ T ng to gi d liu (Preamble, Address, CRC).+ T ng pht hin gi d liu v xc nhn.+ La chn d liu t 1-32 Byte.+ C kh nng truyn li d liu+ T ng xc nhn m ACK.+ C 6 ng dn truyn nhn d liu.1. S dng giao thc SPI trao i d liu vi Vi iu khin, tc truyn nhn d liu ln ti 10Mbp.Mt s ng dng c bn ca nRF24L01:1. Thit b ngoi vi my tnh khng dy.1. ng dng trong chut, bn phm v iu khin t xa.1. iu khin t xa bng sng RF cho cc thit b in t tiu dng.1. Mng cm bin vi in nng cc thp.1. T ng ha trong thng mi v gia dng1. ng dng trong chi.b) S khi

Hnh 2.4 : S khi module nRF24L01c) S chn

Hnh 2.5: S chn nRF24L01d) iu kin lm vicBng 2.2: iu kin lm vic ca nRF24L01.

SymbolThng sNotesMin.Typ.Max.Units

VDDin p cung cp1.93.03.6V

VDDin p tn hiu ng vo >3.6V2.73.03.3V

TEMPNhit lm vic-40+27+85C

e) Hot ng ca nRF24L01.nRF24L01 c nm ch hot ng c bn c iu khin bi cc bit PWR_UP, PRIM_RX trong thanh ghi CONFIG v chn CE. Bng 2.3 : Cc ch hot ng ca nRF24L01.

ModePWR_UP BitPRIM_RX BitCE

RX mode111

TX mode101

TX mode10Xung cao ti thiu 10s

Standby-II101

Standby-I1-0

PowerDown0--

g) S nguyn l

Hnh 2.6: S nguyn l module nRF24L01Khi cm bin : DS18B20a) Gii thiu1. L cm bin nhit digital ca hng Dalas.1. S dng giao thc chun One-wire giao tip d liu vi thit b iu khin.1. C th o nhit t -55o C n 1250C.1. Ngun cung cp t 3V n 5.5V.1. Chuyn i nhit thnh d liu s 9-12 bit.b) S khi

Hnh 2.7: S khi DS18B20c) S chn

Hnh 2.8 : S chn ca DS18B20.

Pin 1 : Chn GNDPin 2: Chn DQ d liu ng ra.Pin 3: Chn Vdd ni ngun.

d) Hot ng chuyn i nhit Nhit c chuyn i thnh d liu s t 9-12 bit, tng ng vi phn gii 0.5oC, 0.25oC, 0.125oC, 0.0625oC thng qua m lnh chuyn i 44h. phn gii mc nh ca DS18B20 l 12 bit (0.0625oC). ci t phn gii ta thay i thanh ghi cu hnh ca DS18B20( Byte 4 ca b nh m).

Bng 4.1 : La chn phn gii cho DS18B20R1R0 phn gii

009 bit

0110 bit

1011 bit

1112 bit

D liu sau khi chuyn i s c lu trong byte 0, byte 1 ca b nh m.

Trong S: l bit du: S = 0 nu nhit dng, =1 nu nhit m. Vi cc phn gii thp hn cc bit thp nhp trong byte 0 s lu 0.Khi hin th : LCD 16x2LCD 16x2 c s dng hin th giao din trong qu trnh ng nhp, hin th v thit lp thi giana) S nguyn l

Hnh 2.9 : S khi hin th LCDb) Cu to v hot ng

Hnh 2.10 : LCD 16x2LCD 16x2 l Text LCD c chia sn thnh tng v ng vi mi ch c th hin th mt k t ASCII, c phn chia thnh 2 hng, mi hng c 16 .Nguyn l hot ng: Chn VCC, VSSv VEE: Cc chn VCC, VSSv VEE: Cp dng ngun - 5v v t tng ng th VEE c dng iu khin tng phn ca LCD. Chn chn thanh ghi RS (Register Select): C hai thanh ghi trong LCD, chn RS(Register Select) c dng chn thanh ghi, nhsau: Nu RS = 0 th thanh ghi m lnh c chn cho php ngi dng gi mt lnh chng hn nh xo mn hnh, a con trv u dng v.v Nu RS = 1 th thanh ghi d liu c chn cho php ngi dng gi dliu cn hin thtrn LCD. Chn c/ ghi (R/W): u vo c/ ghi cho php ngi dng ghi thng tin ln LCD khi R/W = 0 hoc c thng tin tn khi R/W = 1. Chn cho php E (Enable): Chn cho php E c sdng bi LCD cht d liu ca n. Khi dliu c cp n chn dliu th mt xung mc cao xung thp phi c p n chn ny LCD cht dliu trn cc chn d liu. Xung ny phi rng ti thiu l 450ns. Chn D0 - D7: y l 8 chn dliu 8 bt, c dng gi thng tin ln LCD hoc c ni dung ca cc thanh ghi trong LCD. Tuy nhin trong mch s dng LCD 4 bit nn 4 chn D0-D3 s khng s dng. hin thcc chci v cc con s, chng ta gi cc m ASCII ca cc chci tA n Z, a n f v cc con s t 0 - 9 n cc chn ny khi bt RS = 1. Cng c cc m lnh m c th c gi n LCD xo mn hnh hoc a con trv u dng hoc nhp nhy con tr.Hon thin sn phmS layout Master

Hnh 3.1 : Layout MasterS layout Slave

Hnh 3.2 Layout SlaveHnh nh tht sn phm

Hnh 3.3 Hnh nh sn phmKT LUN Trn y l ton b qu trnh thc hin mn n 2 ca nhm chng em vi ti: H thng gim st, truyn pht nhit s dng sng RF tn s 2.4GHz. Tuy nhin nhit c hin th cng cha hon ton chnh xc so vi nhit mi trng. Nhm sinh vin chng em xin chn thnh cm n s hng dn tn tnh ca thy Nguyn Hong Dng trong sut qu trnh thc hin ti.TI LIU THAM KHO[1] http://www.ti.com/product/msp430g2553[2] http://www.alldatasheet.com[3] http://www.dientuvietnam.net

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