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LG ElectronicsLG Electronics

Two Chipsets for DTV Two Chipsets for DTV

Compliant with ATSC StandardCompliant with ATSC Standard

August 17, 1998

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LG ElectronicsLG Electronics

ContentsContents

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����Implementation of 1Implementation of 1 st Generation Chipsetst Generation Chipset

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LG ElectronicsLG Electronics

IntroductionIntroduction

� 1 st & 2 nd generation chipsets compatible with ATSC

DTV

standard

� Support 5 VSB modes : Terrestrial 8VSB and MMDS

2/4/8/16 VSB

� Transport demux having 16 bits interface with MCU

� MPEG2 MP@HL Video decoding including all 18 ATSC

formats

� Video format conversion, any transmission to HD(1080I,

1 st

gen.) or SD(480I/P, 2 nd gen.) display

� Seamless image format change

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LG ElectronicsLG Electronics

VSBVSB

Sync/EQ(GDC21D001)Sync/EQSync/EQ

(GDC21D001)(GDC21D001)

VideoDecoder

(GDC21D401)

VideoVideoDecoderDecoder

(GDC21D401)(GDC21D401)

AudioDecoderAudioAudio

DecoderDecoder

8M ByteSDRAM8M Byte8M ByteSDRAMSDRAM

8M ByteSDRAM8M Byte8M ByteSDRAMSDRAM

I/F Demod.LA7785M

I/FI/F Demod Demod..LA7785MLA7785M

ADCADCADC

MCUMCUMCU

RGB/RGB/YCbCrYCbCr1080I1080I

5.15.1ChCh..AudioAudio

Chipset partitionsChipset partitions

4M bitDRAM4M bit4M bitDRAMDRAM

Transport(GDC21D301)TransportTransport(GDC21D301)(GDC21D301)

TunerTunerTuner ChannelDecoder

(GDC21D002)

ChannelChannelDecoderDecoder

(GDC21D002)(GDC21D002)

VDP(GDC21D701B)

VDPVDP(GDC21D701B)(GDC21D701B)

�� 1 1 stst Generation Chipset Partition(5 chips, HD) Generation Chipset Partition(5 chips, HD)

MuxMuxMux

VGAVGA(Digital)(Digital)

NTSCNTSC(Decode(Decode

d)d)

DTVDTV

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LG ElectronicsLG Electronics

SD Video(GDC21S801)

DemuxMP@HL Dec.

VDPGraphic Proce.NTSC Enc./Dec.

D/A

SD VideoSD Video(GDC21S801)(GDC21S801)

DemuxDemuxMP@HL Dec.MP@HL Dec.

VDPVDPGraphic Graphic ProceProce..NTSC NTSC EncEnc./Dec../Dec.

D/AD/A

8M ByteSDRAM8M Byte8M ByteSDRAMSDRAM

I/F Demod.LA7785M

I/FI/F Demod Demod..LA7785MLA7785M

MCUMCUMCU

5.15.1ChCh..AudioAudio

Chipset partitionsChipset partitions

TunerTunerTuner

�� 2 2 ndnd Generation Chipset Partition(2 chips, SD) Generation Chipset Partition(2 chips, SD)

DTVDTV

AudioDecoderAudioAudio

DecoderDecoder

VSBReceiver(GDC21D003)

ADCSync

EqualizerFEC

VSBVSBReceiverReceiver(GDC21D003)(GDC21D003)

ADCADCSyncSync

EqualizerEqualizerFECFEC

p la y

RGB/RGB/YCbCrYCbCr CVBS/S-CVBS/S-

VideoVideo480I/P480I/P

VGAVGA(Analog(Analog

))

NTSCNTSC(Decoded(Decoded

/Not/Notdecoded)decoded)

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LG ElectronicsLG Electronics

�� TP Decoder(1 TP Decoder(1 st st GenGen.).)

� Byte-parallel/bit-serial MPEG-2

TS input

� Audio PES/Video ES output

� Identify 32 PIDs

� Extract DTS/PTS for video

decoder

� PCR recovery

� Error code insertion for video

� 8/16-bit bus host interface

� Max. TS input rate : 80Mbit/s

Features of Video ChipsFeatures of Video Chips

�� Decodable 18 input

formats

of ATSC standard

� Tricky mode decoding

� MB 4 pixel parallel output

� Decoding operation up to

54MHz

� 64bit Bus Mem. I/F

(Four 1Mx16 SDRAM)

� Up to 81MHz asyn. Memory

I/F

�� Video Decoder(1 Video Decoder(1 st st GenGen.).)

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LG ElectronicsLG Electronics

�� Video Display Processor(1 Video Display Processor(1 st st GenGen.).)

RGB/YCbCr(analog)

Coeff.Loader

OSD

3ChDAC

CSC

LUTLoader

HdVd

Sync.Gen.

PIP & Disp.

Control

HD/SD

NTSC/VGA

NTSC/VGA

(4:2:2)

MB 32bits

(4:2:0)

HostI/F

Digital Output/ Host IF

De-nterlacing&

Format Con.

SDRAM

LUT

Mux

I2C I/F

Arbiter &

SD

RA

M I/F

Mux

� 18 ATSC formats, 480x768I/P(NTSC),

480x640P, 768x1024P(SVGA) input

� Analog/digital 1080 RGB/YCbCr output

� De-interlacing using 3 field memory

for 480I input

� 9-tap horizontal peaking filter

� PIP/Multi-PIP/Zoom

� 2/4/16/256-colors/4-pixels OSD

� RGB/YCbCr Color Space Converter

� 8-bit custom controlled LUT

� Host I/F: 16 bit parallel or I2C I/F

Features of Video ChipsFeatures of Video Chips

HD

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LG ElectronicsLG Electronics

� One-chip for TP, VD, VDP & NTSC

� MPEG2-TS/PES, DVD, DSS-SD(HD),

& MPEG-1 Decoding up to

100Mbps

� EPG/SI(PAT,PMT,PSIP, etc) section

filtering and CRC checking

� Identify 32 packet PIDs/table IDs

� PCR recovery

� PES layer audio output

� Down Conversion for HD stream

� Slice-based error concealment

� Tricky mode decoding

�� Input picture formats : 18 ATS

C

/DSS(4:2:0), NTSC, VGA(4:4:4)

� Output picture formats :

Analog

RGB/YCbCr/CVBS/S-Video

& Digital 480x852I/P,

480x768I/P

� 3-D de-interlacing using 3 field

memory for 480I input

Features of Video ChipsFeatures of Video Chips

�� Features of SD Video(2Features of SD Video(2 nd nd GenGen.).)

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LG ElectronicsLG Electronics

� Seamless image format change

� PIP/Multi-PIP/Zoom/D-window

� 4 layer full screen bit-map OSD

(2/4/8bits color or 8bits blending)

� NTSC Decoder/Encoder

� Fully compatible with EIA-608

NTSC closed caption

� Analog VGA Interface(4:4:4)

¾ 3-channel 10-bit A/D

¾ RGB to YCbCr Color Space

Converter

� Max. 600Mbits/s bandwidth at

VGA main, DTV PIP, Dual prime

decoding, and full screen OSD

� Video contents protection(V-chi

p)

� 16bits host interface

� 8MB SDRAM interface

� No dead-lock condition

� Boundary scan test (JTAG)

� 0.35µm /3.3V/352BGA

Features of Video ChipsFeatures of Video Chips

�� Features of SD Video(2Features of SD Video(2 ndnd Gen Gen.).)

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LG ElectronicsLG Electronics

TS/PSDemux

VideoDecoder

De-interlacing

&Format

Converter

NTSCDecoder

NTSCEncoderCSC

&LUT

CCDecoder

Graphic P

roc. &

multi-P

IP

SDRAM Arbiter

PWMGen.

D/A

VGAI/F

Mux

A/D

PSI/F

TSI/F

Host I/F

Audio &

Data

I/F

Memory Data Bus

Host Bus

8MB SDRAM(16Mbit * 4)

NTSC InputCVBS/S-Video/YUV

VGA RGB Input

Analog OutputsRGB/YPbPr/CVBS/S-Video

Digital OutputRGB/YCbCr

27MHzVCXO

DTV/DVD/DSS/Video-CD

AC-3 (Association)

Data

TP Stream(IEEE1394)

AC-3(main)/MPEG/PCMAudio PES Output

Memory BusHost BusAddress BusIn/Out Signals

REGENDto External

Host Processor

�� Block Diagram of SD Video(2 Block Diagram of SD Video(2 nd nd GenGen.).)

Features of Video ChipsFeatures of Video Chips

DMA

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LG ElectronicsLG Electronics

�� Sync/ Sync/EqEq (1 (1 stst Gen Gen.).)

� Coherent & non-coherent AGC�

DC reduction�

Timing recovery�

Data segment sync and Frame

sync recovery�

NTSC rejection comb filter�

Decision-feedback equalizer�

64 tap FF & 192 tap FB Filter�

Phase corrector

Features of VSB ChipsFeatures of VSB Chips

�� VSB VSB ChCh. Dec.(1. Dec.(1 st st GenGen.).)

� 4&8 states TCM decoder : L=16

� Slice prediction for phase

corrector

� De-interleaver

� Reed-Solomon decoder(208,188)

� Error flag insertion on errorneous

packet

� Tri-state parallel/serial MPEG-2

transport I/F

� Internal segment error counter

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LG ElectronicsLG Electronics

�10bits differential ADC (1Vpp)�

Coherent & non-coherent AGC�

Modified DS/Frame sync recovery�

Auto NTSC rejection comb filter�

Enhanced VSB mode detector �

Decision-feedback and

Blind(D-D mode) Equalizer�

64 tap FF & 192 tap FB Filter�

Concurrent coefficients updating�

Monitoring equalizer coefficients

�Intelligent loop controlled

Phase Corrector

� 4&8 states TCM decoder : L=16

� Error flag insertion on error

� Tri-state parallel MPEG-2 TP I/F

� Internal segment error counter

� I2C bus Interface

� 0.35µm /3.3V

� 128pin HQFP

Features of VSB ChipsFeatures of VSB Chips

�� Features of 1 Chip VSB Receiver(2 Features of 1 Chip VSB Receiver(2 ndnd Gen Gen.).)

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LG ElectronicsLG Electronics

DigitalInput(10bits)

CombFilter

TimingRecovery

AGC

I2CInterface

I2C bus

DCReduct.

ADCMux

AnalogInput Polarity

Correct.

To I/F Polarity Detect

DS SyncRecoveryTo PLL

Field SyncRecovery

ChannelEqualizer(256taps)

PhaseCorrector

VSB modeDetector

Viterbi Decoder

Reed-SolomonDecoder

ConvolutionDe-

interleaver

FieldSync

DataDe-

randomizer

TransportI/F

To TransportDecoder

ClockDivider

From VCXO

Features of VSB ChipsFeatures of VSB Chips

�� Block Diagram of 1 Chip VSB Receiver(2 Block Diagram of 1 Chip VSB Receiver(2 ndnd Gen Gen.) .)

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LG ElectronicsLG Electronics

Design MethodologyDesign Methodology

VHDL description

VHDL simulation

VHDL synthesis

Test Logic insertion

Place & route

Gate level function& timing simulation

Real time testH/W Emulation

Layout verification

Compass(Synopsys) Quikturn Altera

VSIM, leapfrog

Compass(Avante)

Compass(Verilog-XL, VSIM)

Compass(Synopsys)

Summit, VI

Compass(Dracular, Calibre)

1 st gen.(2 nd gen.)

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LG ElectronicsLG Electronics

Chips Sync/Eq VCDTP VD VDP

Die size

Gate count(k)

Clock(MHz)

Power(mW)

Package

Fab.

12x12 10x96x6 13x12 9x9

230 20050 250 520

10.76 10.7627 54, 81 54,65,75

2500 500300 1500 3000

160 PQ2 100 MQFP176 TQFP240 HQFP 304 PQ2

LGS LGSLGS LGS LGS

Technology 0.6u, TLM0.6u, TLM0.6u, TLM0.6u, TLM0.35u,TLM

Status Q. S. Q. S.Q. S. Q. S. Revision

�� Summary of 1 Summary of 1 st st gengen. chipset implementation. chipset implementation

Implementation of 1Implementation of 1 st st GenGen. Chipset. Chipset

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LG ElectronicsLG Electronics

RS Dec.

De-Rand.

Viterbi Dec.

De-Interl.

�� Sync/ Sync/EqEq �� VCD VCD

Implementation of 1Implementation of 1 st st GenGen. Chipset. Chipset

Equalizer

Sync

FIR Filter

PLL

Ph.Corr.

Host I/F V/A/D I/F

TSDec.

PES Dec.

DRAM I/F Mem.

Mem.

IQ/IS

BuffersMV Dec.

VLD

IDCT

SDRAMI/F

NTSC I/F

SDRAM I/F

Format Converter

CSC

DAC

DTV I/F

�� Layout of 1 Layout of 1 st st Gen Gen ChipsetChipset

�� TP TP DemuxDemux �� Video Decoder Video Decoder �� VDP VDP

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LG ElectronicsLG Electronics

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