UltraFast 嵌入式设计方法指南(UG1046)

UltraFast

UG1046 (v2.2) 2017 7 27

UltraFast 2UG1046 (v2.2) 2017 7 27 china.xilinx.com

2017 7 17 2.2 Vivado IDE

2015 4 22 2.1

2015 3 26 2.0 SDSoC

2014 10 20 1.1

2014 10 8 1.0

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1 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 (Profiling) (Partitioning) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75PL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77ACP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81PL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88GP APU PL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96OS RTOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

5 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Vivado IDE IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122UltraFast 3UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 (HLS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

6 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 SDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

8 : SDSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 C RTL IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 HLS IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

A: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Documentation Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Xilinx Documentation Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167UltraFast 4UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


1

All Programmable SoC All Programmable SoC

All Programmable SoC Vivado Design Suite UltraFast (UG949) [ 16] FPGA

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1

SDSoC

1-1

1-1

1-1

X X X

X X

X X

X

X

X X

SDSoC XUltraFast 6UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


1 SDSoC 1-1 2 - 7 8 SDSoC

All-Programmable SoC

Zynq-7000 All Programmable SoC (UG585) [ 4] Zynq-7000 All All Programmable SoC (UG821) [ 7]

Zynq-7000 AP SoC Zynq-7000 All Programmable SoC (DS190) [ 29]

X-Ref Target - Figure 1-1

1-1

System Level Considerations

Debug

Hardware DesignConsideration

Software DesignConsideration

Vivado Design Suite Hardware

Design Flow

Software DesignFlow Overview

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1

(SDK) Vivado Documentation Navigator

Documentation Navigator v2015.1 Documentation Navigator

1. Design Hub View

2. Create Design Checklist

3. OK

4. 1-2 Title Page

https://china.xilinx.com/support/documentation/sw_manuals/c_xtp397-embedded-design-methodology-checklist.xlsx


1-2Documentation Navigator Embedded Design Methodology ChecklistUltraFast 8UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback

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1

Documentation NavigatorXilinx Documentation Navigator/ Documentation Navigator

Documentation Navigator Update Catalog

Documentation Navigator Design Hub View Design HubZynq-7000 PetaLinux SDKEmbedded Processor Design Support Resources Embedded Processor Design


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1 QuickTake QuickTake SDK SDSoC PetaLinux

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2

Zynq-7000 AP SoC

Zynq-7000 AP SoC

Zynq-7000 AP SoC

(Profiling) (Partitioning)UltraFast 11UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 Zynq-7000 AP SoC 60 / Zynq-7000 AP SoC (PL)

Zynq-7000 AP SoC

Zynq PL AXI IP PL (PS) PL PL PL UltraFAST ( Vivado Design Suite) (UG949) [ 16]

PS I/O PL PL Zynq ARM Cortex-A9 ARM DS-5 Development Studio [ 72]

Zynq

Zynq Zynq

Zynq AXI DMA Zynq

ARM CPU memcpy 4 KB DMA PS DMA PL 32 GP Zynq-7000 All Programmable SoC (UG585) [ 4] PS DMA PS DMA PL DMA 64 ACP HP PL

PS AXI IOP DMA IP GigE SDIO USB (DevC)Zynq-7000 All Programmable SoC (UG585) [ 4] IP Linux Zynq-7000 AP SoC PS PL UltraFast 12UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 PL (XAPP1082) [ 38] GigE

AXI PL ACPHP slave GP

ACP

PL

GP APU PL

DMA AXI4 AXI4 DMA AXI4-Stream FIFO AXI-Stream AXI AXI PL DMA

DMA

MIO EMIO SD GigE

OCML2 DDR PS ACP L2 DDR ACP PL L2 ACPHP DDR OCM PL 256 KB OCM L2 DDR

ARM PL Zynq ARM PL IP PL IP

PL Zynq-7000 AP SoC PL OS PL Amdahl

S 1- p TCF p

DMA p DMA p p (Profiling) (Partitioning)

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2 ARM Zynq PS PL

SCU (PS)SCU Linux clock_nanosleep

ARM (PS) ARM (PMU) Linux Perf ARM Streamline (SDK) 2014.2 ARM Cortex-A9 [ 75]

L2 (PS)L2 SDK Zynq-7000 All Programmable SoC (UG585) [ 4]

GigE (PS) Zynq-7000 All Programmable SoC (UG585) [ 4]

AXI (PL) PL AXI AXI AXI AXI [ 43]

AXI (PL) PL PL PL AXI / [ 44]

AXI (PL) PS AXI LogiCORE AXI [ 45]

PL

(SDK) Linux [ 50] Linux

SDK SDK HP ACP APM SDK

Zynq-7000 AP SoC

SoC

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2

SoC FPGA FPGA

2-1

Zynq-7000 AP SoC 2-2


2-1


2-2Zynq-7000 AP SoC

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2 PS PL PL PS PL PL 2-1 PS PL Zynq-7000 All Programmable SoC Z-7010Z-7015 Z-7020DC AC [ 28]

PS

Zynq-7000 AP SoC PS Zynq-7000 All Programmable SoC PCB (UG933) [ 14] 5 (PS)

PL

Zynq-7000 AP SoC PL

PL Zynq-7000 AP SoC PL Zynq-7000 AP SoC

2-1

PS VCCPINT 1.0V

VCCPAUX 1.8V I/O

VCCO_DDR 1.2V 1.8V DDR

VCCO_MIO0 1.8V 3.3V MIO 0, 0:15

VCCO_MIO1 1.8V 3.3V MIO 1, 16:53

VCCPLL 1.8V PLL

PL VCCINT 1.0V

VCCAUX 1.8V I/O

VCCO_# 1.8V 3.3V I/O

VCC_BATT 1.5V PL

VCCBRAM 1.0V PL RAM

VCCAUX_IO_G# 1.8V 2.0V PL I/O

XADC VCCADC 1.8V

GND UltraFast 16UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2

(PDS) PDS

PDS LC

PDS

PDS EMI

Zynq Zynq-7000 All Programmable SoC PCB (UG933) [ 14] 3

Zynq-7000 AP SoC Zynq-7000 AP SoC PS ARM Cortex-A9 CPU PL 7 28 nm (HPL) HPL

2-2 PL

VCCINT&

VCCBRAM

CLB RAM/FIFO DSP slice IOB (ILOGIC/OLOGIC) ISERDES/OSERDES MAC (DCM PLL) () MGT PCIE PCS

VCCAUX&

VCCAUX_IO

(MMCM DCM PLL) IODELAY/IDELAYCTRL VREF I/O HSTL18_I

VCCO (DCI) (OCT)

MGT PMA UltraFast 17UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 PS

Zynq-7000 AP SoC PS APU PS PLL SCU OCM

PS

(APU)Zynq-7000 AP SoC APU CP15 CPU

Zynq-7000 All Programmable SoC (UG585) [ 4]

PS PS PS DMASPIQSPISDIO DDR Zynq-7000 All Programmable SoC (UG585) [ 4] 25

L2 l2cpl310.reg15_power_ctrl

L2 L2 (WFI) WFI L2 WFI Zynq-7000 All Programmable SoC (UG585) [ 4] 3

WFI L2

(OCM) OCM Linux DDR OCM

(SCU)SCU mpcore.SCU_CONTROL_REGISTER SCU

CPU WFI

ACP

SCU

CPU WFI ACP SCU

PLLPLL PLL PLL PLL DDR PLL ARM I/O PLL DDR PLL

Zynq-7000 AP SoC DDR2 DDR3 LPDDR2 DDR 16 32 DDR DDR DDR

DDR

DDR ECC UltraFast 18UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 DDR

DDR LPDDR

DDR DDR DDR DDR

DDR Zynq-7000 All Programmable SoC (UG585) [ 4]

I/OI/O MIO DDR IO I/O Zynq-7000 All Programmable SoC PCB (UG933) [ 14] SelectIO

Linux

S0

S1 RAM

S3--RAM RAM

Zynq-7000 AP SoC Linux Zynq [ 64]

Zynq-7000 AP SoC CPU CPU CPU CPU

PL PL PL PS PL PL VCCINT VCCAUX VCCBRAM VCCO

PL PL

Zynq-7000 AP SoC PL

PL Zynq-7000 AP SoC CLB PL PL

CLB CLB

IP PS IP DSP48 slice RAM ROM

UltraFAST ( Vivado Design Suite) (UG949) [ 16]

FPGA RTL SR PL PL UltraFast 19UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 SR PL slice SR

LUT LUT FPGA

HDL I/O FPGA

LUT (SRL)LUT RAM RAM

(WP272) [ 32]

PL (fclk) (C) FPGA (V) ( )

= x fclk x C x V2 2-1

FPGA

Vivado

PL RAM DSP48 RAM DSP 2-3

PL

BUFGCE BUFGCE PL

PL BUFHCE BUFRCE PL


2-3



2 BUFGMUX_CTRL PL

PL FPGA

PL

PL

RAM

RAM RAM RAM RAM

RAM

2-4


2-4



2 PL 2-5

I/O

I/O I/O

I/O I/O HSLVDCI FPGA FPGA

Zynq-7000 AP SoC I/O (DCI) I/O DCI

Zynq-7000 AP SoC HSTL SSTL I/O DC

Zynq-7000 AP SoC

LC PLL XAUI PLL PLL PLL

RXPOWERDOWN TXPOWERDOWN PCIe D3 PLL

I/O

I/O

I/O I/O

I/O

PL 100%


2-5UltraFast 22UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 100%

I/O DC LVDS I/O LVDS LVCMOS LVDS

Zynq-7000 AP SoC

2-6


2-6FPGA Vivado UltraFast 23UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 Xilinx Power Estimator (XPE)

(XPE) XPE Zynq-7000 AP SoC XPE 2-7 I/O CPU XPE

XPE XPE

Zynq-7000 AP SoC 1 [ 61] Zynq-7000 AP SoC PS PL


2-7 Zynq-7000 AP SoC UltraFast 24UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 Vivado

Vivado GUI 2-8 Vivado

I/O PS IP RAM DSP

(VCD) (SAIF) Vivado VCD SAIF 0 1 X Z

Vivado PL Vivado

Vivado 30%

Vivado PL IP

RAM RAM

Vivado Design Suite (UG907) [ 10]


2-8Vivado UltraFast 25UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 PL PL PL

1.

Vivado GUI Vivado

2.

Vivado

3.

Vivado Design Suite (UG907) [ 10]

Vivado

Vivado

RAM

Vivado

Vivado Report Power Vivado Vivado Vivado Design Suite (UG907) [ 10]

(XPE)

Vivado XPE IP XPE Vivado XPE

UltraFast 26UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 Zynq-7000 AP SoC IP

PS_CLK

PS 3060 MHz PS_CLK LVCMOS MIO 0 I/O PS PLLARMDRM IO PLL

PS_CLK 33.3 MHz PS

LogiCORE IP 7 wizard PLL I/O PS_CLK SPI UART (FSBL) PS

U-Boot

Linux

PL (MRCC) PL bank I/O PL PS

PHY PHY 25 MHz I/O PHY / RX TX

PS

PS PLLCPU DDR I/O PLL CPU DDR PLL PS_CLK PS_CLK PLL PLL

CPU CPU_6x4xCPU_3x2xCPU_2x CPU_1x6:3:2:1 4:2:2:1 6:2:1 4:2:1 CPU DDR DDR_3x DDR_2x CPU I/O

PS - PL

PL AXI (AXI_HPAXI_ACP AXI_GP PS PL PS PL PS PL

PS PL (FCLK [3:0]) PS-PL ARM DDR I/O PLL FCLK UltraFast 27UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 FCLK FCLK PS - PL

FCLK PL IP

FCLK

FCLK PL

PL

FCLK PL

PL FCLK

PL FPGA

IP FCLK

- (MIG) FCLK MIG

- GT

PS Zynq-7000 All Programmable SoC (UG585) [ 4]

PL

PL FPGA (BUFG BUFR) (PLL) (MMCM) IP MMCM/PLL (DRP) AXI-Lite

Zynq-7000 PS_CLK PL FCLK FPGA

PS PS (PS_POR_B) PS PS power-good PS_POR_B (PS_CLK) 2,000 PS_POR_B VCCO_MIO0 PS_POR_B 100 s

PS RAM OCM Fifo bootROM PL PS_POR_B PS I/O

PS PS (PS_SRST_B) PS_SRST_B PS_SRST_B VCCO_MIO1 PS_SRST_B 1 s

PS (PS_SRST_B) (PS_POR_B) PS_SRST_B PS RAM bootROM PL PS_POR_B (boot-mode strapping) UltraFast 28UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 PS_SRST_B PS_POR_B PS_POR_B bootROM PS_SRST_B PS_SRST_B PS_POR_B PS_POR_B 52847 [ 68]

PL PS

SLCR PSS_RST_CTRL[SOFT_RST] PS_SRTS_B PS RAM PL

Watchdog watchdog Watchdog SWDT ARM Watchdog AWDT0 AWDT1 SWDT AWDT ARM CPU

CPU CPU A9_CPU_RST_CTRL[A9_RSTx] ARM CPU CPU JTAG PL

ARM DAP JTAG

SLCR AXI

PL PS PL (FCLK_RESET [3:0]) PL POR botROM PS PL

FCLK_RESET FCLK FCLK FCLK_RESET PS PL PL

FCLK_RESET proc_sys_reset IP PL IP

FCLK_RESET PL AXI IP IP AXI AXI UltraFast 29UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2

Zynq-7000 AP SoC MPCore (GIC) GIC nIRQ nFIQ

GIC CPU AXI

GIC GIC GIC GIC GIC

5

TrustZone Group 0 Group 1

(PPI) CPU GIC




2

PS PL PS Cortex-A9

PS

Cortex-A9

16 (SGI)

5 (PPI) PL FIQ IRQ AWDT

60 44 PS I/O 16 PL

4 PL GIC

WFE CPU CPU PL

PL

PL PS PL

PS 29 PS

PL PL AXI_GPIO EMIO GPIO SEV

ID

Zynq-7000 AP SoC IRQ ID #0 #95

IRQ ID #0#15

IRQ ID #16#31 IRQ ID #16#26 Zynq-7000 AP SoC IRQ ID #27#31

a. IRQ ID #27

b. IRQ ID #28 FIQ

c. IRQ ID #29

d. IRQ ID #30 AWDT

e. IRQ ID #31 IRQ

IRQ ID #32#95 IRQ ID #36 Zynq-7000 AP SoC IRQ ID #32#35 #37#95 31 (IRQ ID #32#62)

PS PL PS PL MicroBlaze Zynq-7000 AP SoC

PL ACP PL

PS UltraFast 31UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2

Zynq-7000 AP SoC PL PS PS PL PS DMA330

OCM

DDR Zynq-7000 AP SoC L2 (OCM) L1

FIQ IRQ

Zynq-7000 AP SoC Cortex-A9 ARM e (GIC) nFIQ nIRQnFIQ IRQ IRQ FIQ IRQ IRQ FIQ

TrustZone

Zynq-7000 AP SoC ARM TrustZone FIQ IRQ

OS OS

ACP Zynq-7000 AP SoC ACP PL

(AMP) UltraFast 32UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2

Zynq-7000 AP SoC Zynq-7000 AP SoC

(TrustZone)

Zynq-7000 AP SoC (AMP)

Zynq-7000 AP SoC Linux

Zynq-7000 AP SoC Zynq-7000 AP SoC PS PL PS PL

Zynq-7000 AP SoC (bootROM) PL Zynq-7000 AP SoC NORNANDSDIO Quad-SPI JTAG UltraFast 33UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 PS

2-10 PS X-Ref Target - Figure 2-10

2-10PS

Power On Reset(Debug access with JTAG disabled)

Internal memory hardware clean process (Optional OCM ROM CRC)

RSA authentication performed on FSBL

Load boot image header

AES decryption of FSBL(Decrypted FSBL loaded to OCM)

HMAC authentication of FSBL

Disable OCM ROM memory

Pass control to FSBL

Disable and LOCK all security features(AES and HMAC)

Load FSBL into OCM

Disable OCM ROM memory

Enable JTAG

Pass control to FSBL

Secure boot Non-Secure boot

RSA enabledUltraFast 34UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 bootROM CRC

bootROM FSBL bootROM 128 KB CRC CRC eFuse Zynq-7000 AP SoC eFusesZynq-7000 All Programmable SoC (XAPP1175) [ 40]

bootROM SDIO QSPI NAND NOR Zynq-7000 All Programmable SoC (UG585) [ 4]

FSBL RSA

bootROM RSA FSBL FSBL PS eFuse RSA FSBL FSBL Zynq-7000 AP SoC RSA Zynq-7000 All Programmable SoC (XAPP1175) [ 40]

(BOOT.bin)

PS

bootROM FSBL CPU

FSBL

U-Boot

ELF

Linux uImage

PL

(HMAC) PS PL (AES) Zynq-7000 All Programmable SoC (XAPP1175) [ 40] Zynq-7000 All Programmable SoC (UG1025) [ 20]

AES & HMAC

Zynq-7000 AP SoC PL AES HMAC PL PL bootROM PL PL PL

Bootgen

Bootgen BOOT.bin Bootgen Zynq-7000 All Programmable SoC (XAPP1175) [ 40] Zynq-7000 All Programmable SoC (UG821) Bootgen [ 7]

Zynq-7000 AP SoC

AES 256

HMAC UltraFast 35UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 RSA (PSK)

RSA (PPK)

RSA (SSK)

RSA (SPK)

AES HMAC Bootgen Bootgen key0 HMAC key0 HMAC Bootgen Vivado AES PL eFuse BBRAM

Zynq AP SoC RSA OpenSSL RSA OpenSSL OpenSSL RSA / RSA Zynq AP SoC

eFuse/BBRAM

RSA PPK PS eFuse PS eFuse AES PL eFuse BBRAM eFuse Secure Boot PL eFuse BBRAM Key Disable JTAG Chain Disable Vivado eFuse (OTP) eFuse (POR)

Zynq-7000 All Programmable SoC (XAPP1175) [ 40]

(Trust Zone) PS PL

ARM TrustZone

ARM TrustZone [ 74]

Zynq-7000 All Programmable SoC ARM TrustZone (UG1019) [ 19]

(AMP) (AMP) Zynq-7000 AP SoC ARM Cortex-A9 ARM Cortex-A9 ARM Cortex-A9 ARM Zynq-7000 AP SoC

Linux Linux Zynq-7000 AP SoC Linux Linux

Linux Android

Linux UltraFast 36UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 (Profiling) (Partitioning)

PL

PL

2-11


2-11

FunctionA

FunctionB

FunctionA

FunctionC

FcnD

FcnE

FcnF

FunctionC

FcnG

Timer

Program Execution

Profiler InterruptSignalsUltraFast 37UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 PS 2-11 2-12

SDK

SDK PL PL PL

SDK

TCF

SDK TCF TCF gprof

SDK PL AXI (APM) ARM (PMU) Zynq-7000 AP SoC PS L2 SDK JTAG 10




2 SDK Performance 2-13

Cortex-A9 CPU PMU

L2C-PL310 L2

APM HP ACP APM


2-13PL PerformanceUltraFast 39UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2

ARM Development Studio 5 (DS-5)

ARM Development Studio 5 (DS-5) ARM DS-5 ARM ARM Linux Android

Streamline ARM Development Studio 5 (DS-5) Linux Android Linux Streamline Timeline Call Paths Functions Code Call Graph Stack Analysis Logs

1ms 10ms Streamline Streamline

bootROM FSBL U-Boot 55572 [ 69]

100%

Top Linux CPU CPU CPU

CPU

SMP Linux CPU CPU0 CPU CPU irqbalance

Cyclictest Linux cyclictest

PL SoC UltraFast 40UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 Program Trace Module ( PTM)

PTM Program Flow Trace (PFT) PTM

PFT DS-5 PTM PTM

- PTM

Context-ID

PTM

Performance Monitor Unit ( PMU)

Cortex-A9 PMU 58

Level 2 (L2)

PL310 L2 L2

AXI Performance Monitor (AXI APM)

LogiCORE IP AXI IP PL PL AMBA AXI / (AXI4/AXI3/AXI4-Stream)

APM AXI CPU ARM CPU APM APM System Debugger

APM

AXI

AXI UltraFast 41UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 AXI FIFO /

slot /

/ PL

PL PL

PS AXI AXI_ACP AXI_HP slave AXI_GP

AXI-Stream FIFO

AXI-DMA

AXI-slave PS 2-14 X-Ref Target - Figure 2-14

2-14

M_AXI_GP

Register

Accelerator

AX

I-Lite IC

MainUltraFast 42UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 AXI-master PS 2-15

AXI FIFO 2-16

PL OCM DDR DMA 2-17

Zynq-7000 All Programmable SoC ZC702 (Vivado Design Suite 2014.2) (UG925) [ 13] 1080p60


2-15 AXI Master


2-16 FIFO


2-17 DMAUltraFast 43UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


2 DMA DDR DDR DMA UltraFast 44UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3

Zynq-7000 AP SoC

16 32 DDR DDR ECC

Zynq-7000 AP SoC (APU)

IP IP IP

AXI AXI AXI

(PS) PS (PL)

PL PL PL

ACP ACP PL L1

PL HP PL DDR (OCM) HP

FPGA

GP APU PL GP APU PL

Zynq-7000 AP SoC bootROM QSPISDNANDNOR JTAG Zynq-7000 AP SoC eMMC PCIe JTAG

Zynq-7000 AP SoC NAND NOR (FSBL)bootROM FSBL

PS_POR_B PS PLL PS bootROM ARM FSBL OCM OCM FSBL JTAG QSPI/NOR FSBLUltraFast 45UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 3-1

Zynq-7000 AP SoC JTAG JTAG

Zynq-7000 AP SoC

QSPI

NAND

NOR

SD

JTAG

Zynq-7000 AP SoC

eMMC

PCIe USB UART FPGA

bootROM

Zynq-7000 AP SoC bootROM (IMPACT SDK) U-Boot Linux 50991 [ 67]

QSPI NAND NOR

NAND SD QSPI NOR

QSPI

NAND

3-1




3

QSPI

bootROM (0xAA995566) (0x584C4E58) QSPI I/O QSPI SD Zynq-7000 AP SoC QSPI NAND QSPI 16 MB 32 MB QSPI I/O 16 MB bootROM QSPI QSPI

Zynq-7000 AP SoC 50991 [ 67]

NAND

NAND NAND 1 GB QSPI NAND QSPI NAND

ECC Spansion (S34) NAND NAND ECC ECC

NOR

Zynq-7000 AP SoC NOR NAND NOR QSPI MIO NOR 40 MIO 64 MB

Zynq-7000 AP SoC 50991 [ 67]

3-1

XIP /

QSPI 7 8 13

16 MB 32 MB

16 MB/ - eMMC SD

/ 16 MB I/O QSPI 128 MB QSPI

NAND X814X1622

128 MB

ECC JFFS2 UBIFS ECC 1-bit ECC

/ 1 GB

SD 6 /

NOR 37 QSPI

/ 64 MB

eMMC 6 eMMC / UltraFast 47UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 SD

SD NAND SD QSPI SD eMMC SD bootROM ARM_CLK_CTRL (0x1F000200) CPU 2 SD

JTAG

JTAG JTAG ARM DAP PL TAP PL JTAG PL PL TAP EMIO JTAG ARM DAP PL PL TAP

eMMC

QSPI QSPI eMMC FSBL QSPI eMMC25 MHz SDIO eMMC

PCIe Ethernet USB UART FPGA

PCIeUSBUART FPGA PCIe

PCIe PCIe PCIe Zynq-7000 AP SoC PL PCIe PCIe QSPI NAND NOR FSBL FSBL FSBL PCIe U-Boot

PCIe 7 PCIe IP I/O (PIO) APU CPU PL PS GP

FSBL

APU FSBL

PIO FSBL

APU bitDone

PIO bitDone U-Boot.elf PL RAM

U-Boot.elf U-BootDone

APU U-BootDone PS DDR

Linux

eMMC SD (FTL) OS FAT ext3

NAND QSPI NORLinux (MTD) Linux MTD JFFS2 UBIFS UltraFast 48UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3

bootROM bootROM Zynq-7000 All Programmable SoC (UG585)[ 4] 55572 [ 69] Bootgen Zynq-7000 All Programmable SoC (UG821) [ 7] BootgenZynq-7000 All Programmable SoC (UG585) [ 4] bootROM

QSPI 100 MHz PS QSPI ZC702

U-Boot Linux 667 MHz PS 32 MB Spansion 3036 PS 64 MB Spansion 2994 QSPI QSPI PS 41

PS 667 MHz PS 32 MB Spansion 3036 QSPI PS 867 MHz 2523 QSPI PS 667 MHz 867 MHz 513

DDRZynq-7000 AP SoC DDR 1.8V VDDR21.2V LPDDR21.5V DDR3 1.35V DDR3L 16 32 16 32 7z010 CLG225 16 ECC 32 16 10 ECC 16 1 GB DDR ECC 512 MB

DDR AXI (DDRI) (DDRC) PHY (DDRP) Zynq-7000 All Programmable SoC (UG585) [ 4]

PHY I/O Zynq-7000 AP SoC DDR3 666 2/3 MHz DDR3 533 MHz

Data transfer rate = 666 2/3 MHz * 2 bits (for double data rate) = 1333 Mb/s per data IO

32 42.6 Gb/s 5.3 GB/s 3-2 DDRI DDRI 4 64 AXI AXI AXI FIFO S0 L2 PLCPU ACP P1 PS AXI GP PL AXI_HP 2 3 3-2

5.3 GB/s DDR DDR DDR Zynq-7000 All Programmable SoC (UG585) [ 4] DDR // UltraFast 49UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback

https://china.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug585-Zynq-7000-TRM.pdf;a=xDDRMemoryControllerhttps://china.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug585-Zynq-7000-TRM.pdf;a=xDDRMemoryControllerhttps://china.xilinx.comhttps://china.xilinx.com/about/feedback.html?docType=User_Guides&docId=UG1046&Title=UltraFast%20%26%2323884%3B%26%2320837%3B%26%2324335%3B%26%2335774%3B%26%2335745%3B%26%2326041%3B%26%2327861%3B%26%2325351%3B%26%2321335%3B&releaseVersion=2.2&docPage=49

3 PL AXI HP AXI DDR 3-2 AXI_HP DDR 4 PL AXI_HP S2 S3 PL AXI AXI_HP0 AXI_HP2 AXI_HP1 AXI_HP3 DDR 2 3 Linux AXI_HP 50% Zynq-7000 All Programmable SoC (XAPP792) [ 34]

DDRC DDR DDR Zynq-7000 All Programmable SoC (UG585) [ 4]DDR DDRC

DDR DDRP DRAM Zynq-7000 All Programmable SoC (UG585) [ 4]DDR

Zynq-7000 AP SoC DDR PS DDRC 46778 [ 65] DDR DDR SDK FSBL PS bootROM DDR


3-2DDR AXI_HP

S0 S1 S2 S3

M0 M1 M2

AXI_HPto DDR

Interconnect

AXI HP0 AXI HP1 AXI HP2 AXI HP3

S0 S1 S2 S3

CPUs and ACP

Other Bus Masters

DDRMemory

Controller

DDR InterfaceDDR Core

DDR PHY

to OCM

DDR DRAM MemoryDevices

16 or 32 bits

Zynq Device BoundaryUltraFast 50UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback

https://china.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug585-Zynq-7000-TRM.pdf;a=xDDRMemoryControllerhttps://china.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug585-Zynq-7000-TRM.pdf;a=xDDRMemoryControllerhttps://china.xilinx.comhttps://china.xilinx.com/about/feedback.html?docType=User_Guides&docId=UG1046&Title=UltraFast%20%26%2323884%3B%26%2320837%3B%26%2324335%3B%26%2335774%3B%26%2335745%3B%26%2326041%3B%26%2327861%3B%26%2325351%3B%26%2321335%3B&releaseVersion=2.2&docPage=50

3 QSPIPS QSPI QSPI NOR NAND (XIP) CPU QSPI DDR OCMZynq-7000 AP SoC - [ 59] ZC702 XIP Hello World

Zynq-7000 AP SoC QSPI QSPI FSBL eMMC SD Zynq-7000 All Programmable SoC (UG821) [ 7] eMMC

QSPI I/O SPI QSPI AXI QSPI 24 QSPI 16 MBbootROM QSPI XIP QSPI FSBL QSPI XIP bootROM FSBL QSPI FSBL OCM XIP QSPI bootROM FSBL OCM FSBL 192 KB OCM OCM FSBL

I/O TXD RXD I/O QSPI QSPI 128 MB QSPI I/O Zynq-7000 All Programmable SoC (UG585) [ 4] Quad-SPI I/O

QSPI 16 MB Zynq-7000 AP SoC QSPI bootROM 0x0 16 MB 57744 [ 70]

RSA XIP 16 MB 0x0 0x0+32K 0x0 0x0+16 MB X1 QSPI

QSPI QSPI QSPI X1 X2 X4 LQSPI_CFG QSPI PS QSPI LQSPI_CFG Zynq-7000 AP SoC 50991 [ 67]

bootROM bootROM (X1) (X4) (X2) bootROM I/O QSPI X1 bootROM LQSPI_CFG Zynq-7000 All Programmable SoC (UG585) [ 4] QSPI

40 MHz QSPI QSPI QSPI Zynq-7000 All Programmable SoC (UG585) [ 4] QSPI QSPI

QSPI U-Boot Linux iMPACT SDK

QSPI Zynq-7000 All Programmable SoC (UG585) [ 4] QSPI UltraFast 51UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback

https://china.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug821-zynq-7000-swdev.pdf;a=xeMMCFlashDeviceshttps://china.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug585-Zynq-7000-TRM.pdf;a=xQuadSPIFlashControllerhttps://china.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug585-Zynq-7000-TRM.pdf;a=xBootAndConfigurationhttps://china.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug585-Zynq-7000-TRM.pdf;a=xQuadSPIFlashControllerhttps://china.xilinx.com/cgi-bin/docs/ndoc?t=user_guides;d=ug585-Zynq-7000-TRM.pdf;a=xQuadSPIFlashControllerhttps://china.xilinx.comhttps://china.xilinx.com/about/feedback.html?docType=User_Guides&docId=UG1046&Title=UltraFast%20%26%2323884%3B%26%2320837%3B%26%2324335%3B%26%2335774%3B%26%2335745%3B%26%2326041%3B%26%2327861%3B%26%2325351%3B%26%2321335%3B&releaseVersion=2.2&docPage=51

3

NAND NAND NAND NOR SRAM QSPI NOR NOR QSPI 16 MB NOR QSPI 26 NOR 64 MB 16 MB QSPI bootROM 16 MB bootROM FSBL OCM DDR QSPI I/O 128 MB NOR 64 MB 40 QSPI 128 MB 8 QSPI NOR

NAND Zynq-7000 All Programmable SoC (UG585) [ 4]

NAND

NAND NOR NAND 8 16 I/O // 1 GB NAND NAND 1.0

ECC NAND 1 ECC ECC

1 ECC ECC ECC NAND Zynq-7000 AP SoC (SLC) ECC (MLC) x8 x16 NAND 128 MB 1 GB Spansion NAND Zynq-7000 AP SoC 50991[ 67]

NAND Zynq-7000 AP SoC bootROM 128 MB 128 MB

NAND AC Zynq-7000 AP SoC NAND AC SMC CS0 3-3 UltraFast 52UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 CS0 NAND SDK PS smc.SET_CYCLE

bootROM PS smc.SET_CYCLE NAND Zynq-7000 All Programmable SoC (UG585) [ 4] NAND

NAND NAND Linux (MTD) MTD API API MTD JFFS2 UBIFS ext2 ext3 FAT JFFS2 MTD UBIFS UBI MTD NAND

Zynq-7000 AP SoC PS APU AMBA AHB APB USB CAN UART SPI

Zynq-7000 AP SoC

PS

PL

PS ASSP PL PS PL

PS (AMBA) AMBA ARM Cortex-A9


3-3SMC UltraFast 53UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 ARM TrustZone Pl PL

3-4 PS

PS

USB

PS USB USB 2.0

On-The-Go (OTG)

USB ULPI PHY MIO 8 SDR ULPI PHY USB ULPI PHY Zynq-7000 AP SoC USB


3-4PS

2X UART

Memory PeripheralsQSPI, NAND, NOR

Central Interconnect

DDR Controller

SWDT

TTC

SLCR

2X USB

2X GEM

2X SDIO

2X CAN

2X SPI

2X I2C

GPIO

APU

L1/L2 CacheOCM

EMIO

MIO

Processing System 7

PL Master/Slave PL Master

PL InterconnectUltraFast 54UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 EMIO PL SelectIO USB DMA FIFO AHB

Zynq-7000 All Programmable SoC (UG585) [ 4] USB OTG

DMA USB2.0 ULPI PHY

USB

AHB CPU_1x

USB ULPI PHY 60 MHz

USB

PS APB USB

GPIO ULPI PHY

OTG USB

USB USB OTG USB Linux USB 512 1024

MAC (GEM) 10/100/1000 Mb/s IEEE802.3-2008 MAC GEM MIO RGMII GMII EMIO PL

PL EMIO GMII

Zynq-7000 AP SoC GEM MAC PHY

DMA AHB FIFO MIO EMIO FIFO RGMII GMII PHY

MAC

PHY MDIO MDIO PHY

GEM CPU IEEE 1588 (PTP) PTP PTP

DMA PL PL IP

GEM PL AXI MAC IP AXI DMA IP PS DDR GEM 3.3V I/O Zynq-7000 All Programmable SoC (UG585) [ 4] UltraFast 55UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback

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3 SDIO

SD/SDIO SDIO SD MIO SDIO MIO PL EMIO SelectIO 802.11 GPSWiMAX SD SDIO

SD/SDIO SDMA DMA ADMA1 4 KB DMA ADMA2 SD 2.0 A2 ADMA2 32 - DMA SD1 SD4 SPI SD (SDHS) SD (SDHC) SD2.0/SDIO 2.0 [ 89]

SD/SDIO AHB ARM DMA FIFO SD/SDIO MMC 3.31

SD/SDIO DMA AHB FIFO APU SD

SD (FTL) NAND FTL ECC FAT EXT2 ext3 Zynq-7000 AP SoC SD SD SD eMMC eMMC (BGA) SD eMMC Zynq-7000 AP SoC SD eMMC eMMC QSPI

CLK CMD (CDn) SD (WPn) Cdn Wpn

SD/SDIO Zynq-7000 All Programmable SoC (UG585) [ 4] SD/SDIO

UART

UART I/O

UART FIFO

APU APB Rx Tx 64 FIFO APB FIFO MIO/EMIO FIFO APB

Rx Tx FIFO RxD TxD FIFO Rx Tx

Zynq-7000 AP SoC UART FSBL U-Boot UltraFast 56UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback

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3 FSBL UART UART TX RX TX RX PMOD UART1

UART USB USB-to-UART USB Zynq-7000 AP SoC UART 3-5 PC COM Zynq-7000 AP SoC

3-6 Cypress USB-to-UART Zynq-7000 AP SoC UART TxD RxD MIO Cypress COM (VCP) CY7C64225 USB-to-UART COM TeraTerm HyperTerm

Silicon Labs CP2103GM USB-to-UART Zynq-7000 XC7Z020 All Programmable SoC (UG850) [ 8] ZC702

UART MIO 8 UART EMIO UART Zynq-7000 All Programmable SoC (UG585) [ 4] UART

CAN

PS CAN 1 Mb/s 64 FIFO 16


3-5 USB-to-UART Zynq-7000 AP SoC UART PC

3-2CY7C6

EPP EPP UART CY7C6 CY7C64225 UART

D11 (MIO bank 1/501) TX USB_1_RXD 23 RXD

C15 (MIO bank 1/501) RX USB_1_TXD 4 TXD


3-6 Cypress USB-to-UART UltraFast 57UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback

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3

CAN APB CAN MIO PL EMIO CAN

APB Zynq-7000 All Programmable SoC (UG585) [ 4] CAN

I2C

I2C (SDA) (SCL) ACK/NACK I2C EEPROMI/O A/D D/A I2C (SMBus) (PMBus ) (IPMI)

Zynq-7000 AP SoC I2C I2C 100 Kb/s 400 Kb/s 7 10

I2C I2C ACK

[7:3] HOLD I2C HOLD

APB I2C I2C SCL SDA EMIO Pl MIO EMIO SCL SDA I/O PL I/O I2C NACK NACK Zynq-7000 All Programmable SoC (UG585) [ 4] I2C

SCL SDA Zynq-7000 AP SoC I2C [ 76] +5 V +3.3 V I2C Zynq-7000 AP SoC I/O / SDA SCL PCB 500 ps

I2C I2C I2C I2C I2C I2C I2C I2C 3-7 1:8 I2C PCA9548A 8 I2C [ 88]UltraFast 58UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback

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3 U-Boot Linux I2C FSBL Linux Linux I2C [ 52]

SPI

SPI SCLK MISO MOSI SS / SPI A/D D/A EEPROM LCD JTAG SPI

Zynq-7000 AP SoC 2 SPI

3 8 3 8 SPI

32 128 TX/RX FIFO FIFO APB SPI I/O FIFO I/O Zynq-7000 All Programmable SoC (UG585) [ 4] SPI

SPI 8 SPI 10 16

SPI SPI[01] MIO EMIO PL EMIO I/O PL I/O SPI PL SPI SS[1 2] SS0 I/O MIO SCLK 50 MHz I/O EMIO SCLK 25 MHz


3-7I2C UltraFast 59UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback

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3 3-8 SPI MIO SS0 EMIO SS0 (SSn) SS SS0 Vcc

EMIO EMIOSPIxSSON0 PL EMIOSPIxSSIN Vcc SS0 SS0 Mode_Fail SPI 47511 [ 66]

3-9 SPI MIO SS0

SCLK MISO MOSI SS PCB SCLK MISOMOSI SS 50 ps


3-8 SPI SPI


3-9 SPI SPI

SPI Master Controller

MIO

SCLKMOSIMISO

SS0SS1SS2

MISO Slave 0SS0

MOSISCLK

Slave 1SS1

Slave 2SS2

External DevicesVCCUltraFast 60UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 U-Boot Linux SPI MIO FSBL EMIO Linux Linux SPI [ 53]

GPIO

GPIO / GPIO LED DIP EMIO GPIO PL FCLK_RST EMIO PL 64 64 64 64 GPIO

GPIO bank bank 0 32 bank 1 24 bank 54 GPIO MIO bank 2 3 32 EMIO 64 GPIO PL GPIO PS PL

GPIO bank GPIO GPIO GPIO

MIO [87] GPIO 7 8

I/O MIO PL I/O

Linux GPIO FSBL Linux Linux GPIO [ 51]

Cortex-A9

Cortex-A9 SWDT TTC

(SLCR) APU PL SLCR SLCR

PS DMA

PS DMA PS-PL PS PL DDROCM QSPI SMCPL M_AXI_GP

DMA PL Cortex-A9 DDR PS PL DMA

DMA CPU PS DMA CPU DMA Zynq-7000 All Programmable SoC (UG585) [ 4] DMA

XADC

XADC 12 1-MSPS ADC ADC I/O (Vauxn/P) (Vp/Vn) 1 MSPS 500 kHz 250 kHzUltraFast 61UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 XADC ADC XADC Zynq-7000 AP SoC

XADC XADC PS

XADC

XADC ADC

(XADC) Zynq-7000 (PS) (XAPP1172) [ 39]

XADC AXI Zynq-7000 AP SoC (XAPP1182) [ 41]

3-10 DRP JTAG-DRP XADC LogiCORE IP XADC XADC PS AXI_GP 32 AXI PS 1 Mbps AXI XADC LogiCORE IP PL XADC XADC AXI Zynq-7000 AP SoC (XAPP1182) [ 41] 1MSPS

PS_XADC PL FPGA XADC DRP XADCIF_CMDFIFO XADCIF_RDFIFO DRP JTAG FIFO XADC (XADC) Zynq-7000 (PS) (XAPP1172) [ 39] 100 kHzPL-JTAG PS-XADC UltraFast 62UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 X-Ref Target - Figure 3-10

3-10XADC UltraFast 63UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3

AMBA APU USBGEMSDIO SPI

APB APU

AHB DMA

3-11 APU 3-11 DMA X-Ref Target - Figure 3-11

3-11

DMA

Register Interface

InterfaceDriverProtocol Engine

AHB Bus

APBBusUltraFast 64UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3

Zynq-7000 AP SoC GEM RGMII PHY MIO 1000BASE-X PHY EMIO

1. PS GEM RGMII 1000BASE-X

2. Cortex-A9 TrustZone

3. GEM TCP CPU

3-12

PS

Vivado IP GEM0 MIO GEM1 EMIO GEM1 EMIO GMII PS IP IP 1000BASE-X IP GEM1 EMIO Vivado Design Suite Zynq-7000 AP SoC PL PS PL (XAPP1082) [ 38]


3-12GEM

Programmable Logic

Processing System 7

UART

Central Interconnect

GEM0

GEM1

APU

GIC

DDR Controller

1000BASE-X

GTX

EMIO

PS-PL Interconnect

MIO

SFP ConnectorUltraFast 65UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3

GEM TCP CPU APB GEM

GEM GEM DMA DMA MAC

DMA

IP (IP) SoC IP CPU AMBA AXI IP Zynq-7000 AP SoC IP Vivado IP

IP

IP FPGA RTL (HDL) HDL

PS IP PS IP

SoC Zynq-7000 AP SoC I/O GHz ppm

IP Aurora IP AXI4 AXI4 UltraFast 66UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 3-13 Aurora IP ZYNQ-7000 AP SoC

IP IP Zynq-7000 AP SoC MicroBlaze IP IP

System Generator

System Generator FPGA MathWorks Simulink DSP IP System Generator DSP

Vivado Design Suite IP System Generator IP Vivado IP IP IP System Generator

HDL Coder

HDL MathWorks MATLAB Simulink HDL MATLAB/Simulink MATLAB/Simulink HDL

MATLAB Simulink HDL HDL


3-13Aurora IP UltraFast 67UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 Vivado

Vivado (HLS) FPGA C RTL Vivado HLS 3-14

Vivado HLS RTL

IP Vivado IP ZIP

(.dcp) Vivado Design Suite Vivado

System Generator for DSP DSP Vivado System Generator

System Generator for DSP (ISE) DSP ISE System Generator

EDK Pcore Platform Studio

RTL

IP IP IP IP

IP

: IP IP IP IP IP


3-14Vivado HLS

RTL Export RTL Simulation

Constraints/Directives

C, C++, OpenCL Kernel,

System CTestbench

Verilog/VHDL RTL Wrapper

X14136-073117

Vivado HLSUltraFast 68UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 IP HDL HDL Vivado IP IP IP IP

: IP IP AMBA IP IP IP

AXI4-Lite PS AXI4 IP AXI4-Stream AXI DMA AXI4-LiteAXI4 AXI4-Stream AXI DMA PS AXI4-Stream IP PS AXI4-Lite AXI DMA

IP IP HDL HDL AES HDL

IP PS PS PL AMBA IP PS-PL GP AXI3 AXI4 PS IP PL (HP) AXI3 AXI4 IP AXI3 ACP ACP AWAWCACHE ARCACHE ACP IP ACP

ACP L2 CPU PL IP

AXI3/4 AXI4 AXI3/4 /AXI4

IP Zynq AP SoC PL

1. IP AXI3/4 PS-PL AXI AXI3 AXI IP AXI4 IP PS-PL

2. IP IP IP


3-15AXI4-Lite AXI4 Memory-Mapped AXI4-Stream UltraFast 69UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 3. PS-PL

4. AXI4 IP AXI4 IP HP DMA IP IP PS DDR

IP IP IP IP

DSP IP RTD

Zynq-7000 AP SoC PL ADC XADC IP XADC AXI4-Strem XADC IP

Zynq-7000 AP SoC DSP48 IP IP AXI4 AXI4-Lite AXI4-Stream XADC IPAXI4-Lite PS GP0 IP

3-16 IP

IP

1. HDL AXI4 AXI4-Lite AXI4-Stream

2. Vivado IP HDL

3. IP XACT

4. Vivado

5. IP IP UltraFast 70UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 6. Vivado Design Suite

Zynq-7000 AP SoC PL AXI AXI AXI

PL AXI Zynq-7000 AP SoC IP PL ARM AMBA AXI IP Zynq-7000 AP SoC Zynq-7000 AP SoC

32 ACP 130% 262%

Zynq-7000 AP SoC IP AXI AXI IP


3-16IP UltraFast 71UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 AXI AXI AXI AXI

AXI #1 32 AXI-Lite AXI ZC702 100 MHz

AXI #2 64 AXI 4 16 16 Zynq-7000 AP SoC 200 MHz

AXI AXI #1 AXI #2 AXI AXI AXI

AXI AXI

AXI

IP AXI IP

AXI Zynq-7000 AP SoC AXI

3-17

AXI AXI rdlast wrlast AXI Zynq-7000 AP SoC AXI

AXI AXI AXI AXI DDR DDR DDR OCM


3-17 HP UltraFast 72UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 L2 AXI

Zynq-7000 AP SoC 64 16 AXI3 AXI PS PL PS PL AXI AXI4 PS AXI3

AXI PL Zynq-7000 AP SoC AXI OCML2 DDRC PL (MIG)

OCM GPHP ACP ARM PL 256 KB OCM

L2 PL ACP 512 KB L2 ARM Cortex-A9 512 KB CPU ACP ACP

DDR DDRC DDR3 LPDDR2 PL AXI GPHP ACP DDRC PL DDRC DDRC OCM L2

MIG PL PL Zynq-7000 AP SoC MIG IP PL DDRC MIG AXI AXI IP bank PHY

AXI

AXI CPU AXI Zynq-7000 AP SoC

ACP ACP L2 HP DDRC GP OCM ACP HP

OCM ACP L2

PL PS DDRC HP DDRC L2 HP DDRC DDRC L2 QoS301

PL MIG Zynq-7000 AP SoC MIG ZC706 MIG Zynq-7000 AP SoC DDRC

PS PL GP0 GP1 PL AXI PS

AXI

ACP

PL

GP APU PL UltraFast 73UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3

ACP HP AXI4 ACP L2 ARM Cortex-A9 ACP PL Cortex-A9 L2 ACP CPU AXI - DMA L2

HP 32 64 DDRC HP FIFO HP OCM OCM PL

GP ACP HP GP PL

ACP DDRC ACP Zynq-7000 AP SoC ACP 53%HP GP L2 ACP ACP

PS QoS-301 DDRC IP QoS-301 QoS-301 DDRC AXI L2 DDRC QoS-301 L2 DDRC HP DDRC DDRC DDRC

3-18 AXI (APM) PL AXI IP AXI

Zynq-7000 AP SoC APM IP PL


3-18 Vivado 2013.4 IP AXI UltraFast 74UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 Zynq-7000 AP SoC PS PS DDR APU PS DDR PS PL PS PS-PL AXI ACP Zynq-7000 All Programmable SoC (UG585) [ 4]

Zynq-7000 AP SoC PS DDR APU DDR OCM PS-PL PL AXI PL PS

3-19

PS PS PS DDR APU PS DDR PS

64 ARM NIC-301 PS I/O PLHP DDR OCM RAM

; Zynq-7000 All Programmable SoC (UG585) [ 4]



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3 APU PS-DDR

64 AXI AXI SCU OCM L2 APU SCU L2 DDR SCU L2 SCU PL APU ACP OCM CPU L1

L2 DDR

PS PS-DDR

I/O USB GEM SDIO

APB APU

AHB DMA

APB AHB DMA DDR

PS-PL AXI PS-PL AXI PL PS

AXI (AXI_GP)

AXI_GP 32 ;PL PS PS

AXI_GP

M_AXI_GP PL S_AXI_GP PL PS PL S_AXI_GP PS-DDR

(ACP)

ACP SCU PL PL L1 L2 OCM ACP CPU Zynq-7000 All Programmable SoC (UG585) [ 4]

ACP SCU I/O ACP CPU L1 L1 L2

ACP PL-DMA CPU CPU

ACP ACP ACP

ACP ACP CPU PS

(AXI_HP)

AXI PL PS DDR OCM 32 64 PS AXI-HP DDR FIFO AXI FIFO (AFI) UltraFast 76UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback

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3 AXI HP HP port-0 port-2 DDR

HPAXI QoS FIFO PL APB QoS

PS-PL AXI PS-PL

a. MIO I/O PL PS IOP PL PL Zynq-7000 All Programmable SoC (UG585) [ 4]

b. PS-PL PL Zynq-7000 All Programmable SoC (UG585) [ 4]

c. PS PLZynq-7000 All Programmable SoC (UG585) [ 4]

d. PS PL DMA PL IP PS PS CPU

PS-PL AXI

PS PL PL S_AXI_GP PL PL HP

PL CPU L1

PL DDR OCM HP PL PL HP HP HP0 HP2 HP1 HP3 PL

Zynq-7000 AP SoC (UG585) [ 4]

PL Zynq-7000 AP SoC PL PL

PS (FCLK)

GT

MMCM

PS (FCLK) FCLK UltraFast 77UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback

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3 GT GT (CDR) PL PL CDR 3-20

7 FPGA GTX/GTH (UG476) [ 2] 7 FPGA GTP (UG482) [ 3]

FPGA I/O PL P

P N I/O

3-21

7 FPGA (UG472) [ 1]


3-20CDR UltraFast 78UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 MMCM MMCM MMCM 3-22

MMCM MMCME2_ADV (DRP)


3-21


3-22MMCM UltraFast 79UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 FCLK FCLK 3-23

IP

(TPG)

(VTC) TPG

(VDMA) TPG DDR

: HP2 DDR

PS

MMCM FCLK Sys_clk VDMA AXI

PL Sys_clk MMCMPS AXI HP/GP PL


3-23FCLK UltraFast 80UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 ACP PL ARM Cortex-A9 CPU ACP APU CPU ACP APU CPU ACU 3-24 ACP

PL ACP CPU 512 KB L2 Zynq-7000 AP SoC PL ACP CPU GP ACP PL ACP- AXI ACP A*CACHE A*USER 1

PL HP GP DDR CPU DDR ACP

ACP ACP AXI CPU L2 L1 CPU ACP AXI L2 DDR CPU


3-24ACP UltraFast 81UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 CPU CPU ACP

ACP ACP Zynq-7000 AP SoC ACP

ACP-

512 KB L2 ARM ACP ACP ACP

ACP ACP 54%

AXI ACP ACP AXI3 64 ACP AXI3 AXI4 64 16 AXI IP 64 ACP ARM [ 73]

ACP / axresp DMA

ACP - -

ACP PL HP GP AXI 4 ACP Cortex-A9 [ 75] 2.4

ACP PS

L2 L2 CPU ACP PL L2 L2 ACP L2 DDR

ACP PS L2 Zynq-7000 All Programmable SoC (UG585) [ 4]

CPU

CPU CPU CPU L1 ACP ACP

ARM Cortex-A9 ACP L2 4 KB

CPU L1 Dhrystone CoreMark ACP L2 512 KB

CPU ACP ARM Zynq-7000 AP SoC L2 [ 60]UltraFast 82UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 ACP L2 CPU ACP L2 ARM (PMU) PL AXI ACP

PL HP PL DDR (OCM) Zynq-7000 AP SoC HP HP

HP PL OCM DRAM DDR 3-25 HP PS PS HP


3-25 (HP) UltraFast 83UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 HP HP HP HP HP

HP0HP2HP1 HP3HP DDR

HP HP0 HP2 HP0 HP1 15%

HP PL AXI HP HP HP HP HP DDRC

AXI DRAM / Zynq-7000 All Programmable SoC (XAPP792) [ 34] DRAM --/

HP0 HP2 HP2 HP0 0.12%

PL PL DDR PL 3-25 PL PL PS DDRC DDRC PL

HP 533 MHz DDR PL 50 MHz 100 MHz HP 92% 100 MHz 200 MHz HP 13% PL DDR

HP PS HP DDR DRAM HP DDR L2 DDR L2 L2 CPU ACP 512 KB L2 CPU ACP DDRC HP DDRC USB

L2 DDRC HP HP

DDRC

PS QoS-301

HP DDR PS HP

DDR DDR DDR PHY go2critical DDR DDR DDR HP HP Zynq-7000 AP SoC DDR Zynq-7000 All Programmable SoC (UG585) [ 4]

QoS-301 L2 DDR AXI QoS-301 Vivado GUI DDR L2 Zynq-7000 All Programmable SoC (UG585) [ 4] UltraFast 84UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback

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3 DDR ACP HP DDR L2 CPU ACP CPU ACP 512 KB L2 USB DDR

HP L2 HP L2 PL AXI HP

DDR DDR ZC702 533 MHz 32 DDR 4.3 Gb/s DDR DDR

PL (MIG) DDR PL HP DDR PS GP 58387 [ 71]

MIG PS CPU PL DDR 32 GP MIG PS DDR HP

Zynq-7000 AP SoC PS

Zynq-7000 AP SoC

(XADC) PL XADC JTAGDRP PS-XADC JTAG DAP 7 FPGA PS-XADC Zynq-7000 AP SoC UltraFast 85UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 3-26 XADC AXI XADC DRP PL-JTAG PS-XADC

TrustZone ARM TrustZone Zynq-7000 AP SoC PS

3-27 TrustZone PS APU L1 SCUSLCRwatch-dog I2CGPIOSPICANUARTQSPINORDDR L2 AXI DMAC SDIO USB


3-26XADC




3 DDR

64 MB DDR TZ_DDR_RAM (0xF8000430)

0

1

DDR DECERR DDR

L2

L2 NS TrustZone L2

DDR (ECC) 16 DDR DDR 16 ECC ECC ECC DDR ECC DDR ECC ECC DDR ECC ECC

AXI AXI SLVERR AXI PS AXI L2 DMA CPU AXI SLVERR PS AXI

Zynq-7000 AP SoC PL CPU PS PLL I/O

PL PL PL PL PL

PS

(SLCR) 0xF8000000

SPI SPI_CLK_CTRL (0xF8000158) UltraFast 87UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 3-28 SPI

FPGA FPGA

Documentation Navigator

FPGA

SRAM FPGA

Zynq-7000 AP SoC PL LUTDSP48 RAM (PCAP) / Vivado PCAP

3-29


3-28

IO PLL

ARM PLL

DDR PLL

6-bit ProgrammableDivider Clock Gate

SPI_CLK_CTRL [5:4]

SPI_CLK_CTRL [13:8] SPI_CLK_CTRL [0:1]

SPI Ref Clock

X14148-073117UltraFast 88UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback


3 Zynq-7000 AP SoC PL (PCAP) PL PCAP PS PCAP PCAP APB APB PCAP / CPU Vivado PCAP PL

FPGA FPGA

Vivado Documentation Navigator

Vivado

Vivado


3-29

StaticLogic

Input

Communication Macro

Output

PR1PR1

PR2

PR3

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3

FPGA CLB RAM RAM DSP 20% PL

3-30 X-Ref Target - Figure 3-30

3-30

RTL Module 1 System RTL Module 2

Implementation Implementation

Bitgen Program Bitgen Program

Static BitstreamPartial Bitstream Partial Bitstream

Synthesis

RM 1 RM 2Static DesignUltraFast 90UG1046 (v2.2) 2017 7 27 china.xilinx.com Send Feedback

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Documents

UltraFast 嵌入式设计方法指南(UG1046)