UNIVERSITI PUTRA MALAYSIA

DEVELOPMENT OF A MULTI-STANDARD PROTOCOL USING SOFTWARE DEFINED RADIO FOR A MOBILE STATION

TRANSCEIVER

KHALID ELTAHIR MOHAMED OSMAN

FK 2009 73

DEVELOPMENT OF A MULTI-STANDARD PROTOCOL USING SOFTWARE DEFINED RADIO FOR A MOBILE STATION TRANSCEIVER

By

KHALID ELTAHIR MOHAMED OSMAN

Thesis Submitted to the School of Graduate Studies, Universiti Putra Malaysia, In Fulfilment of the Requirement for the Degree of Doctor of Philosophy

March 2009

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DEDICATED

…My dearest mother…. for making out of me the person who can present such a work...for doing all this with pleasure……

…. My beloved wife Amani…. the person who leads to successful life…and gives me all her supports and cute kids…..

To all the glory inside you…

To you… …love…thanks…and my simple effort…

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ABSTRACT Abstract of thesis presented to the Senate of Universiti Putra Malaysia in fulfillment

of the requirement for the degree of Doctor of Philosophy

DEVELOPMENT OF A MULTI-STANDARD PROTOCOL USING SOFTWARE DEFINED RADIO FOR A MOBILE STATION TRANSCEIVER

By

KHALID ELTAHIR MOHAMED OSMAN

March 2009

Chairman: Professor Borhanuddin Mohd. Ali, PhD Faculty: Engineering

In this thesis, the Software Defined Radio Digital Control System (SDR DCS) has

been developed to perform a multi-standard protocol of the handset using the GSM

and CDMA systems. The SDR DCS was designed for the SDR based band digital

transceiver of the handset as a control and protocol software to control and handle

the operation of the handset when roaming between different protocols; it could

easily and quickly let the handset reconfigure with the future protocol; it configured

the handset with either of the GSM or CDMA protocol software, and scheduled for

reconfiguration of the handset with the second protocol in sequence. The SDR DCS

controls the download of the specific air interface environment.

In order to implement the whole design in software, the design had to go through

three stages. The first stage was to do all the design steps in the software using

generic computing resources such as Hardware Description Language (HDL), with

the top-level design for each protocol. The second stage was to define a logic circuit

to perform the signal processing for each protocol; this step was applied after the

simulation and synthesis, and eventually programming that circuit into the FPGA

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board. The third stage was to use the FPGA to implement the functions required for

each protocol which constitutes the multi-standard protocol.

The VHDL files were created for each element of the GSM and CDMA protocols.

The GSM related system was developed with encoders and decoders linked to the

channel model. The CDMA related system was designed with a transmitter to

encode the user’s data into wide bandwidth using a reverse link channel and a

synchronized receiver to receive the signal from the forward link channel and decode

the wide bandwidth to recover the base band user’s data.

The Synopsys™ software package was used for the design, synthesis and simulation

of the SDR base band platform. The simulation tools used include the Model Sim

and System Studio. Meanwhile, the Xilinx ISE 9.2i was used as the synthesis tool.

The results of the simulated and synthesized top-level design files were downloaded

into the Xilinx XSA-3S1000 FPGA board. The waveforms for the GSM and CDMA

outputs approximately matched the ones seen in the oscilloscope for the FPGA

output pin. This proved that the SDR DCS had successfully implemented its task,

according to the objectives of the design.

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ABSTRAK Abstrak tesis yang dikemukakan kepada Senat Universiti Putra Malaysia sebagai

memenuhi keperluan untuk ijazah Doktor Falsafah

REKABENTUK DAN PELAKSANAAN PROTOKOL BERBILANG PIAWAIAN UNTUK TRANSCEIVER STESYEN BERGERAK RADIO

BERDEFINISIKAN PERISIAN (SDR)

Oleh

KHALID ELTAHIR MOHAMED OSMAN

Mac 2009 Pengerusi : Profesor Borhanuddin Mohd. Ali, PhD Fakulti : Kejuruteraan Dalam tesis ini, Sistem Kawalan Digital SDR (SDR-DCS) telah dibangunkan untuk

melaksanakan protokol berbilang piawaian untuk telefon bimbit menggunakan

sistem GSM dan CDMA. SDR-DCS telah direkabentuk untuk transceiver jalurasas

digital berasaskan SDR untuk telefon bimbit supaya ia dapat merayau di antara

bcrbagi sistem tanpa-wayar. SDR DCS dengan mudah dan cepat membenarkan

telefon bimbit mengatur semula dengan protokol yang baru ini; ia mengatur semula

telefon bimbit dengan salah satu dari perisian protokol GSM atau CDMA, dan

menjadualkan untuk mengatursemula telefon bimbit dengan protokol kedua, dalam

jujukannya. Sebagai kesimpulannya, SDR-DCS mengawal muat-turun persekitaran

pengantaramuka udara tertentu.

Untuk melaksanakan keseluruhan rekabentuk dalam perisian, rekabentuk tersebut

akan melalui tiga peringkat. Peringkat pertama ialah melakukan kesemua langkah

rekebentuk dalam perisian menggunakan sumber pengkomputeran umum, iaitu fail

Bahasa Pemerihalan Perisian (HDL) untuk rekabentuk. Peringkat kedua ialah

mendefinisikan suatu litar logik untuk melakukan pemprosesan isyarat bagi setiap

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protokol; langkah ini diaplikasikan setelah selesai simulasi dan sintesis dan diakhiri

dengan pengaturcaraan litar tersebut pada papan FPGA. Peringkat ke tiga ialah

untuk menggunakan FPGA bagi melaksanakan fungsi-fungsi yang diperlukan untuk

setiap protokol yang menjadikan ia protokol berbilang piawaian.

Fail VHDL telah dibentuk untuk setiap unsur protokol GSM dan CDMA. Sistem

berkaitan dengan GSM telah dibangunkan dengan pengekod dan penyahkod yang

dikaitkan dengan model saluran. Sistem berkaitan dengan CDMA telah direkabentuk

dengan satu penghantar untuk mengekod data pengguna kepada lebarjalur yang luas

menggunakan saluran pautan songsang dan satu penerima segerak untuk menerima

isyarat dari saluran pautan kehadapan, dan menyahkod lebarjalur luas untuk

mendapatkan balik data pengguna.

Package perisian Synopsys telah digunakan untuk merekabentuk, mensinthisis dan

mensimulasi platform jalurasas SDR. Alat simulasi yang digunakan adalah Model

Sim dan Sistem Studio. Xilinx ISE 9.2i telah digunakan sebagai alat sintesis. Hasil

keputusan dari fail aras utama yang disimulasi dan disintesiskan telah dimuat turun

kepada papan Xilinx XSA-3S1000 FPGA. Bentuk gelombang untuk GSM dan

CDMA adalah hampir serupa dengan apa yang dapat dilihat dari oscilloscope untuk

pin keluaran FPGA. Ini membuktikan bahawa SDR-DCS telah berjaya

melaksanakan tugasnya mengikut objektif rekaan.

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ACKNOWLEDGMENTS All praises to Almighty Allah (SWT) the most Benevolent, Merciful, and

Compassionate, for giving me the utmost strength, patience, and guidance to have

this work completed.

I would like to express my most sincere gratitude and deepest appreciation to the

chairman of my supervisory committee, Prof. Dr. Borhanuddin Mohd. Ali, for his

invaluable contribution, input and careful supervision. Without his constant

encouragement, this thesis would have never been written. I could never thank him

enough for giving me his support, particularly in extending and completing my work

in MIMOS Berhad.

I am also indebted to the members of my supervisory committee, Prof. Dr. S. S.

Jamuar, for his support and assistance on this project, as well as for serving as a

member on my committee. I am also grateful to Associate Professor Dr. Sabira

Khatun and Dr. Alyani Ismail, for being on my committee and also for their

encouragement, constructive suggestions and guidance.

Furthermore, I would like to acknowledge the Government of Sudan, and the

University of Gezira, for supporting me during my studies. My thanks also go to my

family members, especially my brothers Mohamed, Ameen and Awad.

Thanks are also due to the staff at the Faculty of Engineering, for their assistance and

permission to use all the facilities and software at the wireless lab. My thanks also

go to my fellow graduate students for their hospitality and kind assistance throughout

my studies; my friends’ kind words and help will always be cherished and

remembered. I would like to thank all of my friends for their support and helps.

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Words alone are not enough to express my heartfelt feelings to my beloved wife and

cute kids, Ahmed and Abdelaal, for their constant support, concern and motivation

throughout the study period.

Last but not least to my beloved mother, Rowgia Nooraljalil, my deepest

appreciation and respect for her untiring guidance, support and sacrifices, ever since

my childhood. Her spiritual support, Do’a and motivation have inspired me to do

this research. I owe a depth gratitude to her, which can never be repaid.

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APPROVAL I certify that an Examination Committee met on 11th of March 2009 to conduct the final examination of Khalid Eltahir Mohamed Osman of his Doctor of Philosophy thesis entitled “Development of a Multi Standard Protocol Using Software Defined Radio for Mobile Station Transceiver” in accordance with Universiti Pertanian Malaysia (Higher Degree) Act 1980 and Universiti Pertanian Malaysia (Higher Degree) Regulations 1981. The Committee recommends that the candidate be awarded the relevant degree. Members of the Examination committee are as follows: Roslina Binti Mohd Sidek Associate Professor Department of Electrical and Electronics Engineering Faculty of Engineering Universiti Putra Malaysia (Chairman) Mohd Adzir Mahdi, Ph.D, Professor Department of Computer and Communication Systems Faculty of Engineering Universiti Putra Malaysia (Internal Examiner) Ishak Aris, Ph.D. Associate Professor Department of Electrical and Electronics Engineering Faculty of Engineering Universiti Putra Malaysia (Internal Examiner) Syed Idris Syed Hassan, Ph.D. Professor School of Electrical and Electronic Engineering Universiti Sains Malaysia (External Examiner)

BUJANG KIM HUAT, Ph.D., Professor/Deputy Dean School of Graduate Studies Universiti Putra Malaysia Date:

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This thesis was submitted to the Senate of Universiti Putra Malaysia and has been accepted as fulfillment of the requirement for the degree of Doctor of Philosophy. The members of the Supervisory Committee are as follows: Borhanuddin Mohd. Ali, PhD Professor Faculty of Engineering Universiti Putra Malaysia (Chairman) S. S. Jamuar, PhD Professor Faculty of Engineering Universiti Putra Malaysia (Member) Sabira Khatun, PhD Associate Professor Faculty of Engineering Universiti Putra Malaysia (Member) HASANAH MOHD GHAZALI, PhD Professor and Dean School of Graduate Studies Universiti Putra Malaysia Date: 11 September 2009

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DECLARATION I declare that the thesis is my original work except for the quotations and citations, which have been duly acknowledged. I also declare that it has not been previously, and is not concurrently, submitted for any other degree at Universiti Putra Malaysia or at any other institutions.

KHALID ELTAHIR MOHAMED OSMAN

Date: 15 July 2009

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TABLE OF CONTENTS

Page

DEDICATED ii ABSTRACT iii ABSTRAK v ACKNOWLEDGMENTS vii APPROVAL ix DECLARATION xi LIST OF TABLES xv LIST OF FIGURES xvi LIST OF ABBREVIATIONS xx

1 INTRODUCTION 1 1.1 Research Motivations and Problem Statements 1

1.2 Research Scope 6

1.3 Research Aim and Objectives 7

1.4 Study Module 8

1.5 Research Contribution 12

1.6 Thesis Outline 12

2 LITERATURE REVIEW 13 2.1 A Brief History of Software Defined Radio (SDR) 13

2.2 SDR Architecture 17

2.3 SDR Technology 18

2.4 Advantages of SDR 24

2.5 Requirements of Base Band Platform 26

2.6 Multi Standard SDR Protocol 27

2.7 Multi Standard SDR Handset Transceiver 31

2.8 Summary 39

3 PROPOSED SDR DIGITAL CONTROL SYSTEM (SDR DCS) 41 3.1 SDR Digital Control System (SDR DCS) 41

3.1.1 Reconfigurable SDR DCS 42 3.1.2 SDR DSC for Multi standard Base Band 43 3.1.3 Handset Software Download Methods 48 3.1.4 Download Implementation 49 3.1.5 Roaming Support 50

3.2 Overview of GSM 50 3.2.1 GSM Channel Encoding 51 3.2.2 Channel Model 53

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3.2.3 System Structure 53

3.3 CDMA and Multiple Access 55

3.4 Classification of CDMA 56 3.4.1 Direct Sequence CDMA 58 3.4.2 DS CDMA Wireless Transceiver 60

3.5 Pseudorandom Noise (PN) Sequence 61

3.6 Simulation and Synthesis Tools 62 3.6.1 Simulation Stage 63 3.6.2 Synthesis and Implementation Stage 63

3.6.2.1 Design Entry 63 3.6.2.2 Synthesis 64 3.6.2.3 Implementation 64

3.7 System Design with the VHDL Approach 64 3.7.1 Design Methodology 64 3.7.2 VHDL Modeling Structure 66 3.7.3 VHDL Synthesis 66

3.8 Test Bench 68

3.9 Field Programmable Gate Array (FPGA) 69

3.10 Summary 70

4 METHODOLOGY 71 4.1 SDR Digital Control System (SDR DCS) Overview 71

4.1.1 SDR DCS Design Specification 73 4.1.2 SDR DCS Design 76 4.1.3 SDR DCS Verification 77 4.1.4 SDR DCS Implementation 79

4.1.4.1 Logic Synthesis 81 4.1.4.2 Place and Route 83

4.1.5 Device Programming and Testing 86 4.1.6 SDR DCS Implementation 88 4.1.7 SDR DCS Software Protocol 90 4.1.8 Network Detection and Network ID 92

4.2 Coding, Decoding and Channel Model in GSM System 95 4.2.1 GSM Parity Encoder 95 4.2.2 Convolution Encoder 97 4.2.3 Interleave Encoder 101 4.2.4 Packet Format Encoder 103

4.2.4.1 Normal Burst 104 4.2.4.2 Random Access Burst 106 4.2.4.3 Synchronization Burst 107

4.2.5 Differential Encoder 108 4.2.6 GSM Encoders Model Summary 110 4.2.7 Differential Decoder 110 4.2.8 Packet Format Decoder 111 4.2.9 Interleave Decoder 112 4.2.10 Viterbi Decoder 113

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4.2.11 Parity Check Decoder 114 4.2.12 Implementation of Channel Model 115

4.2.12.1 Channel Model Structure 115 4.2.13 Random Error Mode 116

4.3 CDMA Interface Model 119 4.3.1 Data Model 123 4.3.2 Coding Scheme & Parameter Setting 124

4.3.2.1 Coding Scheme in Reverse Link 124 4.3.2.2 Coding Scheme for Forward Link 128

4.3.3 Circuit Process Model 129 4.3.3.1 Base Band Transmitter Circuit Process Model 129 4.3.3.2 Base Band Receiver Circuit Process Model 132

4.4 Summary 137

5 RESULTS AND DISCUSSION 139 5.1 The SDR DCS 140

5.1.1 Reset Check 140 5.1.2 Test GSM Protocol 141 5.1.3 Test CDMA Protocol 144 5.1.4 Test Future Protocol 144 5.1.5 Selection of the Best Mode of Operation 148

5.2 GSM Protocol 154

5.3 The CDMA Protocol 158

5.4 Transmitter Module 160

5.5 The Receiver Module 161

5.6 The DS CDMA Modem 163

5.7 Implementation Results 164

5.8 Simulation and Implementation Results Integration 170

5.9 System Performance 176 5.9.1 Incremental 177 5.9.2 The Channel Error Rate Calculations 179 5.9.3 The Calculation of the Configuration Delay 181

5.10 SDR switching Systems and SDR DCS 183

5.11 Summary 188

6 CONCLUSION 190 6.1 Achievements 191

6.2 Summary of Contributions 192

6.3 Future Work 193

REFERENCES 195 APPENDICES 202 List of Publications 217

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LIST OF TABLES

Table Page 4.1: SDR DCS input/output (I/O) pin functions 75

4.2: FSM with logic values 77

4.3: convolution encoder 100

4.4: Burst structures in a GSM system 108

4.5: Differential encoding 109

4.6: Differential decoding mapping format 111

4.7: Reordering scheme for a traffic channel TCH 113

4.8: External control signal for receiver module 121

4.9: Receiver module external control signal function 121

4.10: External data Signal for Receiver Module 122

4.11: Receiver module external data signal function 122

4.12: External control signal for transmitter module 122

4.13: Transmitter module external control signal function 122

4.14: External data signal for transmitter module 123

4.15: Transmitter module external data signal function 123

4.16: Parameter setting for transmitter coding scheme 127

4.17: Transmitter test vector setting 127

5.1: Results of the three incremental types 177

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LIST OF FIGURES Figure Page 1.1: SDR Architecture Software Defined Radio Forum (2002) 7

1.2: SDR DCS Study Module 11

2.1: conceptual view of a software radio system 17

2.2: Block diagram of a generic digital transceiver Wipro (2002) 18

2.3: An example of dual mode second-generation cellular handset architecture Shah

(2002) 21

2.4: An example of reconfigurable SDR architecture Shah (2002) 23

2.5: The Vanu Software Radio architecture Shah (2002) 23

2.6: Multi standard SDR base band system Zhigang (2003) 28

2.7: Multi standard SDR base band processing platform SDR Forum Base Station

Working Group (2001) Zhigang (2003) 29

2.8: Hierarchical SDR library concept Koenig (2006) 31

2.9: Tsurumi handheld SDR terminal Tsurumi (1999) 33

2.10: Vanu Anywave GSM/GPRS BSS in a rural cellular deployment Vanu (2006) 34

2.11: Example SDR baseband data path reconfiguration 36

2.12: Base band sample packet transmit timing diagram for VHDL Software Defined

Radio Forum (2009) 39

3.1: The reconfiguration of the CDMA handset to work in GSM network Brawerman

(2005) 44

3.2: Flexible RF section Stefano (2006) 44

3.3: Hierarchical SDR DCS library concept 46

3.4: SDR Forum Reference model Software Defined Radio Forum, (2002) 47

3.5: SDR software framework Koenig (2006), Zhgang (2003) 48

3.6: From GSM to UMTS Sicard (2001) 51

3.7: GSM channel coding structure Eberspacher (2001) 54

3.8: Multiple access schemes: (a) FDMA, (b) TDMA, and (c) CDMA Ojanpera

(2003) 56

3.9: Classification of CDMA Ojanpera (2003) 57

3.10: Direct sequence, frequency hopping, and time hopping Ojanpera (2003) 58

3.11: Block diagram of a DS CDMA transmitter Sam (1998) 59

3.12: Receiver of a DS CDMA signal Sam (1998) 59

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3.13: (a) Traditional schematic design approach (b) VHDL-based design approach 65

3.14: VHDL modeling structure Zwolinski (2000) 66

3.15: Flow in VHDL synthesis Perry (1998) 67

3.16: High –level design flow 68

3.17: General purpose processing with flexible software Chang (2001) 69

4.1 FPGA Design Flow 72

4.2: SDR DCS flow chart 73

4.3: SDR DCS block diagram 75

4.4: SDR DCS sample test frame 78

4.5: FPGA Implementation flow 83

4.6: Sign-Off verification 86

4.7: FPGA Development board Stefano (2006) 87

4.8: Xess FPGA prototyping board 89

4.9: The view of the SDR DCS, GSM and CDMA inside the FPGA board 92

4.10: SDR with software control and frequency selection 92

4.11: SDR DCS frequency detection and reconfiguration 94

4.12: Parity Error detection method used for full rate encoder 96

4.13: Linear feedback shift register in parity encoder 96

4.14: Convolution error correction method used for RELP full rate encoder 98

4.15: Convolution encoder for speech encoding 99

4.16: Details of interleaving process 102

4.17: Diagonal interleaving of speech data 103

4.18: Structure of a normal burst 104

4.19: Structure of a random access burst 107

4.20: Structure of a synchronization burst 108

4.21: Differential encoding 109

4.22: Diagonal interleaver decoding of speech data 112

4.23: Structure of the channel model 116

4.24: Modem chip & its interfaces 121

4.25: Transmitter flow of operation 131

4.26: Base band transmitter architecture Wong (2001) 132

4.27: Receiver flow of operation 134

4.28: Proposed synchronization module 136

4.29: Base band DS CDMA modem architecture 137

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5.1: SDR DCS Reset test 142

5.2: SDR DCS GSM test 143

5.3: SDR DCS CDMA test 145

5.4: SDR DCS future protocol test configure case 147

5.5: SDR DCS future protocol test error case 149

5.6: SDR DCS with call wait status case 1 151

5.7: SDR DCS with call wait status case 2 153

5.8: The simulated result for the GSM channel coding structure 155

5.9: GSM encoder module 156

5.10: GSM decoder module 156

5.11: GSM encoders and decoders 157

5.12: GSM encoders/decoders starting frames 158

5.13: Input and output pins for CDMA transmitter and receiver before

synchronization 159

5.14: Schematic diagram for the transmitter module 159

5.15: Schematic diagram for the receiver module 160

5.16: DS CDMA transmitter 161

5.17: DS CDMA receiver 162

5.18: DS CDMA transceiver capture1 163

5.19: DS CDMA transceiver capture2 164

5.20: SDR DCS implementation for the GSM protocol using FPGA 166

5.21: The output of the GSM as seen in the oscilloscope 166

5.22: SDR DCS implementation for the CDMA protocol using the FPGA 167

5.23: The output of the CDMA as seen in the oscilloscope 167

5.24: SDR DCS implementation for future protocol using the FPGA 168

5.25: The output of the future protocol as seen in the oscilloscope 168

5.26: The automatic switching between GSM and CDMA 169

5.27: The system configured with GSM 170

5.28: The system configured with future protocol 170

5.29: The reset, configuration, and GSM stages for the handset 172

5.30: The GSM, reconfiguration, and CDMA stages for the handset 173

5.31: The CDMA, reconfiguration, and future protocol stages for the handset 174

5.32: Simulation and implementation results comparison 175

5.33: A comparison of the simulation and implementation results 176

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5.34: Simulation results of the random error mode 179

5.35: Simulation results of random error mode continue 180

5.36: The configuration delay period calculations 182

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LIST OF ABBREVIATIONS ADC Analog to Digital Converter AIS Air Interface Standards ASIC Application Specific Integrated Circuits

CDMA Code Division Multiple Access

CORBA Common Object Request Broker Architecture

CRC cyclic redundancy checks

DAC Digital to Analog Converter

DDC Digital Down Converter

DKI Direct Kernel Interface

DoD US Department of Defense

DS Direct Sequence

DSP Digital Signal Processor

DUC Digital Up Converter

EDA Electronic Design Automation

IF Intermediate Frequency

IS-95 Interim Standard 95

ISE™ Integrated Software Environment

ITU-R International Telecommunication Union - Radio

FCC Federal Communications Commission

FPGA Field Programmable Gate Array

FSM Finite State Machine

JTRS Joint Tactical Radio System

GSM Global System for Mobile

GPRS General Packet Radio Service

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LFSR Linear Feedback Shift Register

MS Mobile Station

NCD Native Circuit Description

NGD Native Generic Database

OTA Over-The-Air

PAR Place and Route

PCF Physical Constraint File

PN Pseudo-Noise

RAM Random Access Memory

RF Radio Frequency

ROM READ Only Memory

RTL Register Transfer Level

SCA Software Communication Architecture

SCR software controlled radios

SDR Software Defined Radio

SDR DCS Software Defined Radio Digital Control System

SOC System-on-Chip

UMTS Universal Mobile Telecommunications System

UPM Universiti Putra Malaysia

VCS Verilog Compile Simulator

VHDL Very High Speed Integrated Circuit (VHSIC)

Hardware Description Language

CHAPTER 1

1 INTRODUCTION This chapter introduces the subject of multi-standard protocol for Software Defined

Radio (SDR), the main requirement that must be satisfied by the multi-standard SDR

and its capability to support the communication system applications. There are

numerous definitions given to the SDR, all of which are not totally consistent with

each other. Among other, International Telecommunication Union - Radio (ITU-R)

defines the SDR as “A radio that includes a transmitter, in which the operating

parameters of frequency range, modulation type, and/or maximum output power

(either radiated or conducted) can be altered, post-manufacturing, by making a

change in software or adapting parameters under software direction, without making

changes to the hardware components”. The Federal Communications Commission

(FCC) defines the SDR as a “generation of radio equipment which can be

reprogrammed quickly to transmit and receive any frequency within a wide range of

frequencies, using virtually any transmission format and any set of standards”. In

contrast, the SDR Forum, as an international, non-profit organization promoting the

development of SDR, offers a broader definition, i.e. “SDR is a collection of

hardware and software technologies which enable reconfigurable systems

architectures for wireless networks and user terminals”.

1.1 Research Motivations and Problem Statements

Wireless communication systems are rapidly evolving through the incessant

extension of the old standards (GSM, IS95, CDMA2000, and UMTS) with the new

2

generations. A side effect of this rapid growth is an excess of mobile system

standards; every major country has its own standards.

In present day environment, there is a wide range of wireless communication systems

available such as the GSM, CDMA, WiFi etc. To support such diverse set of

protocols and the associated payloads (voice only with the GSM; voice, graphics,

video with 3G), most mobile handsets are built with multiple RF transceivers and

DSP chipset or microprocessors to handle the complex signal processing

requirements.

In the present technology, a handset is moved from one environment to another, for

example from GSM to CDMA; the handset devices simply "switch" the receiver and

transmitter circuits for the predefined air interfaces, rather than employing a single,

common RF front end. If a particular interface is not built into the handset, it is not

possible for the handset to operate in that particular environment. In such cases, the

consumer will have to purchase a different unit.

With the rapid development and growth in mobile telephone usage, it is clear that a

wireless revolution is taking place. The users’ problem is one of connectivity and a

growing number of incompatible Air Interface Standards (AISs) as well as

information filtering. At their desks, users have email, telephones, personal

computers, and wideband connectivity to internal backbones and external services.

As they leave their offices, they have to rely on their personal computers for

notification and cellular phones for contact. Both of these devices, however, have

limited access areas and specific protocols. Users also have separate palmtop devices

for multimedia information capture, storage, and display; these devices incorporate

substantial computational power.

3

Traditional radios use hardware circuits, fixed at time of manufacture to perform the

high speed signal processing to convert back and forth between user data and radio

waveform. In a traditional cell phone, for example, there is the radio front end,

consisting of an antenna and a radio-frequency transceiver that picks up the analog

radio waves, filters out the unwanted portions of the spectrum, and converts the

remainder into a lower frequency signal, which is fed into an analog-to-digital

converter. The resulting baseband signal is then processed i.e. demodulated,

decompressed, or otherwise decoded.

In a hardware radio (HDR), legacy platforms are tailored to support only one type of

waveform. That is, the physical layer of the waveform was embedded in specific

hardware solutions and the Radio Frequency (RF) front end was also optimized for

the same waveform. The key architectural elements of a radio would be the

transmitter and receiver (or transceiver), RF power amplification, and

encryption/decryption.

Within a Software Defined Radio (SDR), the radio contains several processing

elements (General Purpose Processors (GPP), Digital Signal Processors (DSP), and

Field Programmable Gate Array (FPGA)) that can be programmed by the waveform

to deliver the required functionality. However, if each waveform must be tailored to

the specific unique capabilities of each individual platform, (e.g., the type of GPP,

DSP, and FPGA), significant portions of the waveform may have to be rewritten if

they need to be ported to different hardware platforms. This has prompted the

development of open standards, to make it easier to develop waveforms that can run

on multiple platforms with minimal change.

Software defined radio aims to get rid of most of that hardware. A number of

companies are working on reconfigurable RF chips that can directly convert any