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SungKyunKwan Univ . 1 VADA Lab. L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성성성성성성 http://vada.skku.ac.kr

VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

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Page 1: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

1VADA Lab.

L40: Lower Power Equalizer

J. W. Kim and J.D.Cho

성균관대학교 http://vada.skku.ac.kr

Page 2: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

2VADA Lab.

Low Power Equalizer

• Jin Woo Kim, J.D.Cho, 1999, SKKU

• Introduction

• Equalizer

• Low-Power Methodology in Equalizers

• Simulation

• Future Work

• Reference

Page 3: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

3VADA Lab.

Introduction – xDSL(Digital Subscriber Line)

• Provide high bandwidth over copper twisted pair local loop cable, without amplifiers or repeaters

• Utilize full potential of a copper telephone subscriber loop up to a few hundred times that of a voiceband modem

• Support industry – standard transmission formats and bit rate such as T1 and E1

Page 4: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

4VADA Lab.

Introduction – xDSL Channel Configuration

CentralOffice

RemoteLocation

CentralOffice

CentralOffice

CentralOffice

ONU

CentralOffice

RemoteLocation

RemoteLocation

RemoteLocation

RemoteLocation

ADSL

HDSL

SDSL

VDSL

FTTH

6Mbps(1Mbps)

1.5Mbps

784Kbps

52Mbps

2.4Gbps

3Mbps

64Kbps(384Kbps)

Page 5: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

5VADA Lab.

DMT for ADSL( Discrete MultiTone Modulation)

• Built-in subchannel optimization• Ongoing active monitoring• Maximum loop variation coverage• Highest level of rate flexibility• Superior noise immunity for greater throughput• Broad industry chipset support• Interoperability through standards• Virtually future proof

Page 6: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

6VADA Lab.

DMT SubChannel Allocation for ADSL

• #1 ~ #6 : Analog Voice• #7 ~ #38 : Upstream Channels• #7 ~ #256 : Downstream Channels

10 32 7 8 38 256

4.3125 30.1875 163.875 1104 [KHz]

[Subchannelnumber]

AnalogVoice

Upstream

Downstream

Page 7: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

7VADA Lab.

ADSL Block Diagram ( DMT )

ErrorControlCoding

BitMapping

Pre-coding

IFFTCyclicPrefix

Insertion

DigitalFilter

DAC

AnalogFilter

HybridCircuit

AnalogFilter

AGC

ADC

POTSSplitter

TEQCyclicPrefix

RemovalFFT

EchoCanceller

FEQSymbol

Recovery

ErrorDe-

coding

Twisted PairTelephone Loop

POTS Telephone Setor Voice Band Modem

TransmitBit

ReceiveBit

TEQ : Time Domain Equalizer

FEQ : Frequency Domain Equalizer

AGC : Auto Gain Control

Page 8: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

8VADA Lab.

Equalizer – TEQ ( Time Domain Equalizer )

• TEQ with a small number of taps can reduce the

cyclic prefix(CP)

• Power Consumption Critical Part

• Adaptive FIR filters (LMS algorithm)

– The Filter Output

– The Filter Coefficient

– The Error Signal

1

,0

N

k k n k nn

y w x

1, , 0 1kk n k n k nw w e x for n N

k k ke I y

Page 9: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

9VADA Lab.

Equalizer – Example of TEQ

x (n)

w0 w1 w2 w3 w4

x (n)

y (n)

e (n )

Page 10: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

10VADA Lab.

Equalizer – FEQ ( Frequency Domain Equalizer )

• Compensate for the remaining frequency de

pendent attenuation and phase rotation of ea

ch subchannel

• Complex One-Tap FIR filter per one subcha

nnel (ADSL ; 256-7)

Page 11: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

11VADA Lab.

Equalizer – Example of FEQ• LMS(Least Mean Square) Adaptive Filter

x y

Conjugate

x *

c

- +

Page 12: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

12VADA Lab.

Low Power Methodology in Equalizers – Circuit

• FIR Filter– Carry-save adder– Grouped Multipliers(Wallace Tree Multiplier)– Booth Recoding technique

• Updating Circuits– Power-of-two LMS updating– The use of register file– Coefficient freezing– Make step size constant() to power-of-2

Page 13: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

13VADA Lab.

Low Power Methodology in Equalizers – Run-time

• The Error Monitor

• Adaptive Bit Precision

• Burst-Mode Update

• Adaptive Filter Length

Page 14: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

14VADA Lab.

Low Power Methodology in Equalizers – Example

FIR filterProgrammable

gainSlicer

UpdateError

monitor

Control

x

w A

z y

e

Freeze

Local_update

Error_status

Check_Err

Page 15: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

15VADA Lab.

Simulation – Environment (1)

Input SequencePRD(Pseudo Random Sequence)[T1E1.4]

4 9

1 for n=1to9

for n=10 to 512n

n n n

d

d d d

Make 4-QAM symbols as Training Sequence

Page 16: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

16VADA Lab.

Simulation – Environment (2)

• Test Channel– CSA#6

• 26AWG(0.4mm)

• 9000ft(about 2.7Km)

– AWGN noise environment

– SNR 40dB

ATU-C ATU-R9000ft

26 AWG

Page 17: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

17VADA Lab.

Simulation – Channel ( Impulse Response )

Impulse Response

- 0.001

0

0.001

0.002

0.003

0.004

0.005

1 51 101 151 201 251

Time

Mag

nitu

de

Page 18: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

18VADA Lab.

Simulation – Before Training( Received constellation )

Page 19: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

19VADA Lab.

Simulation – Before Training( Coefficient constellation )

Page 20: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

20VADA Lab.

Simulation – Before Training( Output constellation )

Page 21: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

21VADA Lab.

Simulation – After Training( Output constellation )

Page 22: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

22VADA Lab.

Simulation – Output SNR

Page 23: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

23VADA Lab.

Simulation – Result Analysis• Step Constants() are power-of-2

– 0.5 -> ½ (2-1)– 0.125 -> 1/8 (2-3)– 0.03125 -> 1/32 (2-5)– 0.007125 -> 1/128 (2-7)

• The smaller Constant, the longer convergence time

• Replace Complex Multiplier to Just Exponent Adder

• Low Power Consumption is acquired

Page 24: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

24VADA Lab.

Simulation – Using HP ADSSchematic - Transceiver

Page 25: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

25VADA Lab.

Simulation – Using HP ADSSchematic - Channel

Page 26: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

26VADA Lab.

Simulation – Using HP ADSSchematic - Receiver

Page 27: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

27VADA Lab.

Future Work (1)

• Simulation– TEQ simulation– NEXT, FEXT Channel Modeling– Attach Cyclic Prefix– Echo Canceller Simulation– Apply more Low-power Method– Apply Auto Bit Loading– Transmission Test to 215-QAM

Page 28: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

28VADA Lab.

• Hardware Synthesis– Implement FEQ in VHDL (Synopsys)– Implement TEQ in VHDL (Synopsys)– Apply Low-Power algorithm to EQ– Verify the function between Classical EQ and L

ow-Power EQ– Compare the power between Classical EQ and

Low-Power EQ

Future Work (2)

Page 29: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

29VADA Lab.

Future Work (3)

• Current Simulation and Implementation

model is for ADSL, but after improve the

Speed and Power, I will apply all the

algorithms to VDSL.

Page 30: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

30VADA Lab.

Reference (1)• W. Y. Chen, “DSL”, Macmillan Technical publishing, 199

8

• W. Goralski, “ADSL and DSL Technologies”, McGraw-Hill, 1998

• K. Azadet et al, “Low-Power Equalizer Architectures for High-Speed modems”, IEEE Comm. Magazine, Oct. 1998

• C. Nicol et al, “A Low-Power 128-Tap Digital Adaptive Equalizer for Broadband Modems”, IEEE jour. Of Solid-state Circuits, Nov. 1997

Page 31: VADA Lab.SungKyunKwan Univ. 1 L40: Lower Power Equalizer J. W. Kim and J.D.Cho 성균관대학교

SungKyunKwan Univ.

31VADA Lab.

Reference (2)

• H. Lee et al, “A New Hardware-Efficient Architecture for

Programmable FIR Filters”, IEEE Trans. On Circuits and

Systems, Sep. 1996

• J. Rinne et al, “Equalization of Orthogonal Frequency Divi

sion Multiplexing Signals”, Proc. Of GLOBECOM’94, pp.

415-419, Nov 27, 1994

• “DSP Solutions for Voiceband and ADSL Modems”, Texa

s Instrument, June, 1998