Abstramulti(EEAsignifcapacadiabμm CSuite.functienergintegr

Keywo

ArecensystemmultiMulti[9], sIndia8×8 TSMsuite.

Acertaiapprotime-energnoiseefficibeen one sand iIn Econsubetwefeaturwhichcircui

NovePow

manas

act—In this piplier structure

AL). The powerficantly low bcitance is mostbatic multiplier CMOS process . Both simulaionality of suc

gy-aware and ration (VLSI) c

ords: adiabatic;

A plethora of ntly in literatumatic design miplier based oiplier Architecsutra or “Vert

an Vedic MathVedic multip

MC 0.18μm CM. Adiabatic switin interest, andoach is based o-varying clockgy used by slowe immunity anient adiabatic lintroduced as

sinusoidal powis geared towarEEAL, high sumptions are een the outpures simplicity h substantiallyit complexity.

el Tranwer Hi

Megsh.bst@gmail.c

paper, we desce using Enerr consumptionecause the en

tly recovered. Tstructure havetechnology an

ation and meh logic, makin

performancecircuitry.

; single phase; lo

I.INTRODU

multiplication ure [1]-[8]. Imethodology fon Vedic mathcture is based tical and Croematics. Conv

plier structure MOS technolog

tching [13]-[15d is being impleon a slow chargked ac power wly decreasingnd driving abogic (EEAL) ban adiabatic lo

wer clock supplrd high-speed speed operatioensured by uut nodes andand static log

y decreases t

nsistorgh-spe

M. Ch

ECEghnad Saha Inscom1, suvadip

cribe an energygy Efficient A of the propos

nergy transferrThe proposed

e been designednd verified by easurement resng it suitable foe- efficient v

ow power, multi

UCTION algorithm has

In this paper for fast and arehematics [3],[4

on the Urdhvsswise” algori

ventional, as whave been i

gy, using CAD

5] has recentlemented in maging of the capand a partial

g the supply witbility. In this based on DCVSogic style. EEAly, has simple and low-energon as well sing a paralle clock supplygic resembledtransistor over

r Leveleed Adhanda1, S. Ba

E Dept.1&4, VDstitute of Techn192@gmail.co

y-efficient VedAdiabatic Logsed multiplier red to the loa8x8 CMOS an

d in a TSMC 0.1Cadence Desig

sults verify thfor implementinvery-large sca

iplier.

s been proposewe present

ea efficient dig4],[9]-[12]. Thva-Tiryakbhyaithm of ancie

well as, adiabatimplemented DENCE Desig

ly become of any systems. Thacitive nodes brecovery of ththout sacrificin

paper, EnergS logic [16], ha

AL requires onimplementatiogy VLSI desigas low energ

el resistive pay. EEAL log

d characteristicrheads and th

l Realidiabatianerjee2, D.

DTT Dept.2 andnology1&4, IIT Dom2, deepon.sah

dic gic

is ad nd 18 gn he ng ale

ed a

git he m nt tic in gn

a he by he ng gy as

nly n,

gn. gy ath gic cs, he

Thdescribissue oshows based Crosswadiabaof perimperaconclu

EEDCVSeach st

Figure

EEhas siprevioof eneclock overhecircuit

izationic VedSaha3, S. Ja

d ETCE Dept.3Delhi2, Jadavpha@gmail.com

he rest of the bes the operatiof power dissi the general

on Urdhvawise” algorithatic 8×8 multiprformance of ative logic styusions are given

EAL is a dualS network and tage, as illustra

e 1. EEAL logic (asupply (d

EAL requires imple implem

ously proposedergy consumptischeme [16],

eads. figure 1 (t and supply clo

n of Uldic Muain4

pur University3

m2, sankalp.000

paper is orgaion of EEAL inipation of thisimplementatio

a-Tiryakbhyamhm. Implemenplier, experime

f our energy yles are also den in section V.

II. EEAL Ll-rail adiabatic

a pair of crosated by figure

a) Block diagram (d) Cascading of Inv

only one sinu

mentation, andd adiabatic logiion. As single-this logic styl(b) and (c) shoock ( ) respec

ltra Loultiplie

01@gmail.com

anized as follonverter and alss proposed logon of N×N V

m sutra or ntation of conental results arecovery log

etailed in secti.

LOGIC c logic which css-coupled PM1(a).

(b) Inverter/Bufferverter/Buffer circu

usoidal powerd performs bic families [13-clock circuit rle can enjoy mows the EEAL ctively.

ow er

m4

ows. Section Io addresses thegic. Section IIedic multiplie“Vertical andnventional andand comparisongic with otheion IV. Finally

consists of twoMOS devices in

r circuit (c)Power uits

r clock supplyetter than the

3]-[15] in termrequires simple

minimal controbuffer/Inverte

I e I r d d n r y

o n

y, e s e

ol r

801

978-1-4673-5090-7/13/$31.00 ©2013 IEEE

Tusing(“outup fro“0” aP1 wfollowcombnode suppldisch“outbcan bnode.MHz

TunderrampCLVDchann

Ediss=

Similproce

E = { Hencoutpuvoltagtime, parammeasIn Ealmocomp Eload = CompCLVDadiab Adiab

Ener

= [{2

= 2{R

The operation g figure 1 (b). t” and “outb”) om logic 0 ( “0

and “inb”= “1”will be turned wing the suppbination of PM

is kept at grly clock swing

harged throughb” is kept at sabe obtained in . Output volta

z frequencies w

The energy adrstood by assus up between

DD over a timnel resistance R

={(CLVDD)/T}2

larly, energy cess of the EEA

{(RPCL)/T} CL(

ce RP is the turnut load capacitge drop acrossyet due to v

meter is treateures the thresh

EEAL as charst similar amo

plete cycle can

= 2{(RCL)/T}

pared to conDD

2 energy inbatic gain (G) o

batic Gain (G)

Energy comsumrgy Consumption b

2RPCL/T} + {(

RPCL/T}×100

of EEAL inveAssuming theare initially low0” ) to logic 1 ”; N1, M1 will

ON. The “ouply clock ( )

MOS (P1) and round potentiags from “VDDh the same came ground po

“out” node anage swing for

with 20 fF capac

dvantage of Euming a ramp

n “0” and “Vme period T. R is,

RT = {(RCL)/T

consumption dL inverter/buff

(VDD)2 + ½ CL(

n-on resistancetances, T is thes the resistive very small mad as constant.hold loss whicrging and disount of energy,

be expressed a

CL(VDD)2 + CL

nventional CMn a full cycleof EEAL becom

in (%)

mption by EEAL peby conventional CM

V)/VDD}2] × 1

(as V<<VDD,

rter/buffer cane complementaw and supply c( “VDD”) statebe turned off aut” node is th

closely throuNMOS (M2),

al, as N2 is “D” to groundcharging path otential. Resultnd ground potan adiabatic

citive load is sh

EEAL circuit p type voltage

VDD” and delivThe dissipati

T}CL(VDD)2

uring chargingfer can be expr

( V)2

e of the parallee charging timpath. Though gnitude ( few In equation (

ch is negligiblscharging proc, total energy das,

L ( V)2

MOS logic, we (CL is loadmes,

er cycle x10MOS per cycle

100

, {( V)/VDD}2<

n be summarizeary output nodclock ( ) rampe. Now if “in” and M2, N2 anhen charged bugh the parallwhereas “outbOn”. When th, “out” node

and un-drivetantly full swintential at “outbinverter at 10

hown in fig. 2.

can be readie source whicvers the chargon through th

(1

g or discharginressed as,

(2)

el path, CL is thme and V is th

V depends ow millivolt) th(2), (½CL( V)ly small indeecesses consumdissipation for

(3)

which consumed capacitances

0

<<1) (4

ed es ps =

nd by lel b” he is

en ng b” 00

ly ch ge he

)

ng

he he on he )2) ed. me r a

es s),

4)

So thprolonor disPMOS

R={μn

1={μnC

where ratio, mrespec0.18μm(W/L)p

Figure

II

3.1 U

ThTiryakmultipparallesummalater. Sparallethe proefficie

Thmathemcompu4×4 mFigureplacedsquare

he adiabatic gnging T. Hencescharging pat

S/NMOS transi

nCox(W/L)n(½V

Cox(W/L)n(VDD

(W/L)n ((W/mobility and t

ctively; all the m CMOS p=2(W/L)n, the

2. Output wavefo

II.IMPLEMENTA

Urdhva Tiryakb

he proposed mkbhyam (Verplication formuelism in genation is obtainSince the partiael, the multipliocessor. It is d

ent in terms of he 2×2 or 4matical methouters) needs no

multiplication ise 3. Hence dd in two consee. In case of

gain can be e, the turn-on reth consists oistors and can b

VDD-Vtn)+μpCox

D-2VT)}-1

/L)p), μn (μp),the threshold v

other terms hprocess, con

e above expres

orms of EEAL invload of 10

ATION OF N×N

bhyam sutra

multiplier is bartical & Crula of ancienneration of pned using Urdal products andier is independdemonstrated tsilicon area/sp

4×4 multiplicaods (successivo explanation. s illustrated in igits of multi

ecutive sides (N×N multipl

improved dresistance (RP) of parallel cobe expressed a

x(W/L)p(½VDD

Vtn ( Vtp ) voltages of NMhave the usualnsidering VD

ssion gives R=1

erter at 100 MHz f0fF

MULTIPLIER ST

ased on an algrosswise) [9]

nt Vedic mathpartial producdhva Tiryakbhd their sums ar

dent of the clocthat this architeed. ation utilizingve additions wHence, the Vethe example biplier and mu(along row andication (hence

ramatically byof the chargingombination o

as,

D- Vtp )}-

(5)

are the aspecMOS (PMOSl meaning. FoDD=1.8V and1.02K .

frequencies with a

TRUCTURE

gorithm Urdhva], a genera

hematics. Thcts and thei

hyam explainedre calculated inck frequency otecture is quite

g conventionawhen used onedic method foelow, shown in

ultiplicands ared column) of ae N=4), whole

y g f

)

ct ) r d

a

a al e r d n f e

al n r n e a e

802

squarbe paEach with writtecrosssignifand thinitia

3.2

Imultiand consi(Xa resuThe s i) S1 i ii) S2Y0) a iii) Sgeneraddediv) S4

Bmultishowdivideach we g(N/2+3)YL={

re will be dividartitioned agai

digit of the every digit of en in the smawise dotted linficant digit of he rest as the c

al carry is taken

Figure 3. Mu

Implementatio

In this sectioniplier block, w

8×8 multipidering two inX1X0 and Yult, by doing vsteps are:

is the result of

2 is the additioand (X0 and Y1)

S3 is the vertirated from thed with the verti4 is the carry ge

By using this iplier block ca

wn in figure 4, Nded into two eq

halve. Assumet XL= {X1 X

)….XN}as two {Y1 Y2 Y3…YN

ded into N2 (=n by crosswismultiplier is tthe multiplicanall square boxne are added tothe obtained n

carry for the nen as “logic 0”.

ultiplication using U

on of general V

n we first discwhich will be f

lier structurenputs (X and Y1Y0), we get ertical and cro

Vertical multip

n of crosswire).

ical product oe previous stepical product to enerated during

2×2 multipliean be implemenN-bit multipliequal halves, co

ming N-bit mulX2 X3….XN/2} a

halves of X. N/2} and YH={Y

16) no. of sque line, as showthen independend and the twox. All the digo the previous number acts asext step. In this

UrdhvaTiryakbhy

Vedic multiplier

cuss the organfurther used toes. In 2×2

Y) having tfour outputs (ss-multiplicati

plication betwe

e bit multiplica

of X1 and Y1,ps, otherwise c

generate S3 asg addition of S

er block 4×4, nted. For N×Nr and multipliconsisting of N/ltiplication betand XH= {X (NFor Y, its two

Y(N/2+1) Y(N/2+2)

uares, which wiwn in Figure ently multiplie

o-digit product gits lying on carry. The lea

s the result digs above examp

am Sutra

r structure

nization of 2×o configure 4×

multiplicatiotwo digits eacS S4S3S2S1) aon and additio

een X0 and Y0.

ation of (X1 an

, if no carry carry bit will b a sum. 3.

8×8, 16×16 eN multiplicatiocand first will b/2 no. of bits tween X and YN/2+1) X (N/2+2)o halves will bY(N/2+3) ….YN

ill 3. ed is a

ast git ple

×2 ×4 n, ch as n.

.

nd

is be

etc n, be in Y, X be

N}.

So, Xsteps a

1) Fi

YfirNbi

2) In

,Y{SSLadca

3) VbiOca…ThN S(ad

4) C

caanThlawthS(

and Y can be are given bellow

irst vertical mYL(N/2 bits) wi

rst N/2 bits {N/2 outputs {S1

it in next steps.

n next steps croYL) and (XL ,YSHL(1) SHL(2) SLH(N)} respectivdded up to prodarry.

Figure 4. Gene

Vertical multiplits) also producut of these N

ascaded with …..SLL(N)}, of v

hese total N noN bit adder, S11

(N/2+1) to S(3N/2ddition also pro

1 and C2 are sarry bits. (N/2-nd sum to prodhese N/2 bits w

ast N/2 bits of vwhich are {SHH(hese N/2 bits ad(3N/2+1) to S(2N))

represented asw,

multiplication ill produce totaSLL(1) SLL(2) …S2 ….SN}. Las

.

oss-multiplicatYH)to produce

SHL(3)…..SHL(N)} avely. These twduce another N

eral block diagram

lication betweeces N no. of b

N bits, first N/the last N/2

vertical multipo. bits will be to S1N, to prod

2)) of N×N moduces a carry,

sent to the hal-2) no. of zerosduce a set of Nwill be added uvertical multip(N/2+1) SHH(N/2+2ddition will prof N×N multip

s XH XL and Y

between XL (al N no. of bit

…..SLL(N/2)} arest N/2 bits will

tions have done two sets of and {SLH(1) SL

wo sets of N nN no. bits,S11 to

m of NxN Vedic M

en XH (N/2 bitbits, {SHH(1) SH/2 bits, SHH(1) 2 bits, {SLL(lication betweadded with theduce total N no

multiplier. This, C2.

lf adder to gens will be insert

N/2 bits, as shoup by a N/2 bitplication betwe2) …..SHH(N)} . roduce the last plier.

YHYL . Now th

(N/2 bits) andts. Out of thesee taken as firsl be used for N

e between (XHN no. of bits

LH(2) SLH(3) ….no. of bits aro S1N and C1 a

ultiplier

ts) and YH (N/2HH(2) …..SHH(N)}

to SHH(N/2) ar(N/2+1) SLL(N/2+2een XL and YLe output of firso. of bits (from

s second N bi

nerate sum andted before carryown in figure 4t adder with theen XH and YHThe outputs oN/2 bits (from

e

d e st

N-

H s, .. e s

2 . e 2)

L. st m it

d y

4. e

H, f

m

803

S

multi

Figure

Sthe implepreseEEALusingreplacNANsum blockstandas buand spectPMOwher

3.3

All sDurinand AHencinput{A}=000000010000CMOrespemultimulti

So in a N×Nipliers, two N b

e 5. DCVS networ

Static conventiconventional ementation, firent the designL logic. Com

g simple NMOcing the DCV

ND gate with Eand carry blo

k are shown indard-cell libraryuffer/inverter, tmultiplier blo

tre circuit simuOS and NMOS

e =0.9 m.

Results and Si

simulations hang simulation wA0} and {B} = ce random pattet bit (Ai or Bi={01010101, 01111, 0011000101, 000011111 and 001

OS and Vedic ectively. Perforiplier circuit aipliers with va

N multiplicatiobit adders, a ha

rk (a) Sum block (b

ional CMOS loVedic multip

rst we describen of adiabatic

mplex gates caOS based DCVS network wEEAL circuit ck of Full addn figure 5. Wy, consisting otwo inputs and

ock of varyinulator in 0.18μmS are taken wit

imulations

ave been donewe apply {A} {B7, B6, B5,B4

erns consist of , where i = 0 00001111, 00011 and 0001111, 001100

110011}. The multiplier are rmance measu

along with Cararying bit-size

on, we need alf adder and a

b) Carry block (c)

ogic style is usplier. In case the EEAL ga

8x8 Vedic man be easily iCVS network. we can implem

topology. DCVder circuits, al

We have designof common did three-input f

ng bit length m technology. th W/L = 12

e under 1.8V = {A7, A6, A

4, B3, B2, B1 anf four bits are a

to 7). The as110011,000100101} and {

011, 011100simulated waalso shown in

urement of 8×8rry-Save, Arras (2-bit, 4-bit,

four N/2×NN/2 bit adder.

AND NAND bloc

ed to implemee of adiabat

ates and then wmultiplier usinmplemented b

In Fig. 1, bment the ANDVS network folong with AN

ned an adiabatigital gates sucfunctions, addusing CadencW/L ratio of th /2 and 6 /2

supply voltag5,A4, A3, A2, A

nd B0} as inputssigned for eac

ssigned bits ar101, 0001010B}={011100111, 0001010aveform of 8×n Figure 6 & 8 CMOS Veday, Wallace tre, and 8-bit) ha

/2

ck

nt tic we ng by by D-for

ND tic ch

der ce he 2

ge. A1 ts. ch re; 1, 1, 1,

×8 7

dic ee as

been care alsimulathe muminimis 180n

Figur

compared. Perflso compared ations have bee

multiplier circumum transistor w

nm.

re 6. Output wavef

formances of awith the CM

en done to veriuits using CADwidth in the 0

form of 8×8 Conv

diabatic 8×8 VMOS counterpify the functionDENCE Spice.18μm CMOS

entional(CMOS) V

Vedic multipliepart. Extensivenality of the ale Spectra. Then-well proces

Vedic Multiplier

r e ll e s

804

TconsuSincemultidirect10MH30% Walla

Figure 7. Outpu

Table 1 showsumption compe greater numipliers, the powtly extrapolateHz 2×2, 4×4 anand 41% of th

ace tree multi

ut waveform of 8×

s that Vedic mpared to other mbers of addewer savings fored to higher opnd 8×8 Vedic he total powerplier respectiv

×8 Adiabatic Vedic

multiplier shooptimized mu

er cells are ur smaller operaperand multiplmultiplier con

r consumed byvely. Table 1

c Multiplier

ows least powultiplier circuitused for largand sizes can blier modules. Isume only 33%

y carry save analso shows th

wer ts. er be In

%, nd hat

Vedic existinmultipproducmultipalmostfaster multiplength69% (5multip

(EDP)energyTable carry operat(8×8) 16.9%array, the foproducworse due toEEALyet dureducesaves conven

Tabl

Bit L

o

Conve

Mult

2

4

8

Bit L

o

Conve

Mult

2

4

8

multiplier isng multiplier, plier are gainedcts with their plications thout same speed ythan the other

plier is reportedh, delay of 4×451%) of the to

plier circuit undHence we

) which shouldy is more rel2 shows that tsave and Bit-a

tion yet deviatVedic multip

% (33.4 %) andWallace tree

ollowing resulct (PDP) of tthan the PDP

o the negligibleL logic. Thougue to very low ped significantlalmost 16.5% ntional 8x8 (2xle 1. Power dissipcircuits with vary

Length

of

entional

tiplier

Power

Vedic

2×2 27

4×4 104

8×8 892

Length

of

entional

tiplier

Vedic

2×2 0.23

4×4 0.58

8×8 1.38

s considerablyas the spee

d by parallelizconcurrent s

ugh the otheryet the Vedic mrs. Due to simd as 230 ps onl4 (8×8) Vedic otal delay showder same bit len

also compared combine a mlevant metric though the enearray multiplietions occur in plier achievesd 20% (28.6%)and carry sav

lts can be sumthe 8x8 conveof the fully ad

e amount of nogh adiabatic copower consumly. 8x8 (2x2) (57.1%) of tox2) Vedic multation, delay and E

ying bit lengths for

consumption (μW)

Carry-save

81

427

2060

Delay (ns) of diffe

Carry-save

0.46

0.66

1.68

y faster comped improvemezing the generummations. In

r multiplier cimultiplier is almmplicity, delayly. However onmultiplier is 8

wn by carry-savngth conditione the energy-measure of pe

than Power-ergy-delay proers are almost4×4 and 8×8 almost 11.1) of total EDPe multipliers. mmarized, theentional Vedic

diabatic Vedic on-adiabatic loounterpart is li

mption, power d adiabatic Veotal energy cotiplier.

Energy-delay of CMr 180nm CMOS T

) of different type of

Bit-array

92

449

2090

rent type of Multipl

Bit-array

0.45

0.84

2.69

pared to otheents of Vedication of partian case of 2×2ircuits achievemost two time

y of 2×2 Vedicn increasing bi88% (82%) andve and Bit arrayn. -delay producerformance anddelay product

oduct of Vedict same for 2×2operation. 4×41% (11.3 %)

P shown by BiFrom Table 2

e power delayc multiplier i8x8 multiplier

oss of proposedittle bit slowe

delay product iedic multipliensumed by the

MOS multiplier Technology

f Multiplier units

Wallace Tree [5]

185

389

2172

lier units

Wallace Tree

0.42

0.73

1.53

r c

al 2 e s c it d y

ct d t. c, 2 4 ), it 2, y s s d r s r e

805

Bit Length

of

Conventional

Multiplier

Energy-Delay Product (×10-25 Js) comparison of different type

of Multiplier units

Vedic

Carry-save

Bit-array

Wallace Tree

2×2 0.14 0.17 0.17 3.20

4×4 3.50 18.80 30.50 20.70

8×8 169.80 589.60 1505.10 508.40

Table 2. Performance comparison of conventional and adiabatic Vedic

multiplier circuits with varying bit lengths at 10 MHz for 180nm Technology

Bit Length of Multiplier

Power consumption (μW) of Multiplier

Conventional Vedic Adiabatic Vedic Savings (%)

2×2 27 9.64 64.3

4×4 104 45.76 56.0

8×8 892 526.28 41

Bit Length of

Multiplier

Propagation Delay (ns) of Multiplier

Conventional Vedic Adiabatic Vedic Savings (%)

2×2 0.23 0.25 -8.0

4×4 0.58 0.67 -15.5

8×8 1.38 1.87 -35.5

Bit Length of

Multiplier

Energy-Delay Product (×10-25 Js) comparison of Multiplier

Conventional Vedic Adiabatic Vedic Savings (%)

2×2 0.14 .06 57.1

IV.CONCLUSION An energy efficient new adiabatic multiplier structure

based on Urdhva Tiryakbhyam sutra of Vedic mathematics has been proposed using EEAL style. On basis of Cadence spectre simulations, it can be concluded that this Vedic multiplier is more efficient than array multiplier, Booth multiplier and Wallace-Tree multiplier, in terms of timing efficiency and speed. The speed improvements are gained by parallelizing the generation of partial products with their concurrent summations. It is also shown that energy efficiency can be enhanced significantly in low frequency domain using the newly proposed adiabatic approach.

REFERENCES [1] P. P. Kundu, O. Bandyopadhyay, A. Sinha, "An efficient architecture of

RNS based Wallace Tree multiplier for DSP applications," Proceedings 51st Midwest Symposium on Circuits and Systems, Knoxville, TN, pp. 221, 10-13 Aug. 2008.

[2] Y. H. Seo, D. W. Kim, “ A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm,” IEEE Trans. on VLSI Systems Circuits and Systems, vol. 18, no. 2, pp. 201-208, 2010.

[3] J. Chen, C. H. Chang, “High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 12, pp. 1844-1856, 2009.

[4] M.E Paramasivam and R.S Sabeenian, “An efficient bit reduction binary multiplication algorithm using Vedic methods,” IEEE 2nd International Advance Computing Conference, Patiala, India, pp. 25, 19-20 Feb. 2010.

[5] Asati, A. Chandrasekhar, “An improved high speed fully pipelined 500 MHz 8×8 Baugh Wooley multiplier design using 0.6 m CMOS TSPC logic design style,” ICIIS 2008, pp. 1-6, Dec. 2008.

[6] Z. Huang and M. Ercegovac, “High-Performance Left-to-Right Array Multiplier Design,” Proc. 16th Symp. Computer Arithmetic, pp. 4-11, June 2003.

[7] H. P. Afshar, A. K. Verma, P. Brisk and P. Ienne, “Improving FPGA Performance for Carry-Save Arithmetic,” IEEE Trans. on VLSI system, vol. 18, no. 4, pp. 577-590.

[8] Z. Gang, H. Michalik and L. Hinsenkamp, “Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs” IEEE Trans. on VLSI system, vol. 18, no. 7, pp. 1057-1066.

[9] B. Jagadguru Swami Sri Bharath, KrsnaTirathji, “Vedic Mathematics or Sixteen Simple Sutras From The Vedas”, MotilalBanarsidas , Varanasi(India),1986.

[10] H. Thapliyal, “VLSI implementation of RSA encryption system using ancient Indian Vedic mathematics,” proc. of VLSi circuit and system, vol. 5837, pp. 888-892, 2005.

[11] R. Pushpangadan, V. Sukumaran, R. Innocent, D. Sasikumar, V. Sundar, “High Speed Vedic Multiplier for Digital Signal Processors,” IETE journal of research, vol. 55, issue 6, pp. 282-286, 2010.

[12] Thapliyal and M. B. Srinivas, “An Efficient Method of Elliptic Curve Encryption Using Ancient Indian Vedic Mathematics”, in Proc. IEEE MIDWEST Symp. Circuits. Systems, Cincinnati, Aug. 2005, pp. 826–829.

[13] M. Chanda, A. Dandapat, H. Rahaman, “ Ultra low-power sequential circuit implementation by a Quasi-Static Single phase Adiabatic Dynamic Logic (SPADL),” TENCON 2009, Singapore, pp. 1-5, 2009.

[14] X. Jian, W. Peng-jun, Z. Xiao-yang, “Research of adiabatic multiplier based on CTGAL,” in 7th International Conference on ASIC, China, pp. 138–141, 22-25 Oct., 2007.

[15] Y. Takahashi, T. Sekine, and M. Yokoyama, ”Two-phase clocked CMOS adiabatic logic,” in Proc. IEEE Asia pacifiic Conf. Circuits and Systems, Macao, China, Nov. 30-Dec. 3, 2008.

[16] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective (2nd edition). New York: Prentice Hall, 2003.

806