Verilog HDL 数字集成电路设计原理与应用

**Microelectronics School Xidian University Verilog [email protected]

Microelectronics School Xidian University

Verilog HDLXXXXX**Microelectronics School Xidian University


Verilog HDL

**Microelectronics School Xidian University


70ICIntegrated CircuitMicro Processor Unit, MPU

80FoundryICMPUMicro Control Unit, MCUICApplication-Specific IC, ASIC

90ICCentral Processing UnitCPUDigital Signal ProcessingDSP

ICFundryIP**Microelectronics School Xidian University


HDLCFORTRANPascal

HDLHardware Description LanguageHDL



HDLGateway Design AutomationVerilog HDLDARPAVHDLOO VHDLDE VHDLVITAL

Verilog HDLVHDLHDL19951987IEEE



Verilog HDL**Microelectronics School Xidian University



VerilogIEEE1364-1995199512Verilog HDLIEEEVerilog HDLIEEEVerilog HDL 1364-1995Verilog-A1996Verilog-AOVIIEEE1364 Verilog1999VerilogVerilogIEEE1364-20012001IEEEVerilog IEEE1364-2001HDL1995PLISystemVerilog IEEE1800-20052005VHDLVerilog HDLVerilog HDL IEEE 1364 Verilog-2001 Verilog-2001


Verilog HDLVHDL**Microelectronics School Xidian University


Verilog HDL1: **Microelectronics School Xidian University a4b32module aand4(a,b,c); input [3:0]a,b; output [3:0]c; reg [3:0] c; always @(a or b) c=a&b;endmodulemodule aand32(a,b,c); input [31:0]a,b; output [31:0]c; reg [31:0] c; always @(a or b) c=a&b;endmoduleVerilog HDL


a[3:0]

b[3:0]

c[3:0]

a[31:0]

b[31:0]

c[31:0]

Verilog HDL**Microelectronics School Xidian University 2: 4module shiftregist4 (clk,din,Reset, qout);input clk,Reset,din;output [3:0] qout;reg [3:0] qout;always @(posedge clk or posedge Reset )beginif(Reset) qout

Verilog HDL**Microelectronics School Xidian University 2: 8module shiftregist8 (clk,din, Reset,qout);input clk,Reset,din;output [7:0] qout;reg [7:0] qout;always @(posedge clk or posedge Reset )beginif(Reset) qout

**Microelectronics School Xidian University .(1)Soft Core5000Verilog HDLVHDL

(2) Firm CoreASICFPGA5000

(3) Hard CoreASIC5000




RTL

/

Verilog HDL

2.1 Verilog HDL2.1.1\b\tinitial begin a = 3 b100; b = 3b010; end

initialbegin a = 3 b100;b = 3b010;end



2.1.21//Verilog HDL2/**/Verilog HDL

assign a=b & c; // assign a[3:0]=b[3:0]&c[3:0;]; /*12 */

/* /**/ *//* //*/**Microelectronics School Xidian University


2.1.3Verilog HDLIdentifier$ _**Microelectronics School Xidian University 2.1-3countCOUNT //count_CC_G5B25_78SIX2.1-430count //out* //*a+b-c //+-n@238//@


2.1.3

Verilog HDLEscaped Identifier\()**Microelectronics School Xidian University 2.1-5\ a+b=c\7400\.*.$\{******}\~Q\OutGate //OutGate


2.1.4Verilog HDLVerilog HDL,

ALWAYSalways()

2.1.4**Microelectronics School Xidian University


2.1.5Verilog HDL**Microelectronics School Xidian University

0011xXzZ


**Microelectronics School Xidian University +/-< base_format >< number >2.1-68b10001101 //8100011018ha6 //8a65o35 //5354d6 //464b1x_01 //41x012.1-74d-4 //3 b001 //b(4+4)b11 //

bB01xXzZ_oO0~7xXzZ_dD0~9_hH0~9a~fA~FxXzZ_


13.04.540.25.2564.2e256420.0 8.7E2870.0(e)3E-30.003

**Microelectronics School Xidian University 2.1-8 2.7//5.2e8//3.5E-6//eE5_4582.2158_5896//6.//.3e5//


2.2 :;:


supplystrongpulllargeweakmediumsmallhighz


2.2.11. **Microelectronics School Xidian University

wiretriwortriorwandtrandtriregtri1tri0supply11supply00


(1) wiretri

(2) wortrior**Microelectronics School Xidian University

wire/tri01xz00xx01x1x1xxxxxz01xz

wor/trior01xz001x011111xx1xxz01xz


2.: reg reg

regreg a;//aregreg [3:0] b;//4bregreg[8:1]c,d,e;//cde8reg

regregreg signed[3:0] rega;rega=-2;//rega1110142



2.2.2reg [list_of_variables];

net_ declarationwiretritri0tri1wandtriandtriorwor

range11

delay

list_of_variables

drive_strength**Microelectronics School Xidian University


reg

rangereg1



2.2-2 reg rega;//1reg [7:0] regb;//8tri [7:0] tribus;//8tri0[15:0] busa;//16tri1[31:0] busb;//32reg scalared[1:4]b;//4wire(pull1,strong0)c=a+b;//101ctrireg(large) storeline;//**Microelectronics School Xidian University


2.2.3RAMROMregreg ;range1range21[msb:lsb][msb:lsb]msb-lsb+1



2.2-3reg[7:0] mem1[255:0];// 2568mem1//0255reg [15:0]mem2[127:0],reg1,reg2;//12816mem2//16reg1reg22.2-4reg[n-1:0] a;//nareg mem1[n-1:0];//n1mem1



2.2.4integertimerealparameterinteger;

2.2-6integer index;//32integer i[310]//32



64$timetime;time a,b;//64



real;real stime;//parameterparameter 1=1,2=2,,n=n;2.2-7parameter length=32,weight=16;parameter PI=3.14,LOAD=4b1101;parameter DELAY=(BYTE+BIT)/2;



2.3 **Microelectronics School Xidian University

Verilog! ~ * / %+ ->< >===!====!==&^ ^~|&&||?:if-else


2.3.1 +-*/%12.3-1reg[3:0]A,B,C;reg[5:0]D;A=B+C;//4D=B+C;//6



22.3-2module arith_tb;reg[3:0]a;reg[2:0]b;initialbegina=4'b1111;//15b=3'b011; //3$display("%b",a*b);//4'b1101//45$display("%b",a/b);//4'b0101$display("%b",a+b);//4'b0010$display("%b",a-b);//4'b1100$display("%b",a%b);//4'b0000endendmodule



2.3.2 > =

2.3.3 = =!== = =! = =10x**Microelectronics School Xidian University 2.3-2 a== 2.3-2 b== =2.3-4module equal_tb;reg[3:0]a,b,c,d;initial begina=4'b0xx1;b=4'b0xx1;c=4'b0011;d=2'b11;$display(a==b); //x$display(c==d); //1$display(a===b); //1$display(c===d); //0endendmodule

===01xz0100010100x0010z0001

==01xz110xx101xxxxxxxzxxxx


2.3.4 &&||!

ab4b11104b0000!a=0!b=1a&&b=0a||b=1a4b1100b4b01x0!a=0!b=xa&&b=xa||b=xx**Microelectronics School Xidian University

ab!a!ba&&ba||b110011100101011001001100


2.3.5 ~ & | ^^~

**Microelectronics School Xidian University 2.3-5module bit_tb;reg[2:0]a;reg[4:0]b;initial begin a=5'b101;//a5b00101 b=5'b11101; $display("%b",~a);//5'b11010 $display("%b",~b);//5'b00010 $display("%b",a&b); //5'b00101 $display("%b",a|b); //5'b11101 $display("%b",a^b);//5'b11000 endendmodule

&01x0000101xx0xx


2.3.6 & | ^~&~|~^^~**Microelectronics School Xidian University 2.3-6module cut_tb;reg[5:0]a;initial begin a=6'b101011; $display("%b",&a); //1'b0 $display("%b",|a); //1'b1 $display("%b",^a); //1'b0 endendmodule


2.3.7

0

**Microelectronics School Xidian University 2.3-7module shift_tb;reg[5:0]a,b,c,d;reg[7:0]e;initial begina=6'b101101;b=a3; d=a

2.3.8 ?:10x12

**Microelectronics School Xidian University 2.3-8:module mux2(in1,in2,sel,out);input [3:0]in1,in2;input sel;output [3:0]out;reg [3:0]out;assign out=(!sel)?in1:in2; //sel0outin1,outin2endmodule 21


in1

in2

out

sel

0

1

2.3.9{{}}12n

{{}}**Microelectronics School Xidian University 2.3-9 module con_rep_tb;reg [2:0]a;reg [3:0]b;reg [7:0]c;reg [4:0]d;reg [5:0]e;initial begina=3'b101;b=4'b1110;c={a,b};//d={a[2:1],b[2:0]};//e={2{a}}; // $display("%b",c); //8'b01011110 $display("%b",d);//5'b10110 $display("%b",e);/6'b101101 endendmodule


2.4 2.4.1moduleVerilog HDL

**Microelectronics School Xidian University 2.4-1


1moduleendmodule2inputoutputinout3wireregmemoryparameter4initialalwaysUDPassignfunctiontask



**Microelectronics School Xidian University 2.4-1 D

module dff (din,clk,q,);input din,clk;output q;reg q;always@(posedge clk)q

2.4.21inputoutputinout211221122



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Verilog HDL 数字集成电路设计原理与应用