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Verilog HDL 语言初步

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计算机系统综合课程设计 (2). Verilog HDL 语言初步. 主讲杨全胜 东南大学计算机科学与工程学院. 第一部分 Verilog HDL 语言 §1 综述. 一 . 什么是硬件描述语言？. 硬件描述语言是一种用文本形式来描述和 设计电路的语言。是硬件设计人员和电子设计 自动化（ EDA ）工具之间的界面。. 功能： 1 ）编写设计文件； 2 ）建立电子系统行为级的仿真模型； 3 ）自动综合以生成符合要求且在电路结构上可以实现的数字逻辑网表（ Netlist ）； 4 ）写入到 CPLD 和 FPGA 器件中。. - PowerPoint PPT Presentation

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Verilog HDL1. Bottom Up
4.
REGISTER
PC
RAM
ALU
reg——
2
output out
endmodule
full_add f2 (.a(a[2]),.b(b[2]),.cin(cin2),
.sum(sum[2]),.cout(cin3));
.cout(cout),.sum(sum[3]));


assign
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(\n)

initial
begin
wire——wire
3.
1.
reg
parameter
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parameter r=5.7 //r
//
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B
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reg [WORD_SIZE:1] RamPar [ ADDR_SIZE-
reg [5:0] Frx
out4out5)
reg [3:0] out1
reg [4:0] out3
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a<b ||b<c a || b
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~A=5'b00110

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input [2:0] a b
always @ (a or b)
“1”
&——
~&——
| ——
~| ——
^——
^~~^——
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a——
n ——
endmodule
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Dbus[2], Dbus[3]};//4
4
//44
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//clkreset
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output out
input [1:0] sel
case (sel)
1
output[7:0] out
input [7:0] data
else out=out+1 //
end
endmodule
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:
begin
output f
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“”
5
6alwaysinitial
#50 A=1B=0
`timescale 1ns/100ps1ns, 100ps
`timescale time_unit / time_precision
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#50 B=1
#50 $finish
reg [bytesize-1:0] memory [size-1:0]
memory[index]=0;
endmodule
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endmodule
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#(2*cycle) wave=0 ;//2*5*1050ns
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endmodule
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.
assign #(1.51.02.0) z=x&y;
endmodule
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5
endmodule
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13ifif“”0xz“”1“”
2ifelse“begin-end”
3ififelse
always @(sela or selb or a or b or c);
begin
resetclk);
output [7:0] qout;
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else qout[7:4]<=qout[7:4]+1;
end
end
end
endmodule
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input[7:0] a, b;
begin
input[7:0] a, b;
begin
4if else case default
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end
endmodule
#25 clk=~clk;
inout [16: 1] data;
input [4: 1] num;
begin
else qout=qout + 1;
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begin
temp[counter]=mem[address+counter-1];
data={temp[1],temp[2],temp[3],temp[4]};
end
endtask
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reg [15: 0] a;
reg [31: 0] b;
if (x[i]=1'b0) count=count+1;
get0=count;
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case4
module mux4_1b(out,in1,in2,in3,in4,cntrl1,cntrl2);
output out;
input in1,in2,in3,in4,cntrl1,cntrl2;
reg out;
always@(in1 or in2 or in3 or in4 or cntrl1 or cntrl2)
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endmodule
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reg[3:0] outtemp;
assign {none_on,outcode}=outtemp;
always @(a or b or c or d or e or f or g or h)
begin
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begin
begin
(Trace delay of b) + 0.2ns = 8.1ns
(Trace delay of b) = 7.9ns
A
(Trace delay of a) + 0.2ns = 11.1ns
(Trace delay of a) = 10.9ns

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1->0
0->1
A 3 ns Pulse generate (10.9-7.9 = 3ns)
Output C change back from “1” to “0” as the final result
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: C “0”



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