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8/8/2019 VERILOG HDL LECTUER1
http://slidepdf.com/reader/full/verilog-hdl-lectuer1 1/14
DIVYA SHAH24/02/09
Verilog Hardware DescriptionVerilog Hardware Description
LanguageLanguage
LECTUER-1
8/8/2019 VERILOG HDL LECTUER1
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WHY VERILOG
TO DESCRIBE DIGITAL CIRCUITS
GENERAL PURPOSE HARDW ARE DESCRIPTION LANGUAGE
SIMILAR IN SYNTAX TO C PROGRAMMI9NG LANGUAGE
DIFFERENT LEVEL OF ABSTRACTION MIXED IN THE SAME
MODEL(FROM BEHAVIORAL,DATAFLOW TO SWITCH LEVEL)
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DESIGN METHODOLOGIES
TOP-DOWN DESIGNDEFINE TOP LEVEL BLOCKS AND IDENTIFY THE SUB-BLOCKS
NECESSARY TO BUILD THE TOP LEVEL BLOCK.FURTER SUBDIVIDE
THE SUB-BLOCKS UNTIL GET THE LEAF-CELL BLOCKSWHICH CANT
BE DIVIDE FURTHER.
BOTTOM-UP DESIGNFIRST IDENTIFY THE BUILDING BLOCKS THAT ARE AVAILABLE .
THEN BUILD BIGGER CELL.THUS THESE CELLS USED FOR HIGHERLEVEL BLOCKS UNTILWE BUILD TOP LEVEL BLOCK IN DESIGN
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MODULE
In Verilog, the basic unit of hardware
is called a module.
Modules cannot contain definitions of
other modules.
A module can, however, be instantiated
within another module. Allows the creation of a hi erarc hy in a
Verilog description
8/8/2019 VERILOG HDL LECTUER1
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MODULE DECLARATION
module module_name (portlist);
<Port declarations>;
<module internals>; endmodule
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LEVELS OF ABSTRACTION
BEHAVIORAL OR ALGORITHMIC LEVEL:
Highest level of abstraction
No need to concern for the hardware implementation detail
Designing is very similar to c programming language
DATAFLOW LEVEL:
Specify the flow of data
Designer has to concern how the data flow occur b/w hardwareregister & how the data is procecssed in the design
GATE LEVEL:Implemented in terms of logic gates and interconnection b/w thesegates
Designing is same as describe a design in terms of gate level logicdiagram
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SWITCH LEVEL:
Lowest level of abstraction
Implemented in terms of switches,storage nodes and interconnection
b/w them
IMP:
Designer can mix and match all levels of abstraction
(e.g RTL: behavioral+dataflow)
Higher level of abstraction flexible and technology independent
design
Lower level of abstraction inflexible and technology dependent
design
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INSTANCES
THE PROCESS OF CREATING OBJECTS FROM A
MODULE TEMPLATE IS CALLED ³INSTANTIATION´
AND THE OBJECTS ARE CALLED ³INSTANCES´.
Example:
A 4-bit full adder is shown to you .it instantiates 4 one bit full adder
and again one bit full adder instantiates 2 xor,3 and & 2 or gates.
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Instantiating the module
Example: 4-bit full adder circuit
FA0
FA1FA2FA3
Cout Sum[3] Sum[2]
Sum[1] Sum[0]
cinIn1[0]In2[0]
c0
In1[1]In2[1]
c1
In1[2]In2[2]
c2
In1[3]In2[3]
8/8/2019 VERILOG HDL LECTUER1
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module fadd4(in1, in2, cin, sum,cout);input[3:0] in1,in2;
input cin;
output[3:0] sum;
output cout;wire[2:0] temp_cout;
fadd(in1[0],in2[0],cin,sum[0],temp_cout[0]);
fadd(in1[1],in2[1],temp_cout[0],sum[1],temp_cout[1]);
fadd(in1[2],in2[2],temp_cout[1],sum[2],temp_cout[2]);
fadd(in1[3],in2[3],temp_cout[2],sum[3],cout);
endmodule
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Structural model of a full adder circuit
module fadd(in1, in2, cin, sum,cout);
input in1,in2, cin;
output sum, cout;
wire x1,a1,a2,a3,o1,o2;
xor (x1,in1,in2);
xor (sum,x1,cin);
and(a1,in1,in2);
and(a2,in1,cin);
and(a3,in2,cin);or (o1, a1,a2);
or (cout,o1,a3);
endmodule
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STIMULAS BLOCK
A Verilog procedural block which
executes only once.
Used for simulation. Stimulas block also called testbench.
Testbench generates clock, reset, and
the required test vectors. Two style of stimulas application
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FIRST STYLE
HERE STIMULAS BLOCK INSTANTIATES THE DESIGN BLOCK AND
DIRECTLY DRIVE THE SIGNALS IN THE DESIGN BLOCK
CLK RESET
DESIGN BLOCK
Q
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SECOND STYLE
HERE STIMULAS AND DESIGN BLOCK BOTH ARE INSTANTIATES IN A
TOP LEVEL DUMMY MODULE.HERE STIMULAS BLOCK INTERACTS
WITH THE DESIGN BLOCK ONLY THROUGH THE INTERFACE.
STIMULASBLOCK
DESIGNBLOCK
CLK
RESET
Q
D_CLK
D_RESET
D_Q