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ModelSimModelSim : 툴 소개 및 사용법 툴 소개 및 사용법
한 동 일한 동 일
OutlineOutline
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Core ModelSim FeaturesCore ModelSim Features
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ModelSim GUIModelSim GUI
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HDL Design FlowHDL Design Flow
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The TestbenchThe Testbench
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OutlineOutline
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Design LibrariesDesign Libraries
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Creating Library from GUICreating Library from GUI
File>New>Library
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Creating LibrariesCreating Libraries
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Creating LibrariesCreating Libraries
R l lvlib dware
Real example
vmap work dwarevcom ../vhd_dware/dwmath.vhdvcom ../vhd_dware/dwpackages.vhdvlib dw02vmap work dw02vmap work dw02vcom ../vhd_dw02/dw02_components.vhdvcom ../vhd dw02/dw02 divide.vhd/ _ / _vlib workvmap work workvcom -explicit vm_pack.vhdvcom -explicit vhdl/fc_top_testbench.vhdvcom explicit vhdm/* vhd
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vcom -explicit vhdm/*.vhd
OutlineOutline
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Steps To Compile A DesignSteps To Compile A Design
File>New>Library
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File>New>Library
ModelSim ini fileModelSim ini file
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Compile Source CodeCompile Source Code
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Compile Source Code(cont’d)Compile Source Code(cont d)
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Compile Source Code(cont’d)Compile Source Code(cont d)Real example######### Design Compilation ############
vcom -explicit /homes/white3/hdtv_design/design_final_v1/vhdl_src/hd_pkg/vdec_pack.vhd
vcom -explicit /homes/white3/hdtv design/design final v1/vhdl src/hd core/VDEC/* vhd
Real example
vcom explicit /homes/white3/hdtv_design/design_final_v1/vhdl_src/hd_core/VDEC/ .vhd
#vcom -explicit /homes/white3/hdtv_design/design_final_v1/vhdl_src/hd_core/VDEC_MC/*.vhd
vcom -explicit /homes/king2/dihan/hdvsim/hdtop/VDEC_MC/*.vhd
vcom -explicit /homes/agnes2/scsong/hdtop/top_src/original/syn/991213/fc1/*.vhd
vcom -explicit /homes/white3/hdtv_design/design_final_v1/vhdl_src/hd_core/HDTP_TOP/*.vhd
vcom -explicit /homes/white3/hdtv_design/design_final_v1/vhdl_src/hd_pkg/gfx_pkg.vhd
vcom -explicit /homes/white3/hdtv_design/design_final_v1/vhdl_src/hd_core/GFX/*.vhd
vcom -explicit /homes/white3/hdtv design/design final v1/vhdl src/hd core/MBIST FSM/MBIST FSM vhdvcom -explicit /homes/white3/hdtv_design/design_final_v1/vhdl_src/hd_core/MBIST_FSM/MBIST_FSM.vhd
######### Register File Compilation ###########
vcom -explicit /homes/magenta3/hylyu/HDTV_V2/TOP/TESTBENCH/STRAM/*.vhd
######### Simulation Model Compilation #########
vcom -explicit /homes/magenta3/hylyu/HDTV_V2/TOP/TESTBENCH/hd_cpu_model_gate.vhd
vcom -explicit /homes/king3/dihan/hdvsim/hdtop/vhdl/image_store_ppm.vhd.1360
vcom -explicit /homes/magenta3/hylyu/HDTV_V2/TOP/TESTBENCH/sdram_top.vhd
vcom explicit /homes/king3/dihan/hdvsim/hdtop/vhdl/ext tb vhdvcom -explicit /homes/king3/dihan/hdvsim/hdtop/vhdl/ext_tb.vhd
######### Top Compilation ###########
vcom -explicit /homes/magenta3/hylyu/HDTV_V2/TOP/TESTBENCH/hd_core.vhd
vcom -explicit /homes/magenta3/hylyu/HDTV_V2/TOP/TESTBENCH/hd_core_tb.vhd
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#Dec 13vcom -explicit /homes/king2/dihan/hdvsim/hdtop/vhdm/v_host_size.vhd
#Top generation end.
Section SummarySection Summary
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Lab 1 : Compiling CodesLab 1 : Compiling Codes
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ModelSim ini file
M d lSi 이 i ll 된 di 에서
ModelSim.ini file
ModelSim이 install 된 directory에서ModelSim.ini파일의 내용 확인
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Run ModelSimRun ModelSim
R M d lSi PRun ModelSim ProgramCreate Projectj“File > New > Project” ClickProject NameProject Name
image_testP j t L tiProject Location
User directory/src/image_testDefault Library Name
work한번 생성 이후에는 File > Open > Project Click 후 원하는 프로젝트 선택
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Click 후 원하는 프로젝트 선택
Run ModelSimRun ModelSim
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<ModelSim Project 생성>
Add filesAdd files
U “Add E iti Fil ” Use “Add Exiting File” icon after project setting
tb image test.vhdtb_image_test.vhdcsmile.txtcsmile ppmcsmile.ppmwave.do
Use “Copy to project directory” option
User directory
y p혹은 탐색기를 이용하여직접 프로젝트에 복사
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직접 프로젝트에 복사
CompileCompile
After input All files and then CompileMenu “Compile > Compile All” ClickMenu Compile > Compile All ClickError 발생 시 디버깅
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OutlineOutline
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ModelSim WindowsModelSim Windows
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ModelSim Windows(cont’d)ModelSim Windows(cont d)
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1 Main Window1-Main Window
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2 Structure Window2-Structure Window
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3 Source Window3-Source Window
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4 Signals Window4-Signals Window
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5 Process Window5-Process Window
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6 Variable Window6-Variable Window
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7 Dataflow Window7-Dataflow Window
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8 Wave Window8-Wave Window
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9 List Window9-List Window
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Loading the DesignLoading the Design
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Loading the Design(cont’d)Loading the Design(cont d)
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Running Simulations & LoggingRunning Simulations & Logging
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Advanced Simulation TimeAdvanced Simulation Time
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Re running While LoadedRe-running While Loaded
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Two Types of BreakpointsTwo Types of Breakpoints
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Source Level DebugSource Level Debug
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Section SummarySection Summary
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Lab 2 : SimulationLab 2 : Simulation
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Simulation FlowSimulation FlowRGB 영상을 입력 받아 YCbC 로 변환 후 fil 로 저장RGB 영상을 입력 받아 YCbCr로 변환 후 file로 저장(2 clock 이후)역 변환 이 하여 다시 영상 변환역 변환을 이용하여 YCbCr을 다시 RGB영상으로 변환후 image_out_ppm으로 출력 (2 clock 이후)
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Input ImageInput ImageSmile 영상Smile 영상ppm file format
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Simulation Load DesignSimulation – Load Design
Menu “Simulate > Simulate ...” ClickClick “work” directoryS l “ b i ”Select “tb_image_test”in DesignClick “OK”ModelSim> Prompt ModelSim> Prompt changes to Simulation Mode VSIM>
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Simulation WaveformSimulation – WaveformMenu “View > Wave” ClickMenu View > Wave Clickfrom Wave window,
Select “File > Load Format…”
Select wave do fileSelect wave.do file
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Run SimulationRun SimulationType below in “VSIM>” command windowType below in VSIM> command window
run 25 ms
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Check OutputsCheck OutputsCheck output imagesInput Output1 Output2Check output images
p p p
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Check OutputsCheck OutputsCheck output filesCheck output files
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Waveform window testWaveform window test
Restart simulation and check and test many simulation functionsy
Menu “View > Structure” ClickMenu “View > Signals” ClickMenu View > Signals ClickAdd signals in waveform window - drag and dropdrop
In the waveform windowUse the zoom functionsInsert cursor, divider, breakpoints, etc.Insert cursor, divider, breakpoints, etc.
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Waveform window testWaveform window test
I th f i dIn the waveform windowChange Radix and Format of signals, etc.
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Waveform window testWaveform window testR lt f Ch R di d F t f i lResult of Change Radix and Format of signals
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OutlineOutline
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Full Timing SimulationsFull Timing Simulations
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Place & Route Output FilesPlace & Route Output Files
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Reading the SDFReading the SDF
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Reading the SDF(cont’d)Reading the SDF(cont d)
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Full Timing SummaryFull Timing Summary
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SummarySummary
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