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Vignana Bharathi Institute of Technology UNIT 3 DLD

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DLD

UNIT – III

Combinational Circuits (CC), Analysis procedure, Design Procedure, Combinational circuit for different code converters and other problems, Binary Adder-Subtractor, Decimal Adder, Binary Multiplier, Magnitude Comparator, Decoders, Encoders, Multiplexers, Demultiplexer.

VIDYA SAGAR P



Logic circuits may be combinational or sequential. • Combinational circuits: consist of logic gates whose outputs at any time are determined

from only the present combination of inputs. Combinational circuits have their operation specified logically by a set of Boolean functions.

• Sequential circuits: contain storage elements in addition to logic gates and have their outputs being a function of the inputs and the state of the storage elements which is a

function of previous inputs. Sequential circuits have their outputs depending not only on present values of inputs, but also on past inputs, and the circuit behavior must be

specified by a time sequence of inputs and internal states. A combinational circuit consists of an interconnection of logic gates.

Combinational circuits react to the values at their inputs and produce the value of the output signal, transforming binary information from the given input data to a required

output data. A block diagram of a combinational circuit is shown below.

The n inputs come from an external source; the m outputs are produced by the

combinational circuit and go to an external destination.

Each input and output is actually an analog electrical signal whose values are interpreted to be a binary signal that represents logic 1 and logic 0.

ANALYSIS PROCEDURE:

The analysis of a combinational circuit requires that we determine the function that the circuit

implements. This task starts with a given logic diagram and culminates with a set of Boolean

functions, a truth table, or, possibly, an explanation of the circuit operation.

If the logic diagram to be analyzed is accompanied by a function name or an explanation of

what it is assumed to accomplish, then the analysis problem reduces to a verification of the

stated function. The analysis can be performed manually by finding the Boolean functions or

truth table or by using a computer simulation program.

The first step in the analysis is to make sure that the given circuit is combinational and not

sequential. The diagram of a combinational circuit has logic gates with no feedback paths

or memory elements. A feedback path is a connection from the output of one gate to the

input of a second gate whose output forms part of the input to the first gate. Feedback paths

in a digital circuit define a sequential circuit and must be analyzed by special methods and

will not be considered here.

Once the logic diagram is verified to be that of a combinational circuit, one can proceed to

obtain the output Boolean functions or the truth table. If the function of the circuit is under

investigation, then it is necessary to interpret the operation of the circuit from the derived

Boolean functions or truth table. The success of such an investigation is enhanced if one has

previous experience and familiarity with a wide variety of digital circuits.



To obtain the output Boolean functions from a logic diagram, we proceed as follows:

1. Label all gate outputs that are a function of input variables with arbitrary symbols—but

with meaningful names. Determine the Boolean functions for each gate output.

2. Label the gates that are a function of input variables and previously labeled gates with

other arbitrary symbols. Find the Boolean functions for these gates.

3. Repeat the process outlined in step 2 until the outputs of the circuit are obtained.

4. By repeated substitution of previously defined functions, obtain the output Boolean

functions in terms of input variables.

The analysis of the combinational circuit of Fig. 4.2 illustrates the proposed procedure.

We note that the circuit has three binary inputs A, B, and C and two binary outputs F1 and

F2. The outputs of various gates are labeled with intermediate symbols.

The outputs of gates that are a function only of input variables are T1 and T2. Output F2 can

easily be derived from the input variables. The Boolean functions for these three outputs are

F2 = AB + AC + BC

T1 = A + B + C

T2 = ABC

Next, we consider outputs of gates that are a function of already defined symbols:

T3 = F’2T1; F1 = T3 + T2

To obtain F1 as a function of A, B, and C, we form a series of substitutions as follows:



The derivation of the truth table for a circuit is a straightforward process once the output

Boolean functions are known. To obtain the truth table directly from the logic diagram without

going through the derivations of the Boolean functions, we proceed as follows:

1. Determine the number of input variables in the circuit. For n inputs, form the 2n possible

input combinations and list the binary numbers from 0 to (2n - 1) in a table.

2. Label the outputs of selected gates with arbitrary symbols.

3. Obtain the truth table for the outputs of those gates which are a function of the input

variables only.

4. Proceed to obtain the truth table for the outputs of those gates which are a function of

previously defined values until the columns for all outputs are determined.

This process is illustrated with the circuit of Fig. 4.2 . In Table 4.1 , we form the eight possible

combinations for the three input variables. The truth table for F2 is determined directly from

the values of A , B , and C , with F2 equal to 1 for any combination that has two or three

inputs equal to 1. The truth table for F_2 is the complement of F2. The truth tables for T1 and

T2 are the OR and AND functions of the input variables, respectively. The values for T3 are

derived from T1 and F_2:T3 is equal to 1 when both T1 and F_2 are equal to 1, and T3 is equal

to 0 otherwise. Finally, F1 is equal to 1 for those combinations in which either T2 or T3 or

both are equal to 1. Inspection of the truth table combinations for A, B, C, F1, and F2 shows

that it is identical to the truth table of the full adder given in Section 4.5 for x, y, z, S , and C

, respectively.

DESIGN PROCEDURE:

The design of combinational circuits starts from the specification of the design objective and

culminates in a logic circuit diagram or a set of Boolean functions from which the logic

diagram can be obtained. The procedure involves the following steps:

1. From the specifications of the circuit, determine the required number of inputs and outputs

and assign a symbol to each.

2. Derive the truth table that defines the required relationship between inputs and outputs.

3. Obtain the simplified Boolean functions for each output as a function of the input variables.

4. Draw the logic diagram and verify the correctness of the design (manually or by simulation).



A truth table for a combinational circuit consists of input columns and output columns. The

input columns are obtained from the 2n binary numbers for the n input variables. The binary

values for the outputs are determined from the stated specifications. The output functions

specified in the truth table give the exact definition of the combinational circuit. It is important

that the verbal specifications be interpreted correctly in the truth table, as they are often

incomplete, and any wrong interpretation may result in an incorrect truth table.

Code Conversion Example:

To convert from binary code A to binary code B, the input lines must supply the bit

combination of elements as specified by code A and the output lines must generate the

corresponding bit combination of code B. A combinational circuit performs this

transformation by means of logic gates. The design procedure will be illustrated by an example

that converts binary coded decimal (BCD) to the excess-3 code for the decimal digits.

Since each code uses four bits to represent a decimal digit, there must be four input variables

and four output variables. We designate the four input binary variables by the symbols A, B,

C, and D, and the four output variables by w, x, y , and z . The truth table relating the input

and output variables is shown in Table 4.2 . The bit combinations for the inputs and their

corresponding outputs are obtained directly from Section 1.7. Note that four binary variables

may have 16 bit combinations, but only 10 are listed in the truth table. The six bit

combinations not listed for the input variables are don’t-care combinations. These values have

no meaning in BCD and we assume that they will never occur in actual operation of the circuit.

Therefore, we are at liberty to assign to the output variables either a 1 or a 0, whichever gives

a simpler circuit.

The maps in Fig. 4.3 are plotted to obtain simplified Boolean functions for the outputs. Each

one of the four maps represents one of the four outputs of the circuit as a function of the four

input variables. The 1’s marked inside the squares are obtained from the minterms that make

the output equal to 1. The 1’s are obtained from the truth table by going over the output

columns one at a time. For example, the column under output z has five 1’s; therefore, the

map for z has five 1’s, each being in a square corresponding to the minterm that makes z

equal to 1. The six don’t-care minterms 10 through 15 are marked with an X . One possible

way to simplify the functions into sum-of-products form is listed under the map of each

variable.

A two-level logic diagram for each output may be obtained directly from the Boolean

expressions derived from the maps. There are various other possibilities for a logic diagram

that implements this circuit. The expressions obtained in Fig. 4.3 may be manipulated

algebraically for the purpose of using common gates for two or more outputs. This

manipulation, shown next, illustrates the flexibility obtained with multiple-output systems

when implemented with three or more levels of gates:



The logic diagram that implements these expressions is shown in Fig. 4.4. Note that the OR

gate whose output is C + D has been used to implement partially each of three outputs. Not

counting input inverters, the implementation in sum-of-products form requires seven AND

gates and three OR gates. The implementation of Fig. 4.4 requires four AND gates, four OR

gates, and one inverter. If only the normal inputs are available, the first implementation will

require inverters for variables B, C, and D, and the second implementation will require

inverters for variables B and D. Thus, the three-level logic circuit requires fewer gates, all of

which in turn require no more than two inputs.



Adders

In electronics, an adder or summer is a digital circuit that performs addition of numbers. In

modern computers adders reside in the arithmetic logic unit (ALU) where other operations are

performed. Although adders can be constructed for many numerical representations, such as

Binary-coded decimal or excess-3, the most common adders operate on binary numbers. In

cases where twos complement or ones complement is being used to represent negative

numbers, it is trivial to modify an adder into an adder-subtracter. Other signed number

representations require a more complex adder.

Half Adder

A half adder is a logical circuit that performs an addition operation on two binary digits. The

half adder produces a sum and a carry value which are both binary digits.

A half adder has two inputs, generally labelled A and B, and two outputs, the sum S and carry

C. S is the two-bit XOR of A and B, and C is the AND of A and B. Essentially the output of a

half adder is the sum of two one-bit numbers, with C being the most significant of these two

outputs.

The drawback of this circuit is that in case of a multibit addition, it cannot include a carry.

Equation of the Sum and Carry.

Sum=A′B+AB′; Carry=AB; 0 + 0 = 0; 0 + 1 = 1; 1 + 0 = 1; 1 + 1 = 10;

One can see that Sum can also be implemented using XOR gate as A B

Following is the truth table for a half adder:



A B Carry Sum

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

• sum of products Exclusive-OR and AND

Full Adder:

A full adder has three inputs X, Y, and a carry in Z, such that multiple adders can be used to

add larger numbers. To remove ambiguity between the input and output carry lines, the carry

in is labelled Ci or Cin while the carry out is labelled Co or Cout.

A full adder is a logical circuit that performs an addition operation on three binary digits. The

full adder produces a sum and carry value, which are both binary digits. It can be combined

with other full adders or work on its own.



A full adder can be trivially built using our ordinary design methods for combinatorial circuits.

Here is the resulting circuit diagram using NAND gates only:

Co=A′BCi+AB′Ci+ABCi′+ABCi by manipulating Co, we can see thatCo= Ci(A B)+AB; S=A′B′Ci

+A′BCi′+ABCi′+ABCi By manipulating S, we can see that S=Ci (A B)

A full adder can be constructed from two half adders by connecting A and B to the input of

one half adder, connecting the sum from that to an input to the second adder, connecting Ci

to the other input and OR the two carry outputs. Equivalently, S could be made the three-bit

xor of A, B, and Ci and Co could be made the three-bit majority function of A, B, and Ci. The

output of the full adder is the two-bit arithmetic sum of three one-bit numbers.



Binary Adder :

• A binary adder can be constructed with full adders connected in cascade, with the output

carry from each full adder connected to the input carry of the next full adder in the chain

(called ripple-carry adder).

• Example: 4-bit binary adder Ripple carry adder

The layout of ripple carry adder is simple, which allows for fast design time; however, the

ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be

calculated from the previous full adder. The gate delay can easily be calculated by inspection

of the full adder circuit. Following the path from Cin to Cout shows 2 gates that must be passed

through. Therefore, a 32-bit adder requires 31 carry computations and the final sum

calculation for a total of 31 * 2 + 1 = 63 gate delays.

Carry Look-ahead Adder

The carry propagation delay can be reduced using look-ahead carry (more complex

mechanism, yet faster)

Two signals defined:

The carry signals of the adder become

• C3 does not have to wait for C2 and C1 to propagate; in fact, C3 is propagated at the same

time as C1 and C2.

• It means that all the Ci’s depend on Pi, Gi, and C0 directly.

Carry Look-ahead Generator:





Subtractor :

In electronics, a subtractor can be designed using the same approach as that of an adder. The

binary subtraction process is summarized below. As with an adder, in the general case of

calculations on multi-bit numbers, three bits are involved in performing the subtraction for

each bit: the minuend (Xi), subtrahend (Yi), and a borrow in from the previous (less significant)

bit order position (Bi). The outputs are the difference bit (Di) and borrow bit Bi + 1.

Half subtractor :

The half-subtractor is a combinational circuit which is used to perform subtraction of two

bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B

(borrow). Such a circuit is called a half -subtractor because it enables a borrow out of the

current arithmetic operation but no borrow in from a previous arithmetic operation.

The truth table for the half subtractor is given below. D=X′Y+XY′ or D= X Y; B=X′Y

Full Subtractor

As in the case of the addition using logic gates , a full subtractor is made by combining two

half-subtractors and an additional OR-gate. A full subtractor has the borrow in capability

(denoted as BORIN in the diagram below) and so allows cascading which results in the

possibility of multi-bit subtraction.

The final truth table for a full subtractor looks like;The circuit diagram for a full subtractor is

given below.

A B BORIN D BOROUT

0 0 0 0 0

0 0 1 1 1

0 1 0 1 0

0 1 1 0 0

1 0 0 1 1

1 0 1 0 1

1 1 0 0 0

1 1 1 1 1

X Y D B

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0



N-Bit Parallel Subtractor:

The subtraction can be carried out by taking the 1's or 2's complement of the number to be

subtracted. For example we can perform the subtraction (A-B) by adding either 1's or 2's

complement of B to A. That means we can use a binary adder to perform the binary

subtraction.

4 Bit Parallel Subtractor

The number to be subtracted (B) is first passed through inverters to obtain its 1's

complement. The 4-bit adder then adds A and 2's complement of B to produce the subtraction.

S3 S2 S1 S0 represents the result of binary subtraction (A-B) and carry output Cout represents

the polarity of the result. If A > B then Cout = 0 and the result of binary form (A-B) then Cout

= 1 and the result is in the 2's complement form.

Block diagram



Binary Adder-Subtractor :

Our binary adder can already handle negative numbers as indicated in the section on binary

arithmetic But we have not discussed how we can get it to handle subtraction. To see how

this can be done, notice that in order to compute the expression x - y, we can compute the

expression x + -y instead. We know from the section on binary arithmetic how to negate a

number by inverting all the bits and adding 1. Thus, we can compute the expression as x +

inv(y) + 1. It suffices to invert all the inputs of the second operand before they reach the adder,

but how do we add the 1. That seems to require another adder just for that. Luckily, we have

an unused carry-in signal to position 0 that we can use. Giving a 1 on this input in effect adds

one to the result. The complete circuit with addition and subtraction looks like this:

A - B = A + (2’s complement of B)

• 4-bit adder-subtractor – M = 0 →A + B; M = 1 → A + B’ + 1

• Output V is for detecting an overflow.



Decimal Adder:

Add two BCD's

9 inputs: two BCD's and one carry-in

5 outputs: one BCD and one carry-out

Design approaches

A truth table with 29 entries

use binary full Adders

» the decimal sum must be not larger than 19 (= 9 + 9 + 1)

» the BCD sum is no larger than 9; (S8S4S2S1) ≦ (1001)

The Sum of a BCD Adder :



BCD Adjustment

• When the binary sum is equal to or less than 1001, the corresponding BCD number is

identical, no conversion is needed.

• When the binary sum is greater than 1001, an addition of 6 (0110) converts it to the correct

BCD representation and also produces an output carry as required.

• Modifications are needed if the sum > 9 (1001)– C must be set to 1, if

• When C = 1, add 0110 to the binary sum.



Binary Multiplier

• Performed in the same way as multiplication of decimal numbers.

• Partial products: AND operations.

• 2-bit × 2-bit → 4-bit (n × n → 2n bits)

For J multiplier and K multiplicand bits, we need (J × K) AND gates and (J - 1) K-bit

adders to produce a product of (J + K) bits.

• K = 4 and J = 3:

12 AND gates and two 4-bit adders: produce a 7-bit product.



General Form:

Array Multiplier :



Magnitude Comparator

A magnitude comparator compares two numbers A and B and determines their relative

magnitudes. The results of comparison between two numbers are: A > B, A = B, A < B

Design Approaches: The truth table for two n-bit numbers comparison» 22n entries - too

cumbersome for large n use inherent regularity of the problem (algorithm

approach);algorithm— a procedure which specifies a finite set of steps, reduce design efforts;

reduce human errors.

Consider two 4-bit numbers, A = A3A2A1A0, B = B3B2B1B0

o A and B are equal (A = B) if A3 = B3, A2 = B2, A1 = B1, and A0 = B0.

o The equality of each pair of bits can be expressed with an exclusive-NOR function as:

o xi = AiBi + Ai’ Bi’ for i = 0, 1, 2, 3; xi = (Ai’Bi + AiBi’)’;xi = 1 only if the pair of bits in position i

are equal (both are 1 or both are 0).For equality to exist (A = B), all xi variables must be equal

to 1: (A = B) = x3x2x1x0;To determine whether (A > B) or (A < B), starting from the MSB, if the

two bits are equal, then compare the next lower significant pair of bits until a pair of unequal

bits is reached.

o If the corresponding bit of A is 1 and that of B is 0, we conclude that A > B.

o If the corresponding digit of A is 0 and that of B is 1, we have A < B.

o The sequential comparison can be expressed by the two Boolean functions

(A > B) = A3B3’ + x3A2B2’ + x3x2A1B1’ + x3x2x1A0B0’

(A < B) = A3’B3 + x3A2’B2 + x3x2A1’B1 + x3x2x1A0’B0



Decoders: A decoder converts binary information from n input lines to a maximum of 2n

unique output lines.

A n-to-m decoder (m ≦ 2n); a binary code of n bits has 2n distinct information with n input

variables; up to 2n output lines only one output can be active (high) at any time.

Two-to-four Decoder with Enable:

• Enable input is added to control the circuit operation.



Decoder Expansion:

3 to 8 Decoder: We know that 2 to 4 Decoder has two inputs, A1 & A0 and four outputs,

Y3 to Y0. Whereas, 3 to 8 Decoder has three inputs A2, A1 & A0 and eight outputs, Y7

to Y0.

We can find the number of lower order decoders required for implementing higher

order decoder using the following formula.

Required number of lower order decoders=m2/m1

Where, m1 is the number of outputs of lower order decoder.

m2 is the number of outputs of higher order decoder.

Here, m1= 4 and m2= 8. Substitute, these two values in the above formula.

Required number of 2to4 decoders =8/4=2

Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder. The

block diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the following figure.

The parallel inputs A1 & A0 are applied to each 2 to 4 decoder. The complement of

input A2 is connected to Enable, E of lower 2 to 4 decoder in order to get the outputs,

Y3 to Y0. These are the lower four min terms. The input, A2 is directly connected to

Enable, E of upper 2 to 4 decoder in order to get the outputs, Y7 to Y4. These are the

higher four min terms.



• Expand two 3-to-8 decoder with Enable to a 4-to-16 decoder

Universal Combinational Logic Implementation :

A decoder provides the 2n minterms of n input variables.

A decoder and an external OR gate can implement any Boolean function of n input variables

in sum-of-minterm form.

• For example, a full-adder has its sum S(x,y,z) =∑ (1,2,4,7) and carry C(x,y,z) =∑ (3,5,6,7).

Encoders:

The inverse function of a decoder and has 2n (or fewer) input lines and n output lines.

The output lines generate the binary code corresponding to the input value.

• Example:



Priority Encoder:

Encoder that includes the priority function; Resolve the ambiguity of illegal inputs, only one

of the input is encoded, the input having the highest priority will take precedence.

• Example: D3 has the highest priority

» D0 has the lowest priority

» X: don't-care conditions

» V: valid output indicator

x = D2 + D3

y = D3 + D1 D2’

V = D0 + D1 + D2 + D3

Multiplexers:

Select from one of many inputs and passes it to a single output, controlled by a set of

selection lines. A multiplexer is also called a data selector.

• Normally, there are 2n inputs and n selection lines whose bit combinations

determine which input is selected.

• Example: (two-to-one multiplexer)



Quadruple 2-to-1 Multiplexer:

Implementation of Higher-order Multiplexers.

Now, let us implement the following two higher-order Multiplexers using lower-order

Multiplexers.

8x1 Multiplexer

16x1 Multiplexer

8x1 Multiplexer

In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1

Multiplexer. We know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and

one output. Whereas, 8x1 Multiplexer has 8 data inputs, 3 selection lines and one

output.



So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs.

Since, each 4x1 Multiplexer produces one output, we require a 2x1 Multiplexer in

second stage by considering the outputs of first stage as inputs and to produce the

final output.

Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 & s0

and one output Y. The Truth table of 8x1 Multiplexer is shown below.

Selection Inputs Output

S2 S1 S0 Y

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

We can implement 8x1 Multiplexer using lower order Multiplexers easily by

considering the above Truth table. The block diagram of 8x1 Multiplexer is shown

in the following figure.

The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data

inputs of upper 4x1 Multiplexer are I7 to I4 and the data inputs of lower 4x1

Multiplexer are I3 to I0. Therefore, each 4x1 Multiplexer produces an output based

on the values of selection lines, s1 & s0.



The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer

that is present in second stage. The other selection line, s2 is applied to 2x1

Multiplexer.

If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I3 to

I0 based on the values of selection lines s1 & s0.

If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I7 to

I4 based on the values of selection lines s1 & s0.

Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer

performs as one 8x1 Multiplexer.

16x1 Multiplexer

In this section, let us implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1

Multiplexer. We know that 8x1 Multiplexer has 8 data inputs, 3 selection lines and

one output. Whereas, 16x1 Multiplexer has 16 data inputs, 4 selection lines and one

output.

So, we require two 8x1 Multiplexers in first stage in order to get the 16 data inputs.

Since, each 8x1 Multiplexer produces one output, we require a 2x1 Multiplexer in

second stage by considering the outputs of first stage as inputs and to produce the

final output.

Let the 16x1 Multiplexer has sixteen data inputs I15 to I0, four selection lines s3 to s0

and one output Y. The Truth table of 16x1 Multiplexer is shown below.

Selection Inputs Output

S3 S2 S1 S0 Y

0 0 0 0 I0

0 0 0 1 I1

0 0 1 0 I2

0 0 1 1 I3

0 1 0 0 I4

0 1 0 1 I5

0 1 1 0 I6

0 1 1 1 I7

1 0 0 0 I8

1 0 0 1 I9

1 0 1 0 I10

1 0 1 1 I11

1 1 0 0 I12

1 1 0 1 I13

1 1 1 0 I14

1 1 1 1 I15



We can implement 16x1 Multiplexer using lower order Multiplexers easily by

considering the above Truth table. The block diagram of 16x1 Multiplexer is shown


The same selection lines, s2, s1 & s0 are applied to both 8x1 Multiplexers. The data

inputs of upper 8x1 Multiplexer are I15 to I8 and the data inputs of lower 8x1

Multiplexer are I7 to I0. Therefore, each 8x1 Multiplexer produces an output based

on the values of selection lines, s2, s1 & s0.

The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1 Multiplexer

that is present in second stage. The other selection line, s3 is applied to 2x1

Multiplexer.

If s3 is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs Is7

to I0 based on the values of selection lines s2, s1 & s0.

If s3 is one, then the output of 2x1 Multiplexer will be one of the 8 inputs I15 to

I8 based on the values of selection lines s2, s1 & s0.

Therefore, the overall combination of two 8x1 Multiplexers and one 2x1 Multiplexer

performs as one 16x1 Multiplexer.

Boolean Function Implementation:

MUX has a structure composed of a decoder and an OR gate 2n-to-1 MUX can implement any

Boolean function of n+1 input variables.n of these input variables are used as the selection

lines. The remaining single variable is used for the data inputs. If the single variable is denoted

by z, each data input of the multiplexer will be z, z’, 1, or 0.



Demultiplexer:

A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and

distributes it over several outputs. It has only one input, n outputs, m select input. At a time

only one output line is selected by the select lines and the input is transmitted to the selected

output line. A de-multiplexer is equivalent to a single pole multiple way switch as shown in

fig.

Demultiplexers come in multiple variations.

1 : 2 demultiplexer

1 : 4 demultiplexer

1 : 16 demultiplexer

1 : 32 demultiplexer

1x4 De-Multiplexer :

1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and four outputs Y3, Y2, Y1

&Y0. The block diagram of 1x4 De-Multiplexer is shown in the following figure.

The single input ‘I’ will be connected to one of the four outputs, Y3 to Y0 based on the values

of selection lines s1 & s0. The Truth table of 1x4 De-Multiplexer is shown below.

Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From the above Truth table, we can directly write the Boolean functions for each output as

Y3=S1’ S0’

Y2= S1’ S0

Y1= S1 S0’

Y0= S1 S0



We can implement these Boolean functions using Inverters & 3-input AND gates. The circuit

diagram of 1x4 De-Multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can implement

1x8 De-Multiplexer and 1x16 De-Multiplexer by following the same procedure.

1x4 De-Multiplexer WITH Enable :

Block diagram

Truth Table:

Implementation of Higher-order De-Multiplexers

Now, let us implement the following two higher-order De-Multiplexers using lower-order De-

Multiplexers.

1x8 De-Multiplexer

1x16 De-Multiplexer

1x8 De-Multiplexer

In this section, let us implement 1x8 De-Multiplexer using 1x4 De-Multiplexers and 1x2 De-

Multiplexer. We know that 1x4 De-Multiplexer has single input, two selection lines and four

outputs. Whereas, 1x8 De-Multiplexer has single input, three selection lines and eight

outputs.

So, we require two 1x4 De-Multiplexers in second stage in order to get the final eight outputs.

Since, the number of inputs in second stage is two, we require 1x2 DeMultiplexer in first



stage so that the outputs of first stage will be the inputs of second stage. Input of this 1x2 De-

Multiplexer will be the overall input of 1x8 De-Multiplexer.

Let the 1x8 De-Multiplexer has one input I, three selection lines s2, s1 & s0 and outputs Y7 to

Y0. The Truth table of 1x8 De-Multiplexer is shown below.

Selection Inputs Outputs

s2 s1 s0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 I

0 0 1 0 0 0 0 0 0 I 0

0 1 0 0 0 0 0 0 I 0 0

0 1 1 0 0 0 0 I 0 0 0

1 0 0 0 0 0 I 0 0 0 0

1 0 1 0 0 I 0 0 0 0 0

1 1 0 0 I 0 0 0 0 0 0

1 1 1 I 0 0 0 0 0 0 0

We can implement 1x8 De-Multiplexer using lower order Multiplexers easily by considering

the above Truth table. The block diagram of 1x8 De-Multiplexer is shown in the following

figure.

The common selection lines, s1 & s0 are applied to both 1x4 De-Multiplexers. The outputs of

upper 1x4 De-Multiplexer are Y7 to Y4 and the outputs of lower 1x4 De-Multiplexer are Y3 to

Y0.

The other selection line, s2 is applied to 1x2 De-Multiplexer. If s2 is zero, then one of the four

outputs of lower 1x4 De-Multiplexer will be equal to input, I based on the values of selection

lines s1 & s0. Similarly, if s2 is one, then one of the four outputs of upper 1x4 DeMultiplexer

will be equal to input, I based on the values of selection lines s1 & s0.



1x16 De-Multiplexer

In this section, let us implement 1x16 De-Multiplexer using 1x8 De-Multiplexers and 1x2 De-

Multiplexer. We know that 1x8 De-Multiplexer has single input, three selection lines and eight

outputs. Whereas, 1x16 De-Multiplexer has single input, four selection lines and sixteen

outputs.

So, we require two 1x8 De-Multiplexers in second stage in order to get the final sixteen

outputs. Since, the number of inputs in second stage is two, we require 1x2 DeMultiplexer

in first stage so that the outputs of first stage will be the inputs of second stage. Input of this

1x2 De-Multiplexer will be the overall input of 1x16 De-Multiplexer.

Let the 1x16 De-Multiplexer has one input I, four selection lines s3, s2, s1 & s0 and outputs

Y15 to Y0. The block diagram of 1x16 De-Multiplexer using lower order Multiplexers is shown


The common selection lines s2, s1 & s0 are applied to both 1x8 De-Multiplexers. The outputs

of upper 1x8 De-Multiplexer are Y15 to Y8 and the outputs of lower 1x8 DeMultiplexer are Y7

to Y0.

The other selection line, s3 is applied to 1x2 De-Multiplexer. If s3 is zero, then one of the eight

outputs of lower 1x8 De-Multiplexer will be equal to input, I based on the values of selection

lines s2, s1 & s0. Similarly, if s3 is one, then one of the 8 outputs of upper 1x8 De-Multiplexer

will be equal to input, I based on the values of selection lines s2, s1 & s0.



Applications of Demultiplexer:

1. Demultiplexer is used to connect a single source to multiple destinations. The main

application area of demultiplexer is communication system where multiplexer are used. Most

of the communication system are bidirectional i.e. they function in both ways (transmitting

and receiving signals). Hence, for most of the applications, the multiplexer and demultiplexer

work in sync. Demultiplexer are also used for reconstruction of parallel data and ALU circuits.

2. Communication System – Communication system use multiplexer to carry multiple data

like audio, video and other form of data using a single line for transmission. This process

make the transmission easier. The demultiplexer receive the output signals of the multiplexer

and converts them back to the original form of the data at the receiving end. The multiplexer

and demultiplexer work together to carry out the process of transmission and reception of

data in communication system.

3. ALU (Arithmetic Logic Unit) – In an ALU circuit, the output of ALU can be stored in multiple

registers or storage units with the help of demultiplexer. The output of ALU is fed as the data

input to the demultiplexer. Each output of demultiplexer is connected to multiple register

which can be stored in the registers.

4. Serial to parallel converter – A serial to parallel converter is used for reconstructing parallel

data from incoming serial data stream. In this technique, serial data from the incoming serial

data stream is given as data input to the demultiplexer at the regular intervals. A counter is

attach to the control input of the demultiplexer. This counter directs the data signal to the

output of the demultiplexer where these data signals are stored. When all data signals have

been stored, the output of the demultiplexer can be retrieved and read out in parallel.



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