Vivado Design Suite Tcl コマンドリファレンスガイド … · VivadoDesignSuiteTclコマンドリファレンスガイド UG835(v2012.3)2012年10月16日 2 . 第1章概要

Vivado Design Suite Tcl

UG835 (v 2012.3) 2012 10 16

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(v 2012.3)

[email protected]

Vivado Design Suite Tcl UG835 (v 2012.3) 2012 10 16 http://japan.xilinx.com 2

http://www.xilinx.com/warranty.htmhttp://www.xilinx.com/warranty.htm#critapps

1

Vivado Tcl

Tcl (Tool Command Language) Vivado Tcl

SDC (Synopsys Design Constraints)

SDC Synopsis Synplify FPGA

Tcl

Tcl

Tcl

Vivado Tcl

: Tcl Tcl Vivado Tcl

Tcl

Vivado vivado.log vivado.jou Tcl Tcl

: vivado.jou_bakup 1 Tcl


UG835 (v 2012.3) 2012 10 16 http://japan.xilinx.com 3

Tcl

Tcl help Tcl

help : Tcl

help

File I/O

help -category category :

help -category object

Tcl

help pattern :

help get_*

get_ Tcl

help command :

help get_cells

get_cells

help -args command :

help -args get_cells

help -syntax command :

help -syntax get_cells

Vivado

Vivado 3

GUI ()

Tcl Vivado ( )

Tcl



Vivado 2 Tcl

1. installdir/Vivado/version/scripts/init.tcl

2. userdir/Xilinx/Vivado/init.tcl

:

installdir : Vivado Design Suite

userdir :

Windows 7 : %APPDATA%/Roaming/Xilinx/Vivado/init.tcl

Windows XP : %APPDATA%/Xilinx/Vivado/init.tcl

Linux : $HOME/.Xilinx/Vivado/init.tcl

init.tcl

init.tcl

Vivado

init.tcl

init.tcl

init.tcl Tcl Vivado Tcl init.tcl Tcl

source path_to_file/file_name.tcl

Tcl

Tcl OS Linux (/)


Tcl

Tcl 1 GUI Vivado

(IDE) Tcl [Tools] [Run Tcl Script]

Tcl

source file_name

Tcl Vivado IDE IDE

OS

(kill)



Tcl helphelphelp sourcesourcesourcesourcesourcesource

eval

Tcl Tcl

Tcl evalevaleval Tcl

help -category-category-category 1

help -category ipflow

set cat ipflow

:

setsetset : Tcl

catcatcat :

"ipflow""ipflow""ipflow" :

Tcl

eval help -category $cat

set cat -category ipflow

eval help $cat

() ({})

set runblocksOptDesignOpts { -sweep -retarget -propconst -remap }

eval opt_design $runblocksOptDesignOpts

Tcl helphelphelp evalevalevalevalevaleval

Tcl Tcl

( {} )



: [] Tcl () 4

Vivado

add_wave {bus[4]}

Tcl

add_wave bus(4)

Verilog : Verilog Verilog Verilog

(\)

Tcl

: Tcl

VHDL

my wire Vivado

add_wave {\my wire }

:

Verilog Tcl

w Vivado

Vivado

add_wave {\w }

w

add_wave w

VHDL : VHDL Tcl (\)

( \} )Tcl VHDL

Tcl \my sig\

add_wave \\my\ sig\\

: 2


command [optional_parameters] required_parameters



( _ ) - - -

get_

set_

report_

get_cells -help

get_cells

Description:

Get a list of cells in the current design

Syntax:

get_cells [-hsc arg ] [-hierarchical] [-regexp] [-nocase] [-filter arg ]

[-of_objects args ] [-match_style arg ] [-quiet] [ patterns ]

Returns:

list of cell objects

Usage:

Name Optional Default Description

---------------------------------------------

-hsc yes / Hierarchy separator

-hierarchical yes Search level-by-level in current instance

-regexp yes Patterns are full regular expressions

-nocase yes Perform case-insensitive matching (valid

only when -regexp specified)

-filter yes Filter list with expression

-of_objects yes Get cells of these pins or nets

-match_style yes sdc Style of pattern matching, valid values are

ucf, sdc

-quiet yes Ignore command errors

patterns yes * Match cell names against patterns

Categories:

SDC, XDC, Object

Tcl Tcl Vivado



OS exec

OS

Tcl

Tcl

0 1

Tcl Tcl catch

catch // Tcl

Vivado Tcl TCL_OK TCL_ERROR Tcl

$ERRORINFO

$ERRORINFO Tcl

puts $ERRORINFO

Tcl (procs.tcl)

(loads) 5

Line 1: Vivado % source procs.tcl

Line 2: Vivado% loads

Line 3: Found 180 driving FFs

Line 4: Processing pin a_reg_reg[1]/Q...

Line 5: ERROR: [HD-Tcl 53] Cannot specify -patterns with -of_objects.

Line 6: Vivado% puts $errorInfo

Line 7: ERROR: [HD-Tcl 53] Cannot specify -patterns with -of_objects. While executing

"get_ports -of objects $pin" (procedure "my_report" line 6) invoked from within procs.tcl

Tcl catch puts $errorInfo Tcl puts $errorInfo

6 puts $errorInfo7

Tcl




Vivado Design Suite

LUTI/O RAMDSP

I/O FPGA

1

DCMPLLMMCM UCF TIMESPEC

PERIOD

Tcl get_

get_object_type pattern

pattern

get_cells */inst_1

inst_1

get_cells -hierarchical inst_1

inst_1

help get_cells

get_cells -help



get_property property_name object

lib_cell UniSim

get_property lib_cell [get_cell inst_1]

report_propertyreport_propertyreport_property

report_property [get_cells inst_1]

bel OLOGICE1.OUTFF string

class cell string

iob TRUE string

is_blackbox 0 bool

is_fixed 0 bool

is_partition 0 bool

is_primitive 1 bool

is_reconfigurable 0 bool

is_sequential 1 bool

lib_cell FD string

LOC OLOGIC_X1Y27 string

name error string

primitive_group FD_LD string

primitive_subgroup flop string

site OLOGIC_X1Y27 string

type FD & LD string

XSTLIB 1 bool

UCF HDL

Tcl set_property

set_property loc OLOGIC_X1Y27 [get_cell inst_1]



get_*

FD

get_cells * -hierarchical -filter lib_cell == FD

=~

get_cells * -hierarchical -filter lib_cell =~ FD*

OR (||) AND (&&)

get_cells * -hierarchical filter {lib_cell =~ FD* && loc != }

: " " { } Tcl loc

Tcl ()

Tcl foreach_in_collection

Tcl foreachforeachforeach

GUI Tcl Tcl get_*get_*get_*

...

1

()

get_cells inst_1

inst_1

get_cells * -hierarchical

XST_VCC XST_GND error readIngressFifo wbDataForInputReg fifoSelect_0 fifoSelect_1 fifoSelect_2 fifoSelect_3 ...

%set x [get_cells * -hierarchical]

XST_VCC XST_GND error readIngressFifo wbDataForInputReg fifoSelect_0 fifoSelect_1 fifoSelect_2 fifoSelect_3 ...

%lindex $x end

bftClk_BUFGP/bufg

%llength $x

4454

4000 ...

Tcl



get_*get_*get_* -of-of-of

get_pins -of [get_cells inst_1]

get_*get_*get_* -of-of-of

Tcl

GUI

INFOWARNING

CRITICAL_WARNINGERROR

INFO

INFO: [HD-LIB 1] Done reading timing library

Tcl Tcl

Tcl

Tcl Tcl catch



2

Tcl ()

ChipScope

DRC

GUI

IP

IP

SDC

System Generator

XDC

XPS



Tcl ()

ChipScope

connect_debug_port

create_debug_core

create_debug_port

delete_debug_core

delete_debug_port

disconnect_debug_port

get_debug_cores

get_debug_ports

implement_debug_core

launch_chipscope_analyzer

read_chipscope_cdc

report_debug_core

write_chipscope_cdc

write_debug_probes

DRC

add_drc_checks

create_drc_check

create_drc_ruledeck

create_drc_violation

delete_drc_check

delete_drc_ruledeck

get_drc_checks

get_drc_ruledecks

get_drc_vios

remove_drc_checks

report_drc

reset_drc

reset_drc_check



Tcl ()

config_webtalk

infer_diff_pairs

read_checkpoint

read_chipscope_cdc

read_csv

read_edif

read_ip

read_saif

read_twx

read_vcd

read_verilog

read_vhdl

read_xdc

write_bitstream

write_bmm

write_checkpoint

write_chipscope_cdc

write_csv

write_debug_probes

write_edif

write_ibis

write_ncd

write_sdf

write_verilog

write_vhdl

write_xdc



Tcl ()

add_cells_to_pblock

create_pblock

delete_pblock

delete_rpm

get_pblocks

place_cell

place_pblocks

remove_cells_from_pblock

reset_ucf

resize_pblock

swap_locs

unplace_cell

GUI

endgroup

get_selected_objects

highlight_objects

mark_objects

redo

select_objects

start_gui

startgroup

stop_gui

undo

unhighlight_objects

unmark_objects

unselect_objects



Tcl ()

close_hw_target

connect_hw_server

current_hw_device

current_hw_ila

current_hw_ila_data

current_hw_server

current_hw_target

disconnect_hw_server

display_hw_ila_data

get_hw_devices

get_hw_ila_data

get_hw_ilas

get_hw_probes

get_hw_servers

get_hw_targets

open_hw_target

program_hw_devices

read_hw_ila_data

refresh_hw_device

refresh_hw_server

refresh_hw_target

reset_hw_ila

run_hw_ila

upload_hw_ila_data

wait_on_hw_ila

write_hw_ila_data



Tcl ()

IP

convert_ip

copy_ip

create_ip

generate_target

get_ipdefs

get_ips

import_ip

open_example_project

read_ip

reset_target

update_ip_catalog

upgrade_ip

validate_ip

IP

assign_bd_address

connect_bd_intf_net

connect_bd_net

copy_bd_objs

create_bd_addr_seg

create_bd_cell

create_bd_design

create_bd_intf_net

create_bd_intf_pin

create_bd_intf_port

create_bd_net

create_bd_pin

create_bd_port

current_bd_design

current_bd_instance

delete_bd_design

delete_bd_objs

disconnect_bd_intf_net

disconnect_bd_net



Tcl ()

find_bd_objs

generate_target

get_bd_addr_segs

get_bd_addr_spaces

get_bd_cells

get_bd_designs

get_bd_intf_nets

get_bd_intf_pins

get_bd_intf_ports

get_bd_nets

get_bd_pins

get_bd_ports

group_bd_cells

move_bd_cells

open_bd_design

package_bd_design

regenerate_bd_layout

save_bd_design

ungroup_bd_cells

write_bd_tcl

connect_net

create_cell

create_net

create_pin

disconnect_net

remove_cell

remove_net

remove_pin

rename_ref

resize_net_bus

resize_pin_bus

add_drc_checks



Tcl ()

create_drc_check

create_drc_ruledeck

delete_drc_check

delete_drc_ruledeck

filter

get_bel_pins

get_bels

get_boards

get_cells

get_clock_regions

get_clocks

get_debug_cores

get_debug_ports

get_delays

get_designs

get_drc_checks

get_drc_ruledecks

get_drc_vios

get_files

get_filesets

get_generated_clocks

get_hw_devices

get_hw_ila_data

get_hw_ilas

get_hw_probes

get_hw_servers

get_hw_targets

get_interfaces

get_io_standards

get_iobanks

get_ipdefs

get_ips

get_lib_cells

get_lib_pins

get_libs

get_nets

get_nodes

get_package_pins



Tcl ()

get_parts

get_path_groups

get_pblocks

get_pins

get_pips

get_ports

get_projects

get_property

get_runs

get_selected_objects

get_site_pins

get_site_pips

get_sites

get_tiles

get_timing_arcs

get_timing_paths

get_wires

list_property

list_property_value

remove_drc_checks

report_property

reset_drc_check

reset_property

set_property

create_interface

create_port

delete_interface

make_diff_pair_ports

place_ports

remove_port

resize_port_bus

set_package_pin_val

split_diff_pair_ports



Tcl ()

delete_power_results

power_opt_design

read_saif

read_vcd

report_power

report_power_opt

reset_default_switching_activity

reset_operating_conditions

reset_switching_activity

set_default_switching_activity

set_operating_conditions

set_power_opt

set_switching_activity

add_files

archive_project

close_design

close_project

copy_ip

create_fileset

create_project

create_run

current_fileset

current_project

current_run

delete_fileset

delete_run

find_top

generate_target

get_boards

get_files

get_filesets

get_ips



Tcl ()

get_projects

get_runs

help

import_files

import_ip

import_synplify

import_xise

import_xst

launch_runs

list_targets

make_wrapper

open_example_project

open_io_design

open_project

open_run

refresh_design

reimport_files

remove_files

reorder_files

report_compile_order

reset_project

reset_run

reset_target

save_design

save_design_as

save_project_as

set_speed_grade

update_compile_order

update_design

update_files

wait_on_run



Tcl ()

create_property

filter

get_param

get_property

list_param

list_property

list_property_value

report_param

report_property

reset_param

reset_property

set_param

set_property

check_timing


create_slack_histogram

delete_clock_networks_results

delete_timing_results

delete_utilization_results

get_msg_count

get_msg_limit

report_carry_chains

report_clock_interaction

report_clock_networks

report_clock_utilization

report_clocks

report_config_timing

report_control_sets

report_datasheet

report_debug_core

report_default_switching_activity

report_disable_timing



Tcl ()

report_drc

report_environment

report_high_fanout_nets

report_io

report_operating_conditions

report_param

report_phys_opt

report_power

report_property

report_pulse_width

report_route_status

report_ssn

report_sso

report_switching_activity

report_timing

report_timing_summary

report_transformed_primitives

report_utilization

reset_drc

reset_msg_count

reset_msg_limit

reset_msg_severity

reset_ssn

reset_sso

reset_timing

set_msg_limit

set_msg_severity

version

SDC

all_clocks

all_fanin

all_fanout

all_inputs

all_outputs

all_registers

create_clock



Tcl ()

create_generated_clock

current_design

current_instance

get_cells

get_clocks

get_hierarchy_separator

get_nets

get_pins

get_ports

get_timing_arcs

get_timing_paths

group_path

report_operating_conditions

reset_operating_conditions

set_case_analysis

set_clock_groups

set_clock_latency

set_clock_sense

set_clock_uncertainty

set_data_check

set_disable_timing

set_false_path

set_hierarchy_separator

set_input_delay

set_load

set_logic_dc

set_logic_one

set_logic_unconnected

set_logic_zero

set_max_delay

set_max_time_borrow

set_min_delay

set_multicycle_path


set_output_delay

set_propagated_clock

set_units



Tcl ()

add_bp

add_condition

add_files

add_force

checkpoint_vcd

close_saif

close_sim

close_vcd

compile_simlib

create_fileset

current_scope

current_sim

current_time

data2mem

delete_fileset

describe

flush_vcd

get_objects

get_scopes

get_value

import_files

launch_modelsim

launch_xsim

limit_vcd

log_saif

log_vcd

log_wave

ltrace

open_saif

open_vcd

open_wave_database

ptrace

read_saif

read_vcd

remove_bps



Tcl ()

remove_conditions

remove_files

remove_forces

report_bps

report_conditions

report_objects

report_scopes

report_simlib_info

report_values

reset_simulation

restart

run

set_value

start_vcd

step

stop

stop_vcd

write_sdf

write_verilog

write_vhdl

xsim

System Generator

create_sysgen

make_wrapper



Tcl ()

check_timing

config_timing_analysis

config_timing_corners

delete_timing_results

get_timing_arcs

get_timing_paths

report_config_timing

report_disable_timing

report_timing

report_timing_summary

reset_timing

set_delay_model

set_disable_timing

update_timing

launch_chipscope_analyzer

launch_impact

launch_modelsim

launch_sdk

launch_xsim

link_design

list_features

load_features

opt_design

phys_opt_design

place_design

route_design

synth_design



Tcl ()

add_wave

add_wave_divider

add_wave_group

add_wave_marker

add_wave_virtual_bus

close_wave_config

create_wave_config

current_wave_config

get_wave_configs

open_wave_config

save_wave_config

XDC

add_cells_to_pblock

all_clocks

all_cpus

all_dsps

all_fanin

all_fanout

all_ffs

all_hsios

all_inputs

all_latches

all_outputs

all_rams

all_registers

create_clock


create_pblock

current_design

current_instance

delete_pblock

filter

get_cells



Tcl ()

get_clocks

get_generated_clocks

get_hierarchy_separator

get_iobanks

get_nets

get_package_pins

get_path_groups

get_pblocks

get_pins

get_ports

get_sites

get_timing_arcs

group_path


resize_pblock

set_case_analysis

set_clock_groups

set_clock_latency

set_clock_sense

set_clock_uncertainty

set_data_check

set_default_switching_activity

set_disable_timing

set_external_delay

set_false_path


set_input_delay

set_input_jitter

set_load

set_logic_dc

set_logic_one

set_logic_unconnected

set_logic_zero

set_max_delay

set_max_time_borrow

set_min_delay

set_multicycle_path




Tcl ()

set_output_delay

set_package_pin_val

set_power_opt


set_property

set_switching_activity

set_system_jitter

set_units

XPS

create_xps

export_hardware

generate_target

get_boards

launch_sdk

list_targets

make_wrapper

reset_target



3

Tcl () SDC Tcl

add_bp

(file_name) (line_number)

add_bp [-quiet] [-verbose] file_name line_number

[-quiet-quiet-quiet]

[-verbose-verbose-verbose]

file_name

line_number



Tcl ()

add_cells_to_pblock

Pblock

add_cells_to_pblock [-add_primitives] [-clear_locs] [-quiet] [-verbose] pblock[cells ...]

[-add_primitives-add_primitives-add_primitives] Pblock

[-clear_locs-clear_locs-clear_locs]



pblock Pblock

[cells]

XDC

Pblock Pblock place_pblocksplace_pblocksplace_pblocks

Pblock FPGA Pblock resize_pblocksresize_pblocksresize_pblocks

Pblock

Pblock remove_cells_from_pblockremove_cells_from_pblockremove_cells_from_pblock

-add_primitives-add_primitives-add_primitives : Pblock

Pblock

-clear_locs-clear_locs-clear_locs :

Pblock LOC

Pblock



Tcl ()

-quiet-quiet-quiet () :

TCL_OK

-verbose-verbose-verbose () :

: set_msg_limitset_msg_limitset_msg_limit

pblock : Pblock

cells : Pblock 1

pb_cpuEngine Pblock cpuEngine

create_pblock pb_cpuEngine

add_cells_to_pblock pb_cpuEngine [get_cells cpuEngine] -add_primitives -clear_locs

get_pblocks

place_pblocks


resize_pblock



Tcl ()

add_condition

add_condition [-name arg] [-radix arg] [-quiet][-verbose] condition_expression commands

[-name-name-name] ()

[-radix-radix-radix] defaultdecbinocthexunsignedascii



condition_expression

commands



Tcl ()

add_drc_checks

DRC

add_drc_checks [-of_objects args] [-regexp] [-nocase] [-filter arg]-ruledeck arg [-quiet] [-verbose] [patterns]

DRC

[-of_objects-of_objects-of_objects] DRC DRC

[-regexp-regexp-regexp]

[-nocase-nocase-nocase] /(-regexp )

[-filter-filter-filter]

-ruledeck-ruledeck-ruledeck DRC



[patterns] DRC *

DRC

DRC

I/O FPGA

report_drcreport_drcreport_drc

create_drc_ruledeckcreate_drc_ruledeckcreate_drc_ruledeck

get_drc_ruledecksget_drc_ruledecksget_drc_ruledecks report_drc

create_drc_checkcreate_drc_checkcreate_drc_check

get_drc_ruledecksget_drc_ruledecksget_drc_ruledecks



Tcl ()

remove_drc_checksremove_drc_checksremove_drc_checks

-of_objects-of_objects-of_objects arg : DRC

-regexp-regexp-regexp () :

-filter-filter-filter

Tcl .*

http://www.tcl.tk/man/tcl8.4/TclCmd/re_syntax.htm

: Tcl regexpregexpregexp Tcl

http://www.tcl.tk/man/tcl8.4/TclCmd/regexp.htm

-nocase-nocase-nocase () : /-regexp-regexp-regexp

-filter-filter-filter args () :

report_propertyreport_propertyreport_property list_propertylist_propertylist_property

(==) (!=) (=~) (!~)

= AND (&&) OR (||)

clk

get_ports * -filter {DIRECTION == IN && NAME !~ "*clk"}

-ruledeck-ruledeck-ruledeck arg :


TCL_OK



patterns : (*)

: { } 1

project_rules

add_drc_checks -ruledeck project_rules {*DCI* *BUF*}



Tcl ()

placer+ placer_checks

placer+

create_drc_ruledecks placer+

add_drc_checks -of_objects [get_drc_ruledecks placer_checks] -ruledeck placer+

add_drc-checks -ruledeck placer+ *IO*

add_drc_checks -filter {SEVERITY == Warning} -ruledeck warn_only

create_drc_check

create_drc_ruledeck

get_drc_checks

get_drc_ruledecks

list_property

remove_drc_checks

report_drc

report_property



Tcl ()

add_files

add_files [-fileset arg] [-norecurse] [-scan_for_includes] [-quiet] [-verbose][files ...]

[-fileset-fileset-fileset]

[-norecurse-norecurse-norecurse]

[-scan_for_includes-scan_for_includes-scan_for_includes] RTL



[files] -scan_for_includes

1 1

:

read_xxxread_xxxread_xxx

Vivado Design Suite : (UG892)

import_filesimport_filesimport_files



Tcl ()

-fileset-fileset-fileset name () :

-norecurse-norecurse-norecurse () :

-scan_for_includes-scan_for_includes-scan_for_includes () : Verilog includeincludeinclude

includeincludeinclude


TCL_OK



files : 1

:

rtl.v

add_files rtl.v

rtl.v

top.ucftop.ucftop.ucf constrs_1constrs_1constrs_1 project_1

add_files -fileset constrs_1 -quiet c:/Design/top.ucf c:/Design/project_1

-quiet-quiet-quiet

-norecurse-norecurse-norecurse project_1project_1project_1

IP

add_files -norecurse C:/Data/ip/c_addsub_v11_0_0.xci

: IP import_ipimport_ipimport_ip



Tcl ()

add_files C:/Data/dvi_tpg_demo_ORG/system.xmp

: Xilinx Platform Studio (XPS) create_xpscreate_xpscreate_xps

System Generator DSP

add_files C:/Data/model1.mdl

: System Generator DSP create_sysgencreate_sysgencreate_sysgen

create_sysgen

create_xps

import_files

import_ip

read_ip

read_verilog

read_vhdl

read_xdc



Tcl ()

add_force

force

add_force [-radix arg] [-repeat_every arg] [-cancel_after arg] [-quiet][-verbose] hdl_object values ...

force


[-repeat_every-repeat_every-repeat_every]

[-cancel_after-cancel_after-cancel_after]



hdl_object force

values force {value [ time_offset] }



Tcl ()

add_wave

add_wave [-into args] [-at_wave args] [-after_wave args] [-before_wave args][-reverse] [-radix arg] [-color arg] [-name arg] [-recursive] [-r] [-regexp][-nocase] [-quiet] [-verbose] items ...

[-into-into-into] -*_row -*_wave -into -into -*_row -*_wave -into WCFG WCFG WCFG -into

[-at_wave-at_wave-at_wave] -*_row (waveObj) waveObj

[-after_wave-after_wave-after_wave] -*_row (waveObj) waveObj

[-before_wave-before_wave-before_wave] -*_row (waveObj) waveObj

[-reverse-reverse-reverse] IS_REVERSED true


[-color-color-color]

[-name-name-name] DISPLAY_NAME

[-recursive-recursive-recursive]



Tcl ()

[-r-r-r]

[-regexp-regexp-regexp]

[-nocase-nocase-nocase] / (-regexp )



items 1

1

: HDL () itemitemitem Vivado [Objects]

-into-into-into wcfgGroupVbusObj () : wcfgGroupVbusObj WCFG WCFG

WCFG

-into-into-into

-at_wave-at_wave-at_wave waveObj () : waveObj

-after_wave-after_wave-after_wave waveObj () : waveObj

-before_wave-before_wave-before_wave waveObj () : waveObj

-reverse-reverse-reverse () : IS_REVERSEDIS_REVERSEDIS_REVERSED truetruetrue

-radix-radix-radix arg () : defaultdefaultdefaultdecdecdecbinbinbinoctoctocthexhexhexunsignedunsignedunsignedasciiasciiascii

-color-color-color arg () : 6 RGB (RRGGBB)



Tcl ()

-name-name-name arg () : DISPLAY_NAMEDISPLAY_NAMEDISPLAY_NAME

-recursive-recursive-recursive ||| -r-r-r () : items

-regexp-regexp-regexp () : items Tcl .*

http://www.tcl.tk/man/tcl8.4/TclCmd/re_syntax.htm

: Tcl regexp Tcl

http://www.tcl.tk/man/tcl8.4/TclCmd/regexp.htm

-nocase-nocase-nocase () : /-regexp-regexp-regexp


TCL_OK



items : HDL

clk

add_wave clkclk

rsb_design_testbench dout_tvalid

add_wave dout_tvalid/rsb_design_testbench/dout_tvalid

add_wave_divider

add_wave_group

add_wave_marker




Tcl ()

add_wave_divider

add_wave_divider [-into args] [-at_wave args] [-after_wave args][-before_wave args] [-color arg] [-quiet] [-verbose] [name]

[-into-into-into] -*_row -*_wave -into -into -*_row -*_wave -into wcfgGroupVbusObj WCFG WCFG WCFG -into




[-color-color-color] default



[name] new_divider



Tcl ()

:


WCFG -into-into-into






TCL_OK



name () : new_divider

CLK Div1

add_wave_divider -after_wave CLK Div1

add_wave

add_wave_group

add_wave_marker




Tcl ()

add_wave_group

add_wave_group [-into args] [-at_wave args] [-after_wave args][-before_wave args] [-quiet] [-verbose] [name]







[name] new_group



Tcl ()

:


WCFG

-into-into-into





TCL_OK



name () : new_group

clk

add_wave_group clkgroup10

add_wave

add_wave_divider

add_wave_marker




Tcl ()

add_wave_marker

add_wave_marker [-into arg] [-name arg] [-quiet] [-verbose] [time] [unit]

[-into-into-into]

[-name-name-name]



[time] 0

[unit]

:

-into-into-into wcfg : -into-into-into

-name-name-name arg () : new_divider

time : 0

unit : sssmsmsmsusususnsnsns pspsps



Tcl ()


TCL_OK



500ns

add_wave_marker 500 ns

add_wave

add_wave_divider

add_wave_group




Tcl ()


add_wave_virtual_bus [-into args] [-at_wave args] [-after_wave args][-before_wave args] [-reverse] [-radix arg] [-color arg] [-quiet] [-verbose][name]





[-reverse-reverse-reverse] IS_REVERSED true


[-color-color-color] default



[name]



Tcl ()

vb###

: namenamename

-into-into-into wcfgGroupVbusObj : wcfgGroupVbusObj WCFG WCFG

WCFG -into-into-into

-at_wave-at_wave-at_wave waveObj : waveObj

-after_wave-after_wave-after_wave waveObj : waveObj

-before_wave-before_wave-before_wave waveObj : waveObj

-reverse-reverse-reverse () : IS_REVERSEDIS_REVERSEDIS_REVERSED truetruetrue

-radix-radix-radix arg () : defaultdefaultdefault

decdecdecbinbinbinoctoctocthexhexhexunsignedunsignedunsignedasciiasciiascii


-name-name-name customName : DISPLAY_NAMEDISPLAY_NAMEDISPLAY_NAME


TCL_OK



dout_tvaliddout_tvaliddout_tvalid

add_wave_virtual_bus dout_tvalidvbus200



Tcl ()

add_wave_divider

add_wave_group

add_wave_marker

add_wave



Tcl ()

all_clocks

all_clocks [-quiet] [-verbose]



SDCXDC

get_clocksget_clocksget_clocks

create_clockcreate_clockcreate_clock create_generated_clockcreate_generated_clockcreate_generated_clock


TCL_OK



CPU

% all_clocks

cpuClk wbClk usbClk phy_clk_pad_0_i phy_clk_pad_1_i fftClk



Tcl ()

set_propagated_clockset_propagated_clockset_propagated_clock (all_clocksall_clocksall_clocks)

% set_propagated_clock [all_clocks]

create_clock


get_clocks




Tcl ()

all_cpus

CPU

all_cpus [-quiet] [-verbose]

CPU



XDC

CPU CPU

: CPU


TCL_OK



CPU

all_cpus

set_false_path -from [all_cpus] -to [all_registers]



Tcl ()

all_dsps

all_hsios

all_registers

set_false_path



Tcl ()

all_dsps

DSP

all_dsps [-quiet] [-verbose]

DSP



XDC

DSP


TCL_OK



DSP

all_dsps

set_false_path -from [all_dsps] -to [all_registers]



Tcl ()

all_cpus

all_hsios

all_registers

set_false_path



Tcl ()

all_fanin

all_fanin [-startpoints_only] [-flat] [-only_cells] [-levels arg][-pin_levels arg] [-trace_arcs arg] [-quiet] [-verbose] to

[-startpoints_only-startpoints_only-startpoints_only]

[-flat-flat-flat]

[-only_cells-only_cells-only_cells]

[-levels-levels-levels] 0 0

[-pin_levels-pin_levels-pin_levels] 0 0

[-trace_arcs-trace_arcs-trace_arcs] timingenabledall



to

SDCXDC

-startpoints_only-startpoints_only-startpoints_only () :

-flat-flat-flat () :

-only_cells-only_cells-only_cells () :

-levels-levels-levels value () : 0



Tcl ()

-pin_levels-pin_levels-pin_levels value () : 0

-trace_arcs-trace_arcs-trace_arcs value : timingenabledall


TCL_OK



to () :

DAT

all_fanin DAT

MMCM sysClk

all_fanin -to [get_pins fftEngine/control_reg_reg[17]/C] -startpoints_only \

-flat sysClk

all_fanout



Tcl ()

all_fanout

all_fanout [-endpoints_only] [-flat] [-only_cells] [-levels arg][-pin_levels arg] [-trace_arcs arg] [-quiet] [-verbose] from

[-endpoints_only-endpoints_only-endpoints_only]

[-flat-flat-flat]

[-only_cells-only_cells-only_cells]

[-levels-levels-levels] 0 0

[-pin_levels-pin_levels-pin_levels] 0 0

[-trace_arcs-trace_arcs-trace_arcs] timingenabledall



from

SDCXDC

-endpoints_only-endpoints_only-endpoints_only () :

-flat-flat-flat () :

-only_cells-only_cells-only_cells () :

-levels-levels-levels value () : 0



Tcl ()

-pin_levels-pin_levels-pin_levels value () : 0

-trace_arcs-trace_arcs-trace_arcs value : timingenabledall


TCL_OK



from () :

DAT

all_fanout DAT

all_fanin



Tcl ()

all_ffs

all_ffs [-quiet] [-verbose]



XDC


TCL_OK



report_property [lindex [all_ffs] 2 ]

all_registers

report_property



Tcl ()

all_hsios

HSIO

all_hsios [-quiet] [-verbose]

HSIO



XDC

I/O (HSIO) HSIO


TCL_OK



HSIO

all_hsios

set_false_path -from [all_hsios] -to [all_registers]



Tcl ()

all_cpus

all_dsps

all_registers

set_false_path



Tcl ()

all_inputs

all_inputs [-quiet] [-verbose]



SDCXDC


TCL_OK



all_inputs

set_input_delay 5 -clock REFCLK [all_inputs]



Tcl ()

all_outputs

set_input_delay



Tcl ()

all_latches

all_latches [-quiet] [-verbose]



XDC


TCL_OK



all_latches

set_false_path -from [all_mults] -to [all_latches]



Tcl ()

all_ffs

all_registers

set_false_path



Tcl ()

all_outputs

all_outputs [-quiet] [-verbose]



SDCXDC


TCL_OK



all_outputs

set_output_delay 5 -clock REFCLK [all_outputs]



Tcl ()

all_inputs

set_output_delay



Tcl ()

all_rams

RAM

all_rams [-quiet] [-verbose]

RAM



XDC

RAM RAM


TCL_OK



RAM

all_rams



Tcl ()

all_cpus

all_dsps

all_hsios

all_registers



Tcl ()

all_registers

all_registers [-clock args] [-rise_clock args] [-fall_clock args] [-cells][-data_pins] [-clock_pins] [-async_pins] [-output_pins] [-level_sensitive][-edge_triggered] [-no_hierarchy] [-quiet] [-verbose]

[-clock-clock-clock]

[-rise_clock-rise_clock-rise_clock]

[-fall_clock-fall_clock-fall_clock]

[-cells-cells-cells] ()

[-data_pins-data_pins-data_pins]

[-clock_pins-clock_pins-clock_pins]

[-async_pins-async_pins-async_pins] /

[-output_pins-output_pins-output_pins]

[-level_sensitive-level_sensitive-level_sensitive]

[-edge_triggered-edge_triggered-edge_triggered]

[-no_hierarchy-no_hierarchy-no_hierarchy]



SDCXDC



Tcl ()

-cells-cells-cells () :

-clock-clock-clock args () :

-rise_clock-rise_clock-rise_clock args () :

-fall_clock-fall_clock-fall_clock args () :

: -clock-clock-clock-rise_clock-rise_clock-rise_clock -fall_clock-fall_clock-fall_clock

-level_sensitive-level_sensitive-level_sensitive () :

-edge_triggered-edge_triggered-edge_triggered () :

-data_pins-data_pins-data_pins () :

-clock_pins-clock_pins-clock_pins () :

-async_pins-async_pins-async_pins () :

-output_pins-output_pins-output_pins () :

: -*_pins-*_pins-*_pins 1 -data_pins-data_pins-data_pins-clock_pins-clock_pins-clock_pins-async_pins-async_pins-async_pins-output_pins-output_pins-output_pins


TCL_OK



all_registers -fall_clock [all_clocks]

set_min_delay 2.0 -to [all_registers -clock CCLK -data_pins]

all_clocks

set_msg_limit

set_min_delay



Tcl ()

archive_project

archive_project [-force] [-exclude_run_results] [-quiet] [-verbose] [file]

True

[-force-force-force]

[-exclude_run_results-exclude_run_results-exclude_run_results] run



[file]

run ZIP

-force-force-force () : ZIP ZIP -force-force-force

-exclude_run_results-exclude_run_results-exclude_run_results : run


TCL_OK





Tcl ()

file () : archive_projectarchive_projectarchive_project ZIP file ZIP

archive_project

: project_name.zip

project_3 proj3.zip

current_project project_3

archive_project -force -exclude_run_results proj3.zip

: -force-force-force proj3.zip -exclude_run_results-exclude_run_results-exclude_run_results run run

run

current_project



Tcl ()

assign_bd_address

IP

assign_bd_address [-target_address_space arg] [-quiet] [-verbose][objects ...]

""

[-target_address_space-target_address_space-target_address_space]



[objects]

IP



Tcl ()

check_timing

check_timing [-file arg] [-name arg] [-override_defaults args][-include args] [-exclude args] [-quiet] [-verbose]

[-file-file-file]

[-name-name-name] GUI

[-override_defaults-override_defaults-override_defaults]

[-include-include-include]

[-exclude-exclude-exclude]



report_timingreport_timingreport_timing

check_timingcheck_timingcheck_timing

-verbose-verbose-verbose

: Tcl STD GUI



Tcl ()

generated_clocksgenerated_clocksgenerated_clocks :

2

loopsloopsloops :

multiple_clockmultiple_clockmultiple_clock :

set_case_analysisset_case_analysisset_case_analysis 1

no_clockno_clockno_clock :

no_input_delayno_input_delayno_input_delay : set_input_delayset_input_delayset_input_delay

no_output_delayno_output_delayno_output_delay :

set_output_delayset_output_delayset_output_delay

partial_input_delaypartial_input_delaypartial_input_delay :

set_input_delayset_input_delayset_input_delay -max-max-max set_input_delayset_input_delayset_input_delay -min-min-min

set_input_delayset_input_delayset_input_delay -min-min-min -max-max-max

:

partial_output_delaypartial_output_delaypartial_output_delay :

set_output_delayset_output_delayset_output_delay -max-max-max set_output_delayset_output_delayset_output_delay -min-min-min

set_output_delayset_output_delayset_output_delay -min-min-min -max-max-max

:

unconstrained_endpointsunconstrained_endpointsunconstrained_endpoints :

create_clockcreate_clockcreate_clock

set_output_delayset_output_delayset_output_delay set_max_delayset_max_delayset_max_delay

unexpandable_clocksunexpandable_clocksunexpandable_clocks : 1

1000



Tcl ()

-file-file-file arg () : Tcl

:

-name-name-name arg () : GUI [Timing]

-override_defaults-override_defaults-override_defaults {args} () :

-include-include-include args () :

-exclude-exclude-exclude args () : check_timingcheck_timingcheck_timing


TCL_OK



check_timingcheck_timingcheck_timing

check_timing -exclude {loops generated_clocks}

multiple_clocks -verbose-verbose-verbose

get_clocksget_clocksget_clocks

check_timing -verbose -override_defaults {multiple_clock}

Checking multiple_clock.

There are 2 register/latch pins with multiple clocks.

procEngine/mode_du/set_reg[0]/C

provEngine/mode_du/set_reg[1]/C

get_clocks -of_objects [get_pin procEngine/mode_du/set_reg[0]/C]

sysClk coreClk

create_clock

get_clocks

report_timing

set_case_analysis

set_input_delay

set_max_delay

set_output_delay



Tcl ()

checkpoint_vcd

$dumpall Verilog

checkpoint_vcd [-quiet] [-verbose]



HDL VCD (Value Change Dump)

Tcl Verilog $dumpall$dumpall$dumpall

VCD HDL ASCII VCD

VCD

VCD Verilog IEEE (IEEE Std 1364-2005)

checkpoint_vcdcheckpoint_vcdcheckpoint_vcd open_vcdopen_vcdopen_vcd log_vcdlog_vcdlog_vcd

checkpoint_vcdcheckpoint_vcdcheckpoint_vcd


TCL_OK



VCDObject : VCD VCDObject VCD



Tcl ()

HDL VCD

checkpoint_vcd foo.vcd

flush_vcd

log_vcd

open_vcd



Tcl ()

close_design

close_design [-quiet] [-verbose]



close_designclose_designclose_design save_designsave_designsave_design save_design_assave_design_assave_design_as


TCL_OK



close_design

: close_designclose_designclose_design current_designcurrent_designcurrent_design



Tcl ()

current_design rtl_1

close_design

rtl_1rtl_1rtl_1 close_designclose_designclose_design

current_design

save_design

save_design_as



Tcl ()

close_hw_target

close_hw_target [-quiet] [-verbose] [hw_target]



[hw_target]



Tcl ()

close_project

close_project [-delete] [-quiet] [-verbose]

[-delete-delete-delete]



-delete-delete-delete :

:


TCL_OK



close_project

close_projectclose_projectclose_project current_projectcurrent_projectcurrent_project



Tcl ()

project_1

current_project project_1

close_project -delete

: -delete-delete-delete

current_project



Tcl ()

close_saif

close_saif [-quiet] [-verbose]





Tcl ()

close_sim

close_sim [-quiet] [-verbose]



Vivado

:


TCL_OK



close_sim

current_sim

launch_xsim



Tcl ()

close_vcd

VCD

close_vcd [-quiet] [-verbose]



VCD (Value Change Dump)


TCL_OK



VCDObject () : VCD VCDObject VCD

VCD

close_vcd

open_vcd



Tcl ()

close_wave_config

close_wave_config [-force] [-quiet] [-verbose] [wcfgobj]




[wcfgobj] NULL



Tcl ()

compile_simlib

compile_simlib [-cfg_file] [-directory arg] [-exclude_sublib][-exclude_superseded] [-family arg] [-force] [-language arg] [-library arg][-precompiled_directory arg] [-simulator arg] [-simulator_exec_path arg][-source_library_path arg] [-32bit] [-quiet] [-verbose]

[-cfg_file-cfg_file-cfg_file] compile_simlib.cfg

[-directory-directory-directory] .

[-exclude_sublib-exclude_sublib-exclude_sublib] EDK .pao (EDK )

[-exclude_superseded-exclude_superseded-exclude_superseded] EDK (EDK )

[-family-family-family] all


[-language-language-language] all

[-library-library-library] all

[-precompiled_directory-precompiled_directory-precompiled_directory] compile_simlib

[-simulator-simulator-simulator]

[-simulator_exec_path-simulator_exec_path-simulator_exec_path]

[-source_library_path-source_library_path-source_library_path] XILINX_PLANAHEAD (Vivado ) XILINX_EDK(EDK )

[-32bit-32bit-32bit] 32





Tcl ()

HDL Vivado ISim

compile_simlibcompile_simlibcompile_simlib

-cfg_file-cfg_file-cfg_file () : compxlib.cfg

-directory-directory-directory arg () :

:

-exclude_sublib-exclude_sublib-exclude_sublib () : EDK .pao EDK

(UG111)

-exclude_superseded-exclude_superseded-exclude_superseded () : EDK

EDK

(UG111)

-family-family-family arg () :

virtex7 (Virtex-7)

virtex7l (Virtex-7 )

kintex7 (Kintex-7)

kintex7l (Kintex-7 )

artix7 (Artix-7)

artix7l (Atix-7 )

zynq (Zynq-7000 EPP)

-force-force-force () :

-language-language-language [[[ verilogverilogverilog ||| vhdlvhdlvhdl ||| allallall ]]] () :

-simulator-simulator-simulator

Verilog VHDL



Tcl ()

-library-library-library arg () :

all

unisim

simprim

xilinxcorelib

edk

-lib

.. -library unisim -library simprim ..

: EDK (-lib edk)EDK UNISIM SIMPRIM

ISE

-precompiled_directory-precompiled_directory-precompiled_directory arg () :

-simulator-simulator-simulator arg () :

modelsim

questasim

ies (Linux )

vcs_mx (Linux )

-simulator_exec_path-simulator_exec_path-simulator_exec_path arg () : $PATH %PATH% $PATH

%PATH%

-source_library_path-source_library_path-source_library_path arg () : ($XILINX$XILINX_PLANAHEAD $XILINX_EDK)

:

-32bit-32bit-32bit () : 64 32


TCL_OK



Virtex-7 ModelSim (VHDL) UNISIM

SIMPRIM

compile_simlib -simulator modelsim -family virtex7 -library unisim \

-library simprim -language vhdl



Tcl ()

launch_modelsim



Tcl ()


config_timing_analysis [-disable_paths_between_unrelated_ucf_clocks arg][-enable_input_delay_default_clock arg] [-enable_preset_clear_arcs arg][-quiet] [-verbose]

[-disable_paths_between-disable_paths_between-disable_paths_between _unrelated_ucf_clocks_unrelated_ucf_clocks_unrelated_ucf_clocks] UCF truefalse SDC

[-enable_input_delay_default-enable_input_delay_default-enable_input_delay_default _clock_clock_clock] SDC truefalse UCF

[-enable_preset_clear_arcs-enable_preset_clear_arcs-enable_preset_clear_arcs] truefalse



:

-disable_paths_between_unrelated_ucf_clocks-disable_paths_between_unrelated_ucf_clocks-disable_paths_between_unrelated_ucf_clocks [[[ truetruetrue ||| falsefalsefalse ]]] () : UCF

true false

false

: UCF



Tcl ()

-enable_input_delay_default_clock-enable_input_delay_default_clock-enable_input_delay_default_clock [[[ truetruetrue ||| falsefalsefalse ]]] () :

true false false

: SDC

-enable_preset_clear_arcs-enable_preset_clear_arcs-enable_preset_clear_arcs [[[ truetruetrue ||| falsefalsefalse ]]] () :

true false false


TCL_OK



UCF

config_timing_analysis -disable_paths_between_unrelated_ucf_clocks true


report_timing



Tcl ()


/

config_timing_corners [-corner arg] [-delay_type arg] [-setup] [-hold][-quiet] [-verbose]

[-corner-corner-corner] SlowFast

[-delay_type-delay_type-delay_type] nonemaxminmin_max

[-setup-setup-setup] (-delay_type max )

[-hold-hold-hold] (-delay_type min )



/

:

-corner-corner-corner [[[ SlowSlowSlow ||| FastFastFast ]]] () : Slow

Fast

: /

-delay_type-delay_type-delay_type value () : maxmin min_max



Tcl ()

-setup-setup-setup () : -delay_type-delay_type-delay_type maxmaxmax

-hold-hold-hold () : -delay_type-delay_type-delay_type minminmin

: -setup-setup-setup -hold-hold-hold -delay_type-delay_type-delay_type min_maxmin_maxmin_max


TCL_OK



config_timing_corners -corner Slow -setup -hold

config_timing_corners -corner Slow -delay_type min_max

:

config_timing_corners -corner Fast -delay_type min


report_timing



Tcl ()

config_webtalk

IP WebTalk /

config_webtalk [-info] [-user arg] [-install arg] [-quiet] [-verbose]

[-info-info-info] WebTalk

[-user-user-user] WebTalk / on off

[-install-install-install] WebTalk / on off off -user WebTalk



WebTalk FPGA

IP

WebTalk

IP WebTalk /

WebPACK WebTalk

WebTalk WebPACK

WebPACK



Tcl ()

: WebPACK WebPACK WebPACK 34746

-info : WebTalk WebTalk

WebTalk

-user arg : WebTalk

-install arg : WebTalk


TCL_OK



WebTalk

config_webtalk -info

INFO: [Coretcl-120] Webtalk has been disabled by the current user.

INFO: [Coretcl-123] Webtalk has been enabled for the current installation.

INFO: [Coretcl-110] This combination of user/install settings means that WebTalk is currently disabled.

WebTalk

config_webtalk -user on



Tcl ()

connect_bd_intf_net

connect_bd_intf_net [-intf_net arg] [-quiet] [-verbose] object1 object2

0

[-intf_net-intf_net-intf_net] 1



object1

object2

IP



Tcl ()

connect_bd_net

connect_bd_net [-net arg] [-quiet] [-verbose] objects ...

0

[-net-net-net] 1



objects

IP

(bd)

get_bd_portsget_bd_portsget_bd_ports get_bd_pinsget_bd_pinsget_bd_pins

-net-net-net arg () : 1

:


TCL_OK



objects :



Tcl ()

connect_bd_net [get_bd_ports /clk] [get_bd_pins /mycell/mysubcell/clk]

: /clk /mycell/mysubcell/clk -net-net-net

get_bd_pins

get_bd_ports



Tcl ()

connect_debug_port

connect_debug_port [-channel_start_index arg] [-quiet][-verbose] port nets ...

[-channel_start_index-channel_start_index-channel_start_index]



port

nets

ChipScope

ChipScope

create_debug_port

set_propertyset_propertyset_property port_widthport_widthport_width

disconnect_debug_portdisconnect_debug_portdisconnect_debug_port

ChipScope

CORE Generator implement_debug_coreimplement_debug_coreimplement_debug_core



Tcl ()

-channel_start_index-channel_start_index-channel_start_index arg : 0

:

port : core_name/port_name

nets :


TCL_OK



myCore TRIG port_width

3 ( 2)

create_debug_port myCore TRIG

set_property port_width 8 [get_debug_ports myCore/TRIG0]

connect_debug_port myCore/TRIG0 [get_nets [list m0_ack_o m0_cyc_i m0_err_o \

m0_rty_o m0_stb_i m0_we_i ]] -channel_start_index 2

:

create_debug_port


get_debug_ports

get_nets


set_property



Tcl ()

connect_hw_server

connect_hw_server [-host arg] [-port arg] [-password arg] [-launch arg][-quiet] [-verbose]

[-host-host-host] localhost

[-port-port-port] 50001

[-password-password-password]

[-launch-launch-launch] No





Tcl ()

connect_net

connect_net [-hier] [-basename arg] -net arg -objects args [-quiet] [-verbose]

[-hier-hier-hier] (-basename )

[-basename-basename-basename] / (-hier ) (-net )

-net-net-net

-objects-objects-objects



1

write_checkpointwrite_checkpointwrite_checkpoint

write_*write_*write_* VerilogVHDL

EDIF

: RTL

-net-net-net arg :

: create_netcreate_netcreate_net -bus_from-bus_from-bus_from -bus_to-bus_to-bus_to

connect_netconnect_netconnect_net



Tcl ()

-objects-objects-objects args : 1


TCL_OK



myDMA myEnable

create_port -direction IN enableIncreate_pin -direction IN myDMA/encreate_net myEnableconnect_net -net myEnable -objects {enableIn myDMA/en}

32 loop 1

create_port -from 0 -to 31 -direction IN dataINcreate_pin -bus_from 0 -bus_to 31 -direction IN myDMA/datacreate_net -bus_from 0 -bus_to 31 dataBusfor {set x 0} {$x

Tcl ()

convert_ip

IP IP

convert_ip [-quiet] [-verbose] objects ...



objects IP

IP

IP Vivado IP

IP IP

Vivado IP

IP IP IP blk_mem_gen

v7.1 IP

:


TCL_OK



objects : IP 1



Tcl ()

IP

convert_ip [get_ips]

: IP

create_ip

import_ip

upgrade_ip

validate_ip



Tcl ()

copy_bd_objs

copy_bd_objs [-prefix arg] [-to_design arg] [-quiet] [-verbose][parent_cell] objects ...

0 ""

[-prefix-prefix-prefix]

[-to_design-to_design-to_design]



[parent_cell]

objects

IP



Tcl ()

copy_ip

IP

copy_ip -name arg [-quiet] [-verbose] objects ...

IP

-name-name-name IP



objects IP

IP



Tcl ()

create_bd_addr_seg

create_bd_addr_seg -range arg -offset arg [-quiet] [-verbose][parent_addr_space ] [slave_segment ] name

""

-range-range-range

-offset-offset-offset



[parent_addr_space]

[slave_segment]

name

IP



Tcl ()

create_bd_cell

create_bd_cell [-vlnv arg] [-type arg] [-quiet] [-verbose] name

""

[-vlnv-vlnv-vlnv] VLNV

[-type-type-type] IP



name

IP



Tcl ()

create_bd_design

create_bd_design [-quiet] [-verbose] name

""



name

IP



Tcl ()

create_bd_intf_net

create_bd_intf_net [-quiet] [-verbose] name

""



name intf_net

IP



Tcl ()

create_bd_intf_pin

create_bd_intf_pin -vlnv arg -mode arg [-quiet] [-verbose] name

""

-vlnv-vlnv-vlnv VLNV

-mode-mode-mode



name

IP



Tcl ()

create_bd_intf_port

create_bd_intf_port -vlnv arg -mode arg [-quiet] [-verbose] name

""

-vlnv-vlnv-vlnv VLNV

-mode-mode-mode



name

IP



Tcl ()

create_bd_net

create_bd_net [-quiet] [-verbose] name

""



name

IP



Tcl ()

create_bd_pin

create_bd_pin [-from arg] [-to arg] -dir arg [-type arg] [-intf arg] [-quiet][-verbose] name

""

[-from-from-from]

[-to-to-to]

-dir-dir-dir

[-type-type-type]

[-intf-intf-intf]



name

IP



Tcl ()

create_bd_port

create_bd_port [-from arg] [-to arg] -dir arg [-type arg] [-intf arg][-quiet] [-verbose] name

""

[-from-from-from]

[-to-to-to]

-dir-dir-dir

[-type-type-type]

[-intf-intf-intf]



name

IP



Tcl ()

create_cell

create_cell -reference arg [-black_box] [-quiet] [-verbose] cells ...

-reference-reference-reference

[-black_box-black_box-black_box]



cells

write_checkpointwrite_checkpointwrite_checkpoint

write_*write_*write_* VerilogVHDL

EDIF

: RTL

-reference-reference-reference arg :



Tcl ()

-black_box-black_box-black_box () :


TCL_OK



cells :

get_hierarchy_separatorget_hierarchy_separatorget_hierarchy_separator

or1200_cpu 3

create_cell -reference or1200_cpu myCell1 myCell2 myCell3

set_hierarchy_separator |create_cell -reference dmaBlock -black_box usbEngine0|myDMA

: -black_box-black_box-black_box -reference-reference-reference

remove_cell


write_checkpoint

write_edif

write_verilog

write_vhdl



Tcl ()

create_clock

create_clock -period arg [-name arg] [-waveform args] [-add] [-quiet][-verbose] [objects]

-period-period-period 0

[-name-name-name]

[-waveform-waveform-waveform]

[-add-add-add]



[objects]

SDCXDC

()

create_generated_clockcreate_generated_clockcreate_generated_clock

:



Tcl ()

-period-period-period arg : 0 10.0

: set_unitsset_unitsset_units (ns)

-name-name-name arg () : (objects) objects -name-name-name

-waveform-waveform-waveform arg1 arg2 ... () : 1

2

: 0

1/2

-add-add-add () :

-name-name-name


TCL_OK



objects : -add-add-add

objects

:

bftClk

create_clock -name bftClk -period 5.000 [get_ports bftClk]

: get_portsget_portsget_ports



Tcl ()

all_clocks


get_clocks

set_input_delay

set_output_delay


set_units



Tcl ()

create_debug_core

ChipScope

create_debug_core [-quiet] [-verbose] name type



name

type

ChipScope

ChipScope

:

CLK (TRIG) CLK

1

create_debug_port

connect_debug_port

name : ChipScope

type : ChipScope chipscope_ila_v1 ILA

ChipScope Pro

(UG029)

: ILA 1 ILA ICON

1 ICON



Tcl ()


TCL_OK



ChipScope

open_netlist_design -name netlist_1

create_debug_core myCore chipscope_ila_v1

: chipscope_ila_v1

myCore

report_property [create_debug_core myCore chipscope_ila_v1]

set_propertyset_propertyset_property

set_property enable_storage_qualification false [get_debug_cores myCore]

connect_debug_port

create_debug_port

delete_debug_core

get_debug_cores


read_chipscope_cdc

report_debug_core

report_property

set_property

write_chipscope_cdc



Tcl ()

create_debug_port

ChipScope

create_debug_port [-quiet] [-verbose] name type



name

type

ChipScope

ChipScope

create_debug_core CLK (TRIG)

DATA (TRIG_OUT) TRIG

1 1 TRIG DATA

set_propertyset_propertyset_property port_widthport_widthport_width ()

: CLK TRIG_OUT 1

connect_debug_portconnect_debug_portconnect_debug_port disconnect_debug_portdisconnect_debug_portdisconnect_debug_port

name : ChipScope create_debug_portread_chipscope_cdc



Tcl ()

type : CLKDATATRIG TRIG_OUT ChipScope Pro

(UG029)

: ILA CLKDATATRIG_OUT 1

(TRIG)


TCL_OK



ChipScope DATA

create_debug_core myCore chipscope_ila_v1

create_debug_port myCore DATA

myCore 8

create_debug_port myCore TRIG

set_property PORT_WIDTH 8 [get_debug_ports myCore/TRIG0]

connect_debug_port -channel_start_index 1 myCore/TRIG0 {m1_cyc_i \

m1_ack_o m1_err_o m1_rty_o}

: core_name/port_name

connect_debug_port

create_debug_core


read_chipscope_cdc

set_property



Tcl ()

create_drc_check

DRC

create_drc_check [-category arg] -name arg [-desc arg] [-msg arg][-rule_body arg] [-quiet] [-verbose]

[-category-category-category] DRC User Defined

-name-name-name DRC PREFIX-id (PREFIX 4 6 id ) id

[-desc-desc-desc] DRC User rule - default description

[-msg-msg-msg] DRC %MSG_STRING%NETLIST_ELEMENT%SITE_GROUP%CLOCK_REGION%BANK

[-rule_body-rule_body-rule_body] Tcl Tcl



DRC

report_drcreport_drcreport_drc DRC (drc_check)

report_drcreport_drcreport_drc Tcl

Tcl

create_drc_violationcreate_drc_violationcreate_drc_violation



Tcl ()

Tcl Tcl Tcl

report_drcreport_drcreport_drc sourcesourcesource

Tcl create_drc_violationcreate_drc_violationcreate_drc_violation

create_drc_checkcreate_drc_checkcreate_drc_check -rule_body-rule_body-rule_body Tcl

DRC

create_drc_ruledeckcreate_drc_ruledeckcreate_drc_ruledeck add_drc_checksadd_drc_checksadd_drc_checks


drc_check drc_check

delete_drc_check

-category-category-category arg () : User Defined GUI DRC

-name-name-name arg : -rule_body-rule_body-rule_body Tcl create_drc_violationcreate_drc_violationcreate_drc_violation DRC

4 6

ID (ABCD-1ABCD-23 )

-desc-desc-desc arg () : User Rule GUI DRC DRC

-msg-msg-msg arg () :


%MSG_STRING (%STR) : create_drc_violationcreate_drc_violationcreate_drc_violation -msg-msg-msg

: create_drc_checkcreate_drc_checkcreate_drc_check -msg-msg-msg %STR

create_drc_violation -rule_body-rule_body-rule_body DRC

%NETLIST_ELEMENT (%ELG) :

%SITE_GROUP (%SIG) :

%CLOCK_REGION (%CRG) :

%BANK (%PBG) : I/O

-rule_body-rule_body-rule_body arg () : Tcl Tcl -rule_body-rule_body-rule_body Tcl report_drcreport_drcreport_drc

sourcesourcesource



Tcl ()

Tcl create_drc_violation

DRC -msg-msg-msg


TCL_OK



RAMW-1

dataWidthCheck

create_drc_check -name {RAMW-1} -category {RAMB} \

-desc {Data Width Check} -rule_body dataWidthCheck

Tcl dataWidthCheckdataWidthCheckdataWidthCheck RAMW-1

-rule_body-rule_body-rule_body Tcl report_drc

sourcesourcesource

# This is a simplistic check -- report BRAM cells with WRITE_WIDTH_B wider than 36.proc dataWidthCheck {} {

# list to hold violationsset vios {}# iterate through the objects to be checkedforeach bram [get_cells -hier -filter {PRIMITIVE_SUBGROUP == bram}] {

set bwidth [get_property WRITE_WIDTH_B $bram]if { $bwidth > 36} {

# define the message to report when violations are foundset msg "On cell %ELG, WRITE_WIDTH_B is $bwidth"set vio [ create_drc_violation -name {RAMW-1} -msg $msg $bram ]lappend vios $vio

}}if {[llength $vios] > 0} {

return -code error $vios} else {

return {}}

}create_drc_check -name {RAMW-1} \

-category {RAMB Checks} \-desc {Data Width Check} \-rule_body dataWidthCheck

: Tcl report_drcreport_drcreport_drc create_drc_checkcreate_drc_checkcreate_drc_check Tcl dataWidthCheckdataWidthCheckdataWidthCheck RAMW-1



Tcl ()

add_drc_checks

create_drc_ruledeck


delete_drc_check

get_drc_checks

get_drc_vios

report_drc



Tcl ()

create_drc_ruledeck

1 DRC

create_drc_ruledeck [-quiet] [-verbose] ruledecks ...

DRC



ruledecks

DRC

report_drc 1

D

Documents

Vivado Design Suite Tcl コマンド リファレンス ガイド … · VivadoDesignSuiteTclコマンドリファレンスガイド UG835(v2012.3)2012年10月16日 2 . 第1章 概要

Vivado Design Suite Tcl コマンドリファレンスガイド … · VivadoDesignSuiteTclコマンドリファレンスガイド UG835(v2012.3)2012年10月16日 2 . 第1章概要