7/23/2019 VLSI Cad FDP Brouchure
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About COEP & E&TC DepartmentCollege of Engineering, Pune
(COEP) is one
of the prestigious engineering colleges inIndia. Established in
1854, it is the third oldestengineering college in Asia. It is
located inPune, Maharashtra. In 2004, the Institute wasgranted
complete autonomy by the StateGovernment & declared as Center
forExcellence in Technical Education. TheInstitute now is an
autonomous engineeringschool with permanent affiliation to
theUniversity of Pune.The Department of Electronics
andTelecommunication Engineering (E&TC) has
been playing a vital role in producingengineers &
technologists of highest caliber
ever since it was established in the year 1948.The department
offers UG programme with 60intake, two PG programmes with four
specializations (Digital Systems, VLSI &Embedded Systems,
Wired & Wireless
Communication, and Signal Processing) andResearch
programmes.
About the SpeakerMr. Pramod Sabnis obtained Bachelor
ofEngineering (1988) from Walchand Instituteof Technology, Solapur
and M. Tech (1991)from Karnataka Regional Engineering
College, Suratkal.Mr. Sabnis has Total industry experience of
23years in Industrial Drives and Automation,Chip Design, Training
and Development.He has 15+ years of experiencein ASIC/ SoCPhysical
Design.Currently Mr. Sabnis holds the position of
Director ASIC/ SOC implementation atGraphene Semiconductor. In
this role, hisresponsibility is to execute projects, mentor
the team in execution aspects of Chip design,
acquire exposure to newer areas and build thecompetency.
Mr. Sabnis has been successful in buildingteams from scratch at
Qualcore, Sasken andInfosys.He has been involved in design,
methodologydevelopment, design-automation and projectmanagement and
was extensively involved inTraining and Development in VLSI
Design.
Scope of the courseThis FDP focuses on ASIC Physical
Design.Physical Design is the process of translating adesign from a
logical/ behavioral domain to
physical domain. The physical designengineer has to think terms
of real wires and
real physical effects. This process starts withestimation and
analysis of the design. Thereare a number of inputs that a physical
design
engineer has to deal with for this analysis. Theanalysis phase
is followed by Implementation
phase where the design is actually takenthrough the complex
physical design flow.This flow is run with strict PPA (power,
performance and area) goals. These goals aresacro sanct and
these have to be met in tehstipulated time to market. The
Implementation
phase is followed by Verification phase wherethe PPA metrics are
measured and design is
closed.The above three phases make up the ASIC/SoC physical
design process.The FDP intends to familiarize the participantswith
the above process through theory andlabs. The FDP will also cover
the differentinputs that a physical design engineer has todeal
with, their analysis and inferences.ThisFDP will also include a
session on TCLscripting which is a MUST have skill in VLSI
field.
Objectives
One of the major challenges faced by theteachers is in bridging
the concepts to theapplication and to bring out the practical
perspective for an effective teaching learning interaction. This
FDP is designed1. To enable teachers to bridge this gapthrough a
series of handson illustrative
teachinglearning activities/experimentsthat will help connecting
the theoreticalconcepts to the industry relevant application
perspective as well as practices.2. To provide an overview of
the topics with
emphasis on opportunities for getting ready tohandle industrial
application requirement.3. To provide Hands-on experience inCadence
tool.
Broad Topics to be coveredThis FDP will deal with complete Place
andRoute flow of a designThis will involve theory and labs on:
a) Floor planningb) IO planningc) Power planningd) Standard
Cells Placemente) Different clock structures and CT Synthesisf)
Routingg) TCL Scripting
Resource person
Mr. Pramod Sabnis
Director, ASIC/SOC Implementation,
Graphene Semiconductor Services
Pvt.Ltd, Bangalore
7/23/2019 VLSI Cad FDP Brouchure
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Registration form
1. Name: ____________________________
2. Category: Academic / Industry
3. Organization: ______________________
4. Address__________________________
_________________________________
_________________________________
5. Professional
ExperienceTeaching/Industry__________________
6. Research interest
________________________________________________________________
7. Email Id: _______________________
8. Mobile Number: __________________
9. DD No. & Bank: __________________(DD should be drawn in
favor of DIRECTOR,
COEP, payable at Pune)
Declaration by the candidateThe given information is true to the
best of myknowledge.I agree to abide by the rules and
regulations
governing the programme. If selected, I shallattend the course
for the entire duration.Date:Place:
Signature:
Important Dates to Remember:Last date for registration:
18/01/2016
Intimation date: 20/01/2016
The brochure, application form & technical
details can also be downloaded from college
website:www.coep.org.in
Details of Registration
Faculty Rs 10,000/-
Industry personnel - Rs 15,000/-
Research scholar- Rs 5000/-The registration fee includes cost
towardscourse material, lunch, and refreshment.
RegistrationRegistration for the FDP can be made bysending the
duly filled application form alongwith Demand Draft payable at
Pune.
Eligibility:1. Faculty working in Engineering
Colleges/Polytechnic colleges
2. Engineers from R&D Organizations/Industries.3. Research
ScholarsNote:
1. Only 20 participants will be selected on first
come first served basis.
2. Intimation of selection /confirmation will be
only through Email till 20 Jan 2016.
3. If you are selected, the fee paid will not be
refunded under any circumstances.
4. If required, ACCOMMODATION for the
participants will be suggested.
5. No TA/DA will be provided to any participant
The duly filled application form along with
DD is to be sent to:
Ms. Vanita Agarwal
Department of E&TC Engineering
College of Engineering, Pune (COEP)
Wellesley Road, Shivajinagar, Pune-411005
Phone: 020-2550 7616, 09665366195
Fax: 020-2550 7299
Website: www.coep.org.in
Email:[email protected]
TEQIP II sponsoredOne week
Faculty Development Program
on
VLSI CAD using Cadence tool(Jan 22-26, 2016)
Organized by
Department of Electronics &Telecommunication
Engineering,
College of Engineering, Pune (COEP)(An Autonomous Institute of
the
Government of Maharashtra)
Course Coordinators
Ms Vaishali V Ingale(8149477127)
Associate Prof., E & TC, COEP
Ms. Vanita Agarwal(9665366195)
Assistant Prof., E & TC, COEP
http://www.coep.org.in/http://www.coep.org.in/http://www.coep.org.in/mailto:[email protected]:[email protected]:[email protected]:[email protected]://www.coep.org.in/
