VRCH RISC 1

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BITS Pilani, Pilani Campus

RISC - ARCHITECTURE

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Complex instructions have certain disadvantages that a small percentage

of such instructions can sometimes reduce a computers overall

performance.

Processors having small simple instructions each having k time units, itcan execute 100 instructions in 100k time units

If 5% of instructions are slow requiring 21K units each, to execute an

average set of 100 instructions requires (5*21 +95)k = 200 time units.

--- double overall program execution time

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Reduced Instruction Set Computer

- Relatively few instructions

- Relatively few addressing modes

- Memory access limited to load and store- Fixed length and easily decodable instruction format

- Hardwired mostly

- Relatively large number of registers in the processor

- Efficient Instruction pipeline

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Example - RISC Architectures

-Hewlett Packard PA- RISC

-IBM and MOTOROLA Power PC-SGI MIPS

-SPARC Developed by SUN Microsystems

-ARM Advanced RISC machine

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Processor chosen for study

Register Set:

32 bit general purpose registers- 31 in number (R1-R31)

Register R0 Special purpose , value always zero, used to synthesize a

variety of functions.

Floating point registers (FPRs) used as single precision (32-bit) registers.

Data Types:8-bit, 16-bit, 32-bit for integer data

32-bit single precision, 64-bit double precision

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Addressing Modes:

Immediate and displacement both with 16-bit fields

(register + offset (displacement (or) based)

Since one register that has zero always when used in

addressing mode can be synthesized using r0 as the base

displacement addressing.

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Instruction Formats:

To provide facility for pipelining in the architecture all instructions are made

of size 32-bits with a 6-bit primary opcode.

Op 6 RS1 5 RS2 5 RD 5 OP X 11

RS1 source register 1

RS2 source register 2Rd destination register

OP operation details.

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LW R1, 30(R2) - Load Word

Reg [R1] mem [30 + reg( R2)]

LW R1, 1000(RO) - Load Word

Reg [R1] mem [1000+0]

SH R3, 502(R2) - store halfword

Mem [ 502 + reg [R2]] Reg [R3] 16--------32

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Overview: Processor Implementation

Single Cycle

perform each instruction in 1 clock cycle

clock cycle must be long enough for slowest instruction; therefore,

disadvantage: only as fast as slowest instruction

Multi-Cycle

break fetch/execute cycle into multiple steps

perform 1 step in each clock cycle

advantage: each instruction uses only as many cycles as it needs

Pipelined

execute each instruction in multiple steps

perform 1 step / instruction in each clock cycle

process multiple instructions in parallel assembly line

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Implementing MIPS

op rs rt offset

6 bits 5 bits 5 bits 16 bits

op rs rt rd functshamt

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

R-Format

I-Format

op address

6 bits 26 bits

J-Format

arithmetic-logic instructions: add, sub, and, or, slt

memory-reference instructions: lw, sw

control-flow instructions:beq, j

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Two types of functional elements in the hardware:

elements that operate on data (called

combinational elements)

elements that contain data (called state or

sequential elements)

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An overview of Implementation:

For every Instruction

Send Program Counter(PC) to memory that contains code and fetch the

instruction from that memory

Read one or two registers, using fields of the instruction to select the registers to

read. For the load word instruction, we need to read only one register, but most

other instructions require that we need two registers.

After these two steps actions required depend on instruction class.

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All instruction classes except jump use arithmetic-logic unit (ALU) after

reading the registers.

Memory reference instructions use ALU for an address calculation

Arithmetic-logical instruction for operation execution

Branch for comparison.

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After using ALU, the actions required to complete various instruction classes

differ

A memory reference instruction will need to access memory either to writedata for a store or read data for load

An arithmetic/logical instruction write data from the ALU back into the

register

For branch instruction may need to change the next instruction addressbased on comparison.

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Adding instruction fetch

Separate instruction memoryas instruction and data readoccur in the same clock cycle

Separate adder as ALU operations and PCincrement occur in the same clock cycle

PC

Instructionmemory

Readaddress

Instruction

16 32

Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

ALUresult

Zero

Datamemory

Address

Write

data

Readdata

Mux

4

Add

Mux

ALU

RegWrite

ALU operation3

MemRead

MemWrite

ALUSrcMemtoReg

Single Cycle Implementation

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PC

Instructionmemory

Readaddress

Instruction

16 32

Add ALUresult

Mux

Registers

Writeregister

Write

data

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Shift

left 2

4

Mux

ALU operation3

RegWrite

MemRead

MemWrite

PCSrc

ALUSrc

MemtoReg

ALUresult

ZeroALU

Data

memory

Address

Writedata

Readdata M

ux

Signextend

Add

Adding branch capability and another multiplexor

Instruction address is eitherPC+4 or branch target address

Extra adder needed as bothadders operate in each cycle

New multiplexor

Documents

VRCH RISC 1