W-DS-0004-A0 BIT1611B

B i T E K DCC CONTROLLED

May 16, 2007

Beyond Innovation Technology Co., Ltd. BIT1611B

2006/5/5 Confidential, for authorized user only page 1 of 109 DOC NO.W-DS-0004

BIT1611B

Digital Video Decoder with

OSD, T-CON and DAC

Version: A0

Please read the notice stated in this preamble carefully before accessing any contents of the document attached. Admission of BiTEKs statement therein is presumed once the document is released to the receiver.


May 16, 2007



Notice:

Firstly, the information furnished by Beyond Innovation Technology Co. Ltd. (BiTEK) in this document is believed to be accurate and reliable and subject to BiTEKs amendment without prior notice. And the aforesaid information does not form any part or parts of any quotation or contract between BiTEK and the information receiver.

Further, no responsibility is assumed for the usage of the aforesaid information. BiTEK makes no representation that the interconnect of its circuits as described herein will not infringe on exiting or future patent rights, nor do the descriptions contained herein imply the granting of licenses to make, use or sell equipment constructed in accordance therewith.

Besides, the product in this document is not designed for use in life support appliances, devices, or systems where

malfunction of this product can reasonably be expected to result in personal injury. BiTEK customers using or selling this product for use in such applications shall do so at their own risk and agree to fully indemnify BiTEK for any damage resulting from such improper use or sale.

At last, the information furnished in this document is the property of BiTEK and shall be treated as highly

confidentiality; any kind of distribution, disclosure, copying, transformation or use of whole or parts of this document without duly authorization from BiTEK by prior written consent is strictly prohibited. The receiver shall fully compensate BiTEK without any reservation for any losses thereof due to its violation of BiTEKs confidential request. The receiver is deemed to agree on BiTEKs confidential request therein suppose that said receiver receives this document without making any expressly opposition. In the condition that aforesaid opposition is made, the receiver shall return this document to BiTEK immediately without any delay. -Version A4


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Contents 1 General Description............................................................................. 10 2 Feature.................................................................................................11 3 Order Information ................................................................................ 13 4 Functional Block Diagram.................................................................... 13 5 Pin Definition ....................................................................................... 14 6 Application Examples .......................................................................... 18 7 Function Description............................................................................ 20

7-1 Version Control............................................................................................................................ 20 7-2 Interrupt Function ........................................................................................................................ 20 7-3 Double Buffer .............................................................................................................................. 22 7-4 Pad Type Setup........................................................................................................................... 22 7-5 GPO (General Purpose Output) Function................................................................................... 25 7-6 System Enable and Reset........................................................................................................... 28

7.6.1 Hardware Reset.................................................................................................................. 28 7.6.2 Software Reset ................................................................................................................... 28

7-7 Built-in DAC................................................................................................................................. 29 7-8 Clock Domain Systems ............................................................................................................... 30 7-9 Panel Timing Setup ..................................................................................................................... 31 7-10 Output Data Path......................................................................................................................... 32 7-11 Serial RGB Output Mode ............................................................................................................ 33 7-12 Special Output Setup .................................................................................................................. 33 7-13 Special Timing Adjustment .......................................................................................................... 34

7.13.1 Synchronization Timing ...................................................................................................... 34 7.13.2 Two-Fields Synchronization Timing.................................................................................... 34

7-14 TCON Function ........................................................................................................................... 35 7-15 TCON Clock Mode ...................................................................................................................... 36 7-16 External Pin Setup ...................................................................................................................... 37 7-17 Display Layer............................................................................................................................... 39 7-18 Background 2 .............................................................................................................................. 39 7-19 Background and Test Pattern Setup ........................................................................................... 40 7-20 Auto Blue Screen ........................................................................................................................ 40 7-21 Input Image Window Setup ......................................................................................................... 41 7-22 Input Data Path Setup................................................................................................................. 42 7-23 Input Format................................................................................................................................ 43

7.23.1 ITU656................................................................................................................................ 43 7.23.2 ITU656-Like ........................................................................................................................ 43 7.23.3 ITU601................................................................................................................................ 43 7.23.4 RGB888.............................................................................................................................. 43 7.23.5 Serial-RGB ......................................................................................................................... 44 7.23.6 YUV444 .............................................................................................................................. 44

7-24 Input Mode Selection .................................................................................................................. 44 7-25 CSYNC Decoder ......................................................................................................................... 46 7-26 Auto Switch ................................................................................................................................. 47 7-27 Display Window Setup ................................................................................................................ 47 7-28 Re-size Engine ............................................................................................................................ 48


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7.28.1 Horizontal Re-size Down .................................................................................................... 48 7.28.2 Vertical Re-size Down ........................................................................................................ 49

7-29 Timing Adjustment....................................................................................................................... 50 7-30 Brightness/Contrast Adjustment.................................................................................................. 53 7-31 Image Enhancement ................................................................................................................... 55

7.31.1 Black Level and Black/White expansion............................................................................. 55 7.31.2 Sharpness and Smoothness Process ................................................................................ 56 7.31.3 UV Domain Process ........................................................................................................... 57 7.31.4 Chroma Transient Improvement (CTI)................................................................................ 58

7-32 Gamma Correction...................................................................................................................... 58 7.32.1 Adjust-Curve....................................................................................................................... 58 7.32.2 Look-Up-Table (LUT) .......................................................................................................... 59

7-33 Dither........................................................................................................................................... 60 7-34 Color Space Conversion ............................................................................................................. 60 7-35 PLL and OSC Pads ..................................................................................................................... 60 7-36 Timer ........................................................................................................................................... 61 7-37 GPI and KEY Function ................................................................................................................ 62 7-38 Auto Detection............................................................................................................................. 63 7-39 EEPROM Setup .......................................................................................................................... 64 7-40 Serial Peripheral Interface (SPI) ................................................................................................. 64 7-41 Power Sequence Control ............................................................................................................ 66 7-42 PWM Function............................................................................................................................. 67 7-43 Feedback PWM Control .............................................................................................................. 69 7-44 IR Decoder Function ................................................................................................................... 70 7-45 Video Decoder............................................................................................................................. 71

7.45.1 Architectures....................................................................................................................... 71 7.45.2 Analog Input Path ............................................................................................................... 71 7.45.3 Color Standard Setting and detect ..................................................................................... 72 7.45.4 Luminance Process ............................................................................................................ 73 7.45.5 Chroma Process................................................................................................................. 75 7.45.6 Synchronization Process .................................................................................................... 77 7.45.7 AFE Architectures............................................................................................................... 78 7.45.8 Analog AGC Control ........................................................................................................... 78 7.45.9 Analog Clamp Control ........................................................................................................ 79 7.45.10 Digital AGC and Clamp Control ......................................................................................... 80 7.45.11 ADC Control ...................................................................................................................... 81 7.45.12 AFE PLL Clock Control...................................................................................................... 82 7.45.13 Status Register .................................................................................................................. 82

7-46 OSD Function.............................................................................................................................. 84 7.46.1 OSD Windows Function ..................................................................................................... 84 7.46.2 OSD Memory Mapping....................................................................................................... 85 7.46.3 OSD Windows Attribute ...................................................................................................... 88 7.46.4 External OSD Interface....................................................................................................... 90 7.46.5 OSD User Programmable RAM Selection.......................................................................... 92 7.46.6 OSD Built-in Fixed Font...................................................................................................... 93

8 Interface Mode .................................................................................... 94 8-1 Options Pins ................................................................................................................................ 94 8-2 Script Master Mode ..................................................................................................................... 94

8.2.1 Architecture ........................................................................................................................ 94


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8.2.2 Start and Interrupt............................................................................................................... 95 8.2.3 Instruction Set..................................................................................................................... 95 8.2.4 Instruction Format............................................................................................................... 97

8-3 Slave Mode ................................................................................................................................. 99 8.3.1 BiTEKbus Protocol ............................................................................................................. 99 8.3.2 Two-Wire Protocol ............................................................................................................ 100

9 Timing Diagram ................................................................................. 103 9-1 Hardware Reset: ....................................................................................................................... 103 9-2 Clock and Interrupt: ................................................................................................................... 103 9-3 Input Signal: .............................................................................................................................. 103 9-4 Output Signal:............................................................................................................................ 104 9-5 Micro Processor Interface: ........................................................................................................ 104

10 Electrical Characteristic ..................................................................... 106 11 Soldering Information ........................................................................ 107

11-1 Reflow Soldering: ...................................................................................................................... 107 11-2 Wave Soldering: ........................................................................................................................ 107 11-3 Manual Soldering: ..................................................................................................................... 108

12 Package Information ......................................................................... 109


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Tables Table 5-1 BIT1611B PIN Define ................................................................................................................................... 15 Table 7-1 Version Control Register .............................................................................................................................. 20 Table 7-2 Interrupt Source............................................................................................................................................ 20 Table 7-3 Interrupt Register.......................................................................................................................................... 20 Table 7-4 Video Decoder lock source for interrupt select ............................................................................................. 21 Table 7-5 Double Buffer Register ................................................................................................................................. 22 Table 7-6 Multi-Function Pads...................................................................................................................................... 22 Table 7-7 Output Tri-State Control Register ................................................................................................................. 25 Table 7-8 General Purpose Output Register ................................................................................................................ 25 Table 7-9 General Purpose Output Pads Setup Table.................................................................................................. 26 Table 7-10 Soft Reset Register .................................................................................................................................... 28 Table 7-11 DAC Register.............................................................................................................................................. 29 Table 7-12 Clock Domain System Register.................................................................................................................. 30 Table 7-13 Panel Timing Setup register ....................................................................................................................... 31 Table 7-14 Output Data Path Register ......................................................................................................................... 32 Table 7-15 Serial RGB Output Register ....................................................................................................................... 33 Table 7-16 Special Output Pads Setup Register .......................................................................................................... 33 Table 7-17 Special Timing Adjust Register ................................................................................................................... 34 Table 7-18 TCON Function Register ............................................................................................................................ 35 Table 7-19 TCON Clock Mode Register....................................................................................................................... 36 Table 7-20 External Pin Setup...................................................................................................................................... 37 Table 7-21 External Pin Setup Mapping....................................................................................................................... 38 Table 7-22 Background 2 Register............................................................................................................................... 39 Table 7-23 Background and Test Pattern Register....................................................................................................... 40 Table 7-24 Blue Screen Register ................................................................................................................................. 40 Table 7-25 Input Crop Register .................................................................................................................................... 41 Table 7-26 Output Data Path Register ......................................................................................................................... 42 Table 7-27 Input Mode Select Register ........................................................................................................................ 44 Table 7-28 CSYNC Decoder register ........................................................................................................................... 46 Table 7-29 Auto Switch Register .................................................................................................................................. 47 Table 7-30 Display Windows Register.......................................................................................................................... 47 Table 7-31 Horizontal Scale Down Register................................................................................................................. 48 Table 7-32 Vertical Scale-Down Register ..................................................................................................................... 49 Table 7-33 Timing Adjust Register................................................................................................................................ 51 Table 7-34 Color Adjustment Register.......................................................................................................................... 53 Table 7-35 Y Domain Process Register ....................................................................................................................... 55 Table 7-36 Sharpness and Smoothness Process Register .......................................................................................... 56 Table 7-37 UV Domain Register................................................................................................................................... 57 Table 7-38 Chroma Transient Improvement Register................................................................................................... 58 Table 7-39 Adjust-Curve Register ................................................................................................................................ 59 Table 7-40 LUT Gamma Memory Address ................................................................................................................... 59 Table 7-41 LUT Gamma Register ................................................................................................................................ 60 Table 7-42 Dither Register ........................................................................................................................................... 60 Table 7-43 Color Space Converter Register................................................................................................................. 60 Table 7-44 PLL Register............................................................................................................................................... 60 Table 7-45 Timer Register............................................................................................................................................ 61


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Table 7-46 GPI and KEY Register................................................................................................................................ 62 Table 7-47 Auto Detection Register ............................................................................................................................. 64 Table 7-48 EEPROM Read/Write Speed Register ....................................................................................................... 64 Table 7-49 SPI Register ............................................................................................................................................... 64 Table 7-50 Power Sequence Control Register ............................................................................................................. 66 Table 7-51 PWM Function Register ............................................................................................................................. 67 Table 7-52 Feedback PWM Function Register............................................................................................................. 69 Table 7-53 IR PWM Pulse Detect Register .................................................................................................................. 70 Table 7-54 Analog Input Path Register ........................................................................................................................ 72 Table 7-55 Color Standard register .............................................................................................................................. 73 Table 7-56 Luminance Process Register...................................................................................................................... 74 Table 7-57 Chroma Process Register .......................................................................................................................... 75 Table 7-58 Synchronization process Register .............................................................................................................. 77 Table 7-59 Analog AGC Control Register..................................................................................................................... 78 Table 7-60 Clamp Control Register .............................................................................................................................. 79 Table 7-61 Digital AGC Control Register ...................................................................................................................... 80 Table 7-62 ADC Control Register................................................................................................................................. 81 Table 7-63 AFE PLL Clock Control Register ................................................................................................................ 82 Table 7-64 Video Decoder Status Register .................................................................................................................. 83 Table 7-65 OSD Windows Register.............................................................................................................................. 84 Table 7-66 OSD Memory Mapping Table ..................................................................................................................... 85 Table 7-67 OSD Windows Attribute Register................................................................................................................ 88 Table 7-68 External OSD Register ............................................................................................................................... 90 Table 8-1 Options Pins Setup....................................................................................................................................... 94 Table 8-2 Register and Address Index ......................................................................................................................... 94 Table 8-3 Register and Address Index ......................................................................................................................... 95 Table 8-4 Instruction Set .............................................................................................................................................. 95 Table 8-5 BiTEKbus Slave Address ............................................................................................................................. 99 Table 8-6 Two-Wire Protocol Device Address ............................................................................................................ 100


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Figures Figure 4-1 BIT1611B Architecture ................................................................................................................................ 13 Figure 5-1 Pin configuration (LQFP-128) ..................................................................................................................... 14 Figure 6-1 Application 1 ............................................................................................................................................... 18 Figure 6-2 Application 2 ............................................................................................................................................... 18 Figure 6-3 Application 3 ............................................................................................................................................... 19 Figure 6-4 Application 4 ............................................................................................................................................... 19 Figure 7-1 Interrupt Function Block.............................................................................................................................. 21 Figure 7-2 Double Buffer Function ............................................................................................................................... 22 Figure 7-3 GPO function .............................................................................................................................................. 27 Figure 7-4 Hardware Reset Waveform......................................................................................................................... 28 Figure 7-5 Clock Select Function ................................................................................................................................. 31 Figure 7-6 Panel Timing Setup..................................................................................................................................... 32 Figure 7-7 Output Data Path Select ............................................................................................................................. 33 Figure 7-8 Synchronization Timing............................................................................................................................... 34 Figure 7-9 Two-Fields Synchronization Timing ............................................................................................................ 34 Figure 7-10 TCON Clock Mode.................................................................................................................................... 36 Figure 7-11 External Pin Setup .................................................................................................................................... 38 Figure 7-12 Display Layer............................................................................................................................................ 39 Figure 7-13 Input Window Setup.................................................................................................................................. 41 Figure 7-14 Input Data Path Setup .............................................................................................................................. 42 Figure 7-15 ITU656/656-like input................................................................................................................................ 43 Figure 7-16 ITU601 input ............................................................................................................................................. 43 Figure 7-17 RGB 8:8:8 input ........................................................................................................................................ 43 Figure 7-18 Serial-RGB input....................................................................................................................................... 44 Figure 7-19 YUV 4:4:4 input......................................................................................................................................... 44 Figure 7-20 Input Mode Select..................................................................................................................................... 46 Figure 7-21 Display Window Setup.............................................................................................................................. 47 Figure 7-22 Re-size function ........................................................................................................................................ 48 Figure 7-23 Timing Adjustment VREF Information ....................................................................................................... 50 Figure 7-24 R_OS_XT Adjust flow chart ...................................................................................................................... 52 Figure 7-25 Timing Adjust flow..................................................................................................................................... 53 Figure 7-26 Brightness and Contrast ........................................................................................................................... 54 Figure 7-27 Gamma LUT Ram Setting......................................................................................................................... 54 Figure 7-28 Black Level Adjustment............................................................................................................................. 55 Figure 7-29 Black and White Adjustment ..................................................................................................................... 56 Figure 7-30 Black and White Slope.............................................................................................................................. 56 Figure 7-31 Gamma Correction ................................................................................................................................... 58 Figure 7-32 Example of Adjust-Curve .......................................................................................................................... 59 Figure 7-33 SPI Protocol.............................................................................................................................................. 65 Figure 7-34 Power Sequence Function........................................................................................................................ 67 Figure 7-35 PWM function ........................................................................................................................................... 68 Figure 7-36 Video Decoder Architectures .................................................................................................................... 71 Figure 7-37 Video Decoder Analog Input Path............................................................................................................. 72 Figure 7-38 Luminance Process .................................................................................................................................. 73 Figure 7-39 Chroma Process Function Block............................................................................................................... 75 Figure 7-40 Synchronization Process .......................................................................................................................... 77


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Figure 7-41 AFE Architectures ..................................................................................................................................... 78 Figure 7-42 Analog Auto Gain Control ......................................................................................................................... 78 Figure 7-43 Video Decoder PLL................................................................................................................................... 82 Figure 7-44 OSD Windows Setup ................................................................................................................................ 85 Figure 7-45 OSD Memory Mapping ............................................................................................................................. 86 Figure 7-46 OSD User Programmable Font RAM........................................................................................................ 87 Figure 7-47 Palette RAM Example............................................................................................................................... 87 Figure 7-48 OSD Windows Attribute ............................................................................................................................ 90 Figure 7-49 Fixed FONT .............................................................................................................................................. 93 Figure 8-1 Bitek Serial Interface bus............................................................................................................................ 99 Figure 8-2 BiTEKbus Extension Mode ....................................................................................................................... 100 Figure 8-3 I2C Slave Address Mapping...................................................................................................................... 101 Figure 8-4 Read/Write Mode...................................................................................................................................... 102


May 16, 2007



1 General Description

BIT1611B is a high performance digital video decoder combining T-CON, OSD and DAC within one single device. The decoder transfers and decodes most popular NTSC and PAL video contents from TV tuner or DVD sources. Signal feeding into BIT1611B includes analog CVBS and Y/C, digital CCIR656 and digital RGB format. The Automatic Gain Control (AGC) for AD converter extends the capability for handling weak and distorted signals. Advanced CTI and Skin-Tone processes help for improving the picture quality a lot. The programmable timing control (T-CON) let most of the popular panels (resolution under 512xRGBx512) used for BIT1611B system. Programmable brightness, contrast and color saturation with embedded GAMMA correction let user compensate any color problem of display. Embedded OSD makes system designer very easy to develop a friendly interface between user and end product. Advanced wide range display format controller can convert a 4:3 display to 16:9 very smoothly. BIT1611B can be used for a traditional hand-held LCD monitor very easily. With the outstanding video processing performance, it is also suitable for Car TV/navigation system and portable AV system. For some LCD monitors, which combine graphic and video input within a single system, BIT1611B is the most convenient and compact solution.


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2 Feature 2-1 General: y No external memory required y Two 8-bit video CMOS analog-to-digital converters y Require only one crystal (24.576MHz) for all color standards y YUV to RGB color space converting y Programmable arbitrary zoom-out ratio in horizontal and vertical y Anamorphic 4:3 to 16:9 display converting y Embedded brightness, contrast, sharpness and gamma correction y Embedded Skin-Tone and CTI y Embedded programmable OSD for user Interface y Embedded programmable TCON (Timing-Control) generator for LCD interface y Embedded 4 PWM (Pulse Width Modulator) generators for general purpose control y Embedded IR remote control decoder y Embedded video decoder

2-2 Input: y Four analog inputs, internal analog source selectors,

for example (4 x CVBS) or (2 x Y/C) or (1 x Y/C and 2 x CVBS) y Automatic detection of 50 and 60 Hz field frequency y Programmable switching between PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43 and NTSC Japan and

SECAM standards y 24-bit RGB/YUV input up to 30MHz y 16-Bits RGB (RGB 5/6/5) input y 8-bit Serial RGB Data format y ITU-R BT.601 16-bit (CCIR 601) y ITU-R BT.656 8-bit (CCIR 656) y Support digital MUX for two video source input y Built-in YUV to RGB color space converter y Programmable RGB input ports sequence and pins sequence y 5V tolerance input pads support 5V/3.3V interface

2-3 Output: y Single (18/24 bits) port RGB data output y Programmable RGB output ports sequence and pins sequence y Analog RGB output support line invert function y Maximum output pixel frequency 30 MHz y Support inverse and frequency adjustment for LCD panel clock y Support programmable H/V sync. for LCD panel y Support programmable TCON for LCD panel y Support Serial-RGB Interface LCD Panel y Support Delta and Stripe types LCD panel y Free-run Synchronization mode if sync signal disappeared

2-4 Interface: y Support Two-wire BiTEKbus interface y Support I2C bus interface y Support 24Cxx serials EEPROM Script controller


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2-5 OSD: y Built-in OSD generator with 240 ROM fonts, 512 mix color, 3 windows y 16 user download fonts y 5 sizes of zooming font (1/2, x1, x2, x3, x4) y Flashing font attribute y Fringe font attribute y Transparent overlay for OSD windows y Support external OSD interface

2-6 Power management: y 3V power source, 5V tolerant for input pads y 3.3V / 5V power source for output pads

2-7 Package: y LQFP 128 pins


May 16, 2007



3 Order Information

BIT 1611B - LQ LQFP type package Part number Beyond Innovation Technology Co., Ltd.

4 Functional Block Diagram

Figure 4-1 BIT1611B Architecture


May 16, 2007



5 Pin Definition

BIT1611BLQFP_128

123456789

10111213141516171819202122232425

101

100

99 98 97

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

AVDD

AVDD

AVDD

AVDD

GIN

[2]/O

SD

BG

IN[3

]/OS

DB

LAN

KG

IN[4

]/OS

DH

S

RIN5RIN6RIN7 OPTIONS[4]GND

TEST

AOUT2AGNDREFB2REFT2

AIN22AGNDAIN21

AOUT1AGNDREFB1REFT1

AIN12AGND

IRVC

C

AIN11

BIN

[2]/G

PI[

2]AGND

BIN

[1]/G

PI[

1]/E

XT

UD

BIN

[0]/G

PI[

0]/E

XT

RL

P6_

SE

L/B

OU

T7

P5_

SE

L/B

OU

T6

HG

ND

TG

PO

[2]/B

OU

T5

TG

PO

[1]/B

OU

T4

HV

DD

CP

H3

/GO

UT

7H

VD

DC

PH

2/G

OU

T6

DA

C_

RE

FT

ALA

LOG

_B

P5_

SE

L/T

CO

N_R

L/B

OU

T0

P6_

SE

L/T

CO

N_U

D/B

OU

T1

HG

ND

Q2H

/BO

UT

2T

GP

O[0

]/BO

UT

3

GIN

[0]/O

SD

RG

IN[1

]/OS

DG

ICLK

2V

CC

GN

D

HS

YN

C1

BIN

[3]/G

PI[

3]G

ND

BIN

[4]/G

PI[

4]B

IN[5

]/GP

I[5]

BIN

[6]/G

PI[

6]B

IN[7

]/GP

I[7]

VCCOPTIONS[3]

HGND

INT

GN

DR

ES

ET

#G

ND

A

FB4/VSYNC2H

GN

DGND

OPTIONS[5]

VS

YN

C1

60 61 62 63 6440 41

AVDD

42 43 44

45 46 47

48 49 50 51

52 53

54 55 56 57 58 59

ANALOG_G

STV2/ROUT2P2/GPO[1]/ROUT1

HVDDSTV1/ROUT3CKV/ROUT4

FRP/ROUT5HGND

LD(OEV)/ROUT6HVDD

P1/GPO[0]/ROUT0

VCOM/ROUT7

DAC_GND

HGNDP4/GPO[3]/GOUT1

DA

C_V

DD

OE

H/G

OU

T2

HG

ND

ST

H2/

GO

UT

3S

TH

1/G

OU

T4

HV

DD

CP

H1

/GO

UT

5

P3/GPO[2]/GOUT0

DAC_REFBANALOG_R

96959493929190898887868584838281807978777675747372

26 RIN427 RIN328 RIN229 RIN130 RIN031 VCC32 ICLK1

OPTIONS[2] 71

OPTIONS[1] 70

GND 69

OPTIONS[0] 68

VCC 67

FB3/HSYNC2 66

VCCA 65

121

GP

O[6

]/RT

S1

122

GP

O[7

]/RT

S2

123

HV

DD

124

OC

LK

125

HG

ND

126

OD

E

127

GP

O[4

]/PW

M1/

PW

M3

128

GP

O[5

]/PW

M2/

PW

M4

GIN

[5]/O

SD

VS

39G

IN[6

]/OS

DC

LK38

GIN

[7]

37V

CC

36O

SC

I35

OS

CO

34G

ND

33

Analog VDD(3.3V)

Digital VCC(3.3V)

I/O VDD(3.3V/5.0V)

Ground

Figure 5-1 Pin configuration (LQFP-128)


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Table 5-1 BIT1611B PIN Define Pin # Pin Name Pin Type Function Description

1 AVDD AVDD AFE Power (3.3V) 2 AIN11 AIN Analog Input Source 1 3 AGND AGND AFE Ground 4 AIN12 AIN Analog Input Source 2 5 AVDD AVDD AFE Power (3.3V) 6 REFT1 AOUT Reference voltage 1 Output for ADC1 7 REFB1 AOUT Reference voltage 2 Output for ADC1 8 AGND AGND AFE Ground 9 AOUT11 AOUT AFE Analog Output for ADC 1

10 AVDD AVDD AFE Power (3.3V) 11 AIN21 AIN Analog Input Source 3 12 AGND AGND AFE Ground 13 AIN22 AIN Analog Input Source 4 14 AVDD AVDD AFE Power (3.3V) 15 REFT2 AOUT Reference voltage 1 Output for ADC2 16 REFB2 AOUT Reference voltage 2 Output for ADC2 17 AGND AGND AFE Ground 18 AOUT2 AOUT AFE Analog Output For ADC 2 19 AVDD AVDD AFE Power (3.3V) 20 TEST I Test Input 21 AGND AGND AFE Ground 22 GND G33 Ground of (3.3V) 23 RIN7 I R-Port[7] Data Input Pull-Down24 RIN6 I R-Port[6] Data Input Pull-Down25 RIN5 I R-Port[5] Data Input Pull-Down26 RIN4 I R-Port[4] Data Input Pull-Down27 RIN3 I R-Port[3] Data Input Pull-Down28 RIN2 I R-Port[2] Data Input Pull-Down29 RIN1 I R-Port[1] Data Input Pull-Down30 RIN0 I R-Port[0] Data Input Pull-Down31 VCC P33 3.3V Power 32 ICLK1 I Clock 1 Input 33 GND I Ground of (3.3V) 34 OSCO I Oscillator Output 35 OSCI I Oscillator Input 36 VCC P33 3.3V Power 37 GIN7 I G-Port[7] Data Input Pull-Down38 GIN6 I/O G-Port[6] Data Input / External OSD CLK Pull-Down39 GIN5 I/O G-Port[5] Data Input / External OSD VSYNC Pull-Down40 GIN4 I/O G-Port[4] Data Input / External OSD HSYNC Pull-Down41 GIN3 I G-Port[3] Data Input / External OSD Blank Pull-Down42 GIN2 I G-Port[2] Data Input / External OSD B Pull-Down43 GIN1 I G-Port[1] Data Input / External OSD G Pull-Down


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44 GIN0 I G-Port[0] Data Input / External OSD R Pull-Down45 GND G33 Ground of (3.3V) 46 ICLK2 I Clock 2 Input 47 VCC P33 3.3V Power 48 VSYNC1 I Vsync 1 Input Pull-Down49 HSYNC1 I Hsync 1 Input Pull-Down50 BIN7 I B-Port[7] Data Input / GPI[7] Pull-Down51 BIN6 I B-Port[6] Data Input / GPI[6] Pull-Down52 BIN5 I B-Port[5] Data Input / GPI[5] Pull-Down53 BIN4 I B-Port[4] Data Input / GPI[4] Pull-Down54 GND G33 Ground of (3.3V) 55 BIN3 I B-Port[3] Data Input / GPI[3] Pull-Down56 BIN2 I B-Port[2] Data Input / GPI[2] Pull-Down57 BIN1 I B-Port[1] Data Input / GPI[1] / External TCON_UD Pull-Down58 BIN0 I B-Port[0] Data Input / GPI[0] / External TCON_RL Pull-Down59 VCC P33 3.3V Power 60 IR I IR Remote Control Input Pull-Down61 INT O Interrupt Output 62 GND G33 Ground of (3.3V) 63 RESET# I System Reset (Active Low) Pull-Up 64 GNDA AG33 PLL Ground 65 VCCA AP33 PLL Power Supply (3.3) 66 HSYNC2 I HSYCN2 Input / PWM3 Feedback Pull-Down67 VCC P33 3.3V Power 68 OPTIONS0 I/O Interface Control Pin 0 69 GND G33 Ground of (3.3V) 70 OPTIONS1 I/O Interface Control Pin 1 71 OPTIONS2 I/O Interface Control Pin 2 /GPI[8] /SPI_SCL 72 VCC P33 3.3V Power 73 OPTIONS3 I/O Interface Control Pin 3 /GPI[9] /SPI_SDA 74 OPTIONS4 I/O Interface Control Pin 4 /GPI10] /SPI_CS 75 OPTIONS5 I Interface Control Pin 5 Pull-Up 76 VSYNC2 I VSYNC2 Input / PWM4 Feedback Pull-Down77 GND G33 Ground of (3.3V) 78 ROUT0 O R-Data Output Port[0] / GPO[0] / Power_P1 79 HGND G50 5.0/3.3V Ground 80 ROUT1 O R-Data Output Port[1] / GPO[1] / Power_P2 81 ROUT2 O R-Data Output Port[2] / STV2 82 HVDD P50 5.0/3.3V Power (I/O port) 83 ROUT3 O R-Data Output Port[3] / STV1 84 ROUT4 O R-Data Output Port[4] / CKV 85 HGND G50 5.0/3.3V Ground 86 ROUT5 O R-Data Output Port[5] / FRP 87 ROUT6 O R-Data Output Port[6] / LD 88 HVDD P50 5.0/3.3V Power (I/O port) 89 ROUT7 O R-Data Output Port[7] / VCOM 90 GOUT0 O G-Data Output Port[0] / GPO[2] / Power_P3


May 16, 2007



91 HGND G50 5.0/3.3V Ground 92 GOUT1 O G-Data Output Port[1] / GPO[3] / Power_P4 93 DAC_GND AG50 DAC Ground (5.0V) 94 DAC_REFB AG50 DAC Reference Bottom Voltage 95 AROUT AOUT Analog R Data Output 96 AGOUT AOUT Analog G Data Output 97 ABOUT AOUT Analog B Data Output 98 DAC_REFT AP50 DAC Reference Top Voltage 99 DAC_VDD AP50 DAC Power Supply (5.0V)

100 GOUT2 O G-Data Output Port[2] / OEH 101 HGND G50 5.0/3.3V Ground 102 GOUT3 O G-Data Output Port[3] / STH2 103 GOUT4 O G-Data Output Port[4] / STH1 104 HVDD P50 5.0/3.3V Power (I/O port) 105 GOUT5 O G-Data Output Port[5] / CPH1 106 HGND G50 5.0/3.3V Ground 107 GOUT6 O G-Data Output Port[6] / CPH2 108 HVDD P50 5.0/3.3V Power (I/O port) 109 GOUT7 O G-Data Output Port[7] / CPH3 110 BOUT0 O B-Data Output Port[0] / TCON_RL /Power_P5 111 BOUT1 O B-Data Output Port[1] / TCON_UD /Power_P6 112 HGND G50 5.0/3.3V Ground 113 BOUT2 O B-Data Output Port[2] / TCON_Q2H 114 BOUT3 O B-Data Output Port[3] / TCON_GPO[0] 115 HVDD P50 5.0/3.3V Power (I/O port) 116 BOUT4 O B-Data Output Port[4] / TCON_GPO[1] 117 BOUT5 O B-Data Output Port[5] / TCON_GPO[2] 118 HGND G50 5.0/3.3V Ground 119 BOUT6 O B-Data Output Port[6] / Power_P5 120 BOUT7 O B-Data Output Port[7] / Power_P6 121 RTS1 O Special Function Output 1 / GPO[6] 122 RTS2 O Special Function Output 2 / GPO[7] 123 HVDD P50 5.0/3.3V Power (I/O port) 124 OCLK O Output Clock 125 HGND G50 5.0/3.3V Ground 126 ODE O Output Data Enable 127 PWM1 O PWM1 output / GPO[4] /PWM3 Output 128 PWM2 O PWM2 output / GPO[5] /PWM4 Output


May 16, 2007



6 Application Examples

BIT1611B

Analog Video

Source

Analog

TFTPanel

TFT TCON Signals

Analog RGB Output

ExternalOSD

Options

MCU

Smaller than 512x512

BiTEKbus or Two-Wire

Digital Video Source

CVBS x 4 orS-Video x 2 orCVBS x 2 + S-Video

ITU656 / ITU656-LikeRGB888/RGB565

Serial-RGB MUX

Internal Mux

Slave Mode for Analog-TFT Panel

Figure 6-1 Application 1

BIT1611B

Analog Video

Source

Analog

TFTPanel

Digital TFT Panel Timing Signal

Digital RGB Output 8:8:8

ExternalOSD

Options

MCU


BiTEKbus or Two-Wire



MUX

Internal Mux

Slave Mode for Digital-TFT Panel


Serial-RGB

Digital



May 16, 2007



BIT1611B

Analog Video

Source

Analog

TFTPanel

TFT TCON Signal


ExternalOSD

OptionsInternal Mux

Master Mode for Analog-TFT PanelCVBS x 4 orS-Video x 2 orCVBS x 2 + S-Video

EEPROM



MUX

Analog


Serial-RGB

External Pin Setting

24Cxx EEPROM


BIT1611B

Analog Video

Source

Analog

TFTPanel

Digital TFT Panel Timing Signal


ExternalOSD

Options

EEPROM




MUX

Internal Mux

Master Mode for Digital-TFT Panel

External Pin Setting

24Cxx EEPROM


Serial-RGB

Digital



May 16, 2007



7 Function Description

7-1 Version Control BIT1611B provides two registers to save the information of the number of the version of the hardware and the soft

ware. Please refer to the Table 7-1 for the details:

Table 7-1 Version Control Register Mnemonic Address R/W bit Description Default

[1:0] Product version [4:2] Product Number R_HW_VER 0x000 R 8 [7:5] Product Group

0xC6

R_SW_VER 0x001 RW 8 Software Version Control 0x00

7-2 Interrupt Function BIT1611B Interrupt Function provides INT Pin (Pin61) to be the Interrupt Trigger Output. Interrupt can be set as a

Edge or Level trigger through setting the registers. It can be set as Active High or Active Low when it is level trigger. It can be set as a Falling Edge or Rising Edge trigger when it is a edge triggered interrupt. The Interrupt is a Three Layers configuration (FLAG, MASK and ACK) as described in Figure 7-1. BIT1611B provides 8 Interrupt Sources. Please refer to Table 7-2, Table 7-3 and Table 7-4 for the details:

Table 7-2 Interrupt Source Interrupt Source bit Function

R_NOSIG_SEL(0x101[3]=0 Active when input HSYNC has some changes in 2047 XCLKs

R_HASSIG_FLAG 0R_NOSIG_SEL(0x101[3]=1

Active when Video Decoder Lock select source (see Table 7-4)

R_NOSIG_SEL(0x101[3]=0 Active when input HSYNC has no change in 2047 XCLKs

R_NOSIG_FLAG 1R_NOSIG_SEL(0x101[3]=1

Active when Video Decoder Un-Lock select source(see Table 7-4)

R_MODE_FLAG 2 Active when input VSYNC variation larger than the setting of R_MODECHG_MRG

Active when selected VSYNC falling edge occurs. R_INT_VSSEL(0x005[6] = 0 VSYNC from input Vsync source R_VSYNC_FLAG 3R_INT_VSSEL (0x005[6])= 1 VSYNC from output Vsync R_INT_ERRSEL(0x005[7] ) =0 Active when timer1 overflow

R_ERROR1_FLAG 4R_INT_ERRSEL(0x005[7] ) =1 Active when Line Buffer error type 1 occurs. R_INT_ERRSEL(0x005[7]) = 0 Active when timer2 overflow

R_ERROR2_FLAG 5R_INT_ERRSEL(0x005[7] ) =1 Active when Line Buffer error type 2 occurs.

R_IR_FLAG 6 Active when IR Remote Control Detection is ready. R_KEY_FLAG 7 Active when GPI (General Purpose Input) status changes.

Table 7-3 Interrupt Register Mnemonic Address R/W bit Description Default

Interrupt Flag: 0: Nothing. R_INT_FLAG 0x002 R 81: Interrupt event occurs.

-


May 16, 2007



Interrupt MASK: 0: Interrupt Mask Off (Enable interrupt). R_INT_MASK 0x003 RW 81: Interrupt Mask On (Disable interrupt).

0x00

Interrupt ACK: 0: Clear Interrupt Flag and Disable Interrupt. R_INT_ACK 0x004 RW 81: Enable Interrupt.

0x00

Interrupt TYPE: 0: Edge Type. R_INT_TYPE 0x005[0] RW 11: Level Type.

0

Interrupt Polarity: 0: High level active (Level Type) 0: Rising edge active (Edge type) 1: Low level active (Level Type)

R_POL_INT 0x005[1] RW 1

1: Falling edge active (Edge type)

0

Line buffer error detection select 0: ODD Field. R_ERROR_TYPE 0x005[2] RW 11: EVEN Field.

0

Interrupt vector[3] source select 0: Input source Vsync. R_INT_VSSEL 0x005[6] RW 11: Output Vsync.

1

Interrupt vector[4] and vector[5] source select 0: From timer overflow R_INT_ERRSEL 0x005[7] RW 11: From line buffer error

1

Table 7-4 Video Decoder lock source for interrupt select Mnemonic Address R/W bit Description Default

Video Decoder Lock source for interrupt select 00: from STD_READY & SYNC_READY 01: from STD_READY 10: from SYNC_READY

R_HLCK_SEL 0x130[7:6] RW 2

11: from HLCK

11

FF InterruptControl

R_INT_MASKR_INT_ACK R_INT_FLAG

InterruptSource

INT

Figure 7-1 Interrupt Function Block


May 16, 2007



7-3 Double Buffer BIT1611B provides Double Buffer Register for user to do Parallel updating. The double buffer is provided for

the re-size factor (0x5D~0x5F) and Display window setup (0x56~0x59). Please refer to the Figure 7-2 and Table 7-5.

Figure 7-2 Double Buffer Function

Table 7-5 Double Buffer Register Mnemonic Address R/W bits Description Default

Double Buffer Load Enable 0: Nothing R_LOAD_EN 0x005[4] RW 11: Load

0

Double Buffer Register Update Type 0: Immediately R_LOAD_TYPE 0x005[5] RW 11: Control by R_LOAD_EN

0

7-4 Pad Type Setup BIT1611B provides some pads with Multi-Function, these pins and their functions are described in Table 7-6. Table

7-7 provides the information of the Tri-state operated output pins and the setting of the relative registers.

Table 7-6 Multi-Function Pads PIN Type Multi-Function Control Register

G-Port[0] data Input R_EXTOSD_EN (0x162[0])=0GIN0 (44) I

External OSD R Input R_EXTOSD_EN (0x162[0])=1G-Port[1] data Input R_EXTOSD_EN (0x162[0])=0

GIN1 (43) I External OSD G Input R_EXTOSD_EN (0x162[0])=1G-Port[2] data Input R_EXTOSD_EN (0x162[0])=0

GIN2 (42) I External OSD B Input R_EXTOSD_EN (0x162[0])=1G-Port[3] data Input R_EXTOSD_EN (0x162[0])=0

GIN3 (41) I External OSD Blank Input R_EXTOSD_EN (0x162[0])=1I G-Port[4] Data Input R_EXTOSD_EN (0x162[0])=0

GIN4 (40) I/O O External OSD HSYNC Output R_EXTOSD_EN (0x162[0])=1I G-Port[5] Data Input R_EXTOSD_EN (0x162[0])=0

GIN5 (39) I/O O External OSD VSYNC Output R_EXTOSD_EN (0x162[0])=1


May 16, 2007



I G-Port[6] Data Input R_EXTOSD_EN (0x162[0])=0GIN6 (38) I/O

O External OSD Clock Output R_EXTOSD_EN (0x162[0])=1B-Port[0] Data Input External TCON type select 1 R_EXTPIN (0x0C9[7]) = 1 BIN0 (58) I GPI[0] R_KEY0_TYPE (0xC4[1:0]) B-Port[1] Data Input External TCON type select 2 R_EXTPIN (0x0C9[7]) = 1 BIN1 (57) I GPI[1] R_KEY1_TYPE (0xC4[3:2]) B-Port[2] Data Input

BIN2 (56) I GPI[2] R_KEY2_TYPE (0xC4[5:4]) B-Port[3] Data Input





BIN7 (50) I GPI[7] R_KEY7_TYPE (0xC5[7:6]) HSYNC Source 2 Input

HYSNC2(66) I PWM3 Feedback Input VSYNC Source 2 Input

VSYNC2(76) I PWM4 Feedback Input R Data [0] Output R_GPO_SEL (0x08[0])=0 GPO [0] Output R_GPO_SEL (0x08[0])=1

ROUT0 (78) O Power_Phase1 Output

R_GPO_SEL (0x08[0])=1 & R_POWER_SEL(0xBC[0])=1

R Data [1] Output R_GPO_SEL (0x08[1])=0 GPO [1] Output R_GPO_SEL (0x08[1])=1

ROUT1 (80) O Power_Phase2 Output

R_GPO_SEL (0x08[1])=1 & R_POWER_SEL(0x0DA[1])=1

R Data [2] Output R_TCON_EN (0x037[7])=0 ROUT2 (81) I/O

TCON STV1 Output/Input R_TCON_EN (0x037[7])=1 R Data [3] Output R_TCON_EN (0x037[7])=0

ROUT3 (83) I/O TCON STV2 Output/Input R_TCON_EN (0x037[7])=1 R Data [4] Output R_TCON_EN (0x037[7])=0

ROUT4 (84) O TCON CKV Output R_TCON_EN (0x037[7])=1 R Data [5] Output R_TCON_EN (0x037[7])=0

ROUT5 (86) O TCON FRP Output R_TCON_EN (0x037[7])=1 R Data [6] Output R_TCON_EN (0x037[7])=0

ROUT6 (87) O TCON LD Output R_TCON_EN (0x037[7])=1 R Data [7] Output R_TCON_EN (0x037[7])=0

ROUT7 (89) O TCON VCOM Output R_TCON_EN (0x037[7])=1 G Data [0] Output R_GPO_SEL (0x08[2])=0 GPO [2] Output R_GPO_SEL (0x08[2])=1

GOUT0 (90) O Power_Phase3 Output



May 16, 2007



G Data [1] Output R_GPO_SEL (0x08[3])=0 GPO [3] Output R_GPO_SEL (0x08[3])=1

GOUT1 (92) O Power_Phase4 Output


G Data [2] Output R_TCON_EN (0x037[7])=0 GOUT2 (100) O

TCON OEH Output R_TCON_EN (0x037[7])=1 G Data [3] Output R_TCON_EN (0x037[7])=0

GOUT3 (102) I/O TCON STH1 Input / Output R_TCON_EN (0x037[7])=1 G Data [4] Output R_TCON_EN (0x037[7])=0

GOUT4 (103) I/O TCON STH2 Input / Output R_TCON_EN (0x037[7])=1 G Data [5] Output R_TCON_EN (0x037[7])=0

GOUT5 (105) O TCON CPH1 Output R_TCON_EN (0x037[7])=1 G Data [6] Output R_TCON_EN (0x037[7])=0

GOUT6 (107) O TCON CPH2 Output R_TCON_EN (0x037[7])=1 G Data [7] Output R_TCON_EN (0x037[7])=0

GOUT7 (109) O TCON CPH3 Output R_TCON_EN (0x037[7])=1 B Data [0] Output R_TCON_EN (0x037[7])=0 TCON_RL R_TCON_EN (0x037[7])=1

BOUT0 (110) O Power_Phase5 Output

R_TCON_EN (0x037[7])=0 & R_POWER_SEL(0x0DA[4])=1

B Data [1] Output R_TCON_EN (0x037[7])=0 TCON_UD R_TCON_EN (0x037[7])=1



B Data [2] Output R_TCON_EN (0x037[7])=0 BOUT2 (113) O

TCON GPO [0] R_TCON_EN (0x037[7])=1 B Data [3] Output R_TCON_EN (0x037[7])=0

BOUT3 (114) O TCON GPO [1] R_TCON_EN (0x037[7])=1 B Data [4] Output R_TCON_EN (0x037[7])=0

BOUT4 (116) O Q2H-BAR R_TCON_EN (0x037[7])=1 B Data [5] Output R_TCON_EN (0x037[7])=0 CKV_BAR R_TCON_EN (0x037[7])=1



B Data [6] Output R_TCON_EN (0x037[7])=0 LD_BAR R_TCON_EN (0x037[7])=1



B Data [7] Output R_TCON_EN (0x037[7])=0 BOUT7 (120) O

OEH_BAR R_TCON_EN (0x037[7])=1 PWM1 Output R_GPO_SEL (0x08[4])=0 GPO [4] Output R_GPO_SEL (0x08[4])=1

PWM1 (127) O PWM3 Output

R_GPO_SEL (0x08[4])=0 & R_PWM3_SEL(0xD1[2])=1

PWM2 Output R_GPO_SEL (0x08[5])=0 GPO [5] Output R_GPO_SEL (0x08[5])=1 PWM2 (128) O PWM4 Output R_GPO_SEL (0x08[5])=0 &


May 16, 2007



Table 7-7 Output Tri-State Control Register Mnemonic Address R/W bit Description Default

R_ROUT_TRI 0x007[0] RW 1 ROUT Port Tri-State Enable 1 R_GOUT_TRI 0x007[1] RW 1 GOUT Port Tri-State Enable 1 R_BOUT_TRI 0x007[2] RW 1 BOUT Port Tri-State Enable 1 R_OCLK_TRI 0x007[3] RW 1 OCLK pin Tri-State Enable 1 R_ODE_TRI 0x007[4] RW 1 ODE pin Tri-State Enable 1

INT Pin Tri-State Enable R_INT_TRI 0x007[5] RW 1

1 Tri-State, 0 Normal 1

7-5 GPO (General Purpose Output) Function BIT1611B provides 8 GPO Register control outputs. It may be programmed as: Status, High Level, Low Level

and Tri-state. The relative register settings please refer to Table 7-8 and Table 7-9.

Table 7-8 General Purpose Output Register

Mnemonic Address R/W Bits Description DefaultGPO Port Enable: 0: Disable. R_GPO_SEL 0x008[5:0] RW 61: Enable.

0x00

GPO Port Type: 0: Normal. R_GPO_TYPE 0x009[5:0] RW 61: Tri-State.

0x3F

GPO Port Value: 0: Low Level. R_GPO_REG 0x00A[7:0] RW 81: High Level.

0x00

GPO Output Source Select 0: From GPO Register R_GPO_STATUS 0x101[2] RW 11: From Video decoder status

0

Video decoder status output select 0: Normal Status R_VD_MON 0x103[7] RW 11: Testing Only

0


May 16, 2007



Table 7-9 General Purpose Output Pads Setup Table GPO Pin Name/ No. Output Pin Register recommended setting

GPO[0] R_GPO_SEL[0] = 1,R_GPO_STATUS(0x101[2])=0

R_FIDT R_GPO_SEL[0] = 1 R_GPO_STATUS(0x101[2])=1,R_VD_MON(0x103[7])=0

VD_VSYNC (For test only)

ROUT[0](78)

R_GPO_SEL[0] = 1 R_GPO_STATUS(0x101[2])=1,R_VD_MON(0x103[7])=1


R_STD_READY R_GPO_SEL[1] = 1 R_GPO_STATUS(0x101[2])=1,R_VD_MON(0x103[7])=0

VD_HSYNC (For test only)

ROUT[1](80)



R_SYNC_READY R_GPO_SEL[2] = 1 R_GPO_STATUS(0x101[2])=1,R_VD_MON(0x103[7])=0

VD_HC (For test only)

GOUT[0](90)



R_HLCK R_GPO_SEL[3] = 1 R_GPO_STATUS(0x101[2])=1,R_VD_MON(0x103[7])=0

VD_HSY (For test only)

GOUT[1](92)


GPO[4] PWM1(127) R_GPO_SEL[4] = 1 GPO[5] PWM2(128) R_GPO_SEL[5] = 1 GPO[6] RTS1(121) R_RTS1_SEL[2:0] = 110 GPO[7] RTS2(122) R_RTS2_SEL[2:0] = 110


May 16, 2007



MUXPad (127)

01

R_GPO_TYPE(0x009[4])

R_GPO_REG(0x00A[4])

PWM1 Signal

R_GPO_SEL(0x008[4])

MUX Pad (128)01

R_GPO_TYPE(0x009[5])

R_GPO_REG(0x00A[5])

PWM2 Signal

R_GPO_SEL(0x008[5])

MUX Pad(78,80)0

1

R_GPO_TYPE(0x009[1:0])

R_GPO_REG(0x00A[1:0]) or Video Decoder Status

Data ROUT[1:0]

R_GPO_SEL(0x008[1:0])

R_ROUT_TRI(0x007[0])

MUX Pad(90,92)0

1

R_GPO_TYPE(0x009[3:2])

R_GPO_REG(0x00A[3:2])

Or Video Decoder Status

Data GOUT[1:0]

R_GPO_SEL(0x008[3:2])

R_GOUT_TRI(0x007[1])

MUXPad (121)

000001

110R_GPO_REG(0x00A[6])

R_RST1_SEL(0x026[2:0])

MUXPad (122)

000001

110R_GPO_REG(0x00A[7])

R_RST2_SEL(0x026[6:4])

111

111

Figure 7-3 GPO function


May 16, 2007



7-6 System Enable and Reset BIT1611B provides Hardware Reset and Software Reset functions.

7.6.1 Hardware Reset BIT1611B may be reset to the Power-On status through Reset PIN (Pin 63) with a logic low signal, which is

larger than 16 XCLK cycles time. Please refer to Figure 7-4 for the relative timing waveform.

Reset Pulse must be longer than 16 XCLK

cycles

RESET PIN

Figure 7-4 Hardware Reset Waveform

7.6.2 Software Reset BIT1611B may reset the different functional blocks through setting the different registers. Please refer to the

Table 7-10.

Table 7-10 Soft Reset Register Mnemonic Address R/W bit Description Default

R_SYNCDET_EN 0x00B[0] RW 1 SYNCDET function soft reset. 1 R_PWM1_EN 0x00B[1] RW 1 PWM1 function soft reset. 1 R_PWM2_EN 0x00B[2] RW 1 PWM2 function soft reset. 1 R_PWM3_EN 0x00B[3] RW 1 PWM3 function soft reset. 1 R_PWM4_EN 0x00B[4] RW 1 PWM4 function soft reset. 1 R_SAMPLE_EN 0x00B[5] RW 1 SAMPLE function soft reset. 1 R_SRST_VP 0x00C[0] RW 1 Video Process function soft reset. 1 R_SRST_OUT 0x00C[1] RW 1 Output function soft reset 1 R_SRST_OSD 0x00C[2] RW 1 OSD function soft reset. 1 R_SRST_CHROMA 0x00C[3] RW 1 Chroma Decoder function soft reset. 1 R_SRST_SYNC 0x00C[4] RW 1 Sync Decoder function soft reset. 1 R_SRST_CLOCK 0x00C[5] RW 1 Clock control function soft reset 1 R_SRST_AGC 0x00C[6] RW 1 AGC function soft reset. 1 R_SRST_COMB 0x00C[7] RW 1 Reserve (set to 1) 1


May 16, 2007



7-7 Built-in DAC Building three groups of DAC by offering Analog R , G , B to export in BIT1611B, its is relevant please consult

Table 7-12 to establish Register:

Table 7-11 DAC Register

Mnemonic Address R/W bit Description DefaultDAC Clock Phase Select 00: Phase 1 01: Phase 2 10: Phase 3

R_DACCLK_MODE 0x00E[3:2] RW 2

11: Phase 4

00

DAC LCLK Source polarity 0: Normal R_DAC_POL 0x00E[4] RW 1

1: Invert

0

DAC Clock polarity 0: Normal R_DAC_SEL 0x00E[5] RW 1

1: Invert

0

DAC Noise Reduce 0: Disable R_DAC_DG 0x00E[6] RW 1

1: Enable

1

DAC Enable 0: Disable R_DAC_EN 0x00E[7] RW 1

1: Enable

0


May 16, 2007



7-8 Clock Domain Systems There are 4 clock domains in BIT1611B:

1. PCLK Domain: Source Clock 2. LCLK Domain: Panel Clock 3. XCLK Domain: System Clock 4. MCLK Domain: Image Clock

The relative register settings please refer to Table 7-12 and Figure 7-5.

NOTEThe frequency of XCLK Domain should be lower than LCLK Domain.

Table 7-12 Clock Domain System Register Mnemonic Address R/W bit Description Default

LCLK Domain Enable: 0: Disable. R_LCLK_EN 0x00F[0] RW 1

1: Enable.

1

LCLK Domain Polarity: 0: Normal. R_POL_LCLK 0x00F[1] RW 1

1: Invert.

0

LCLK Domain Clock Source Select: 00: ICLK1. 01: ICLK2. 10: PLLCLK

R_LCLK_SEL 0x00F[3:2] RW 2

11: OSCCLK

11

PCLK Domain Enable: 0: Disable. R_PCLK_EN 0x00F[4] RW 1

1: Enable.

1

PCLK Domain Polarity: 0: Normal. R_POL_PCLK 0x00F[5] RW 1

1: Invert.

0

PCLK Domain Clock Source Select: 0: ICLK1. R_ PCLK_SEL 0x00F[6] RW 1

1: ICLK2.

1

XCLK Domain Clock Source Select: 00: OSCCLK. (OSCCLK=Oscillator Frequency)) 01: OSCCLK / 2. 10: OSCCLK / 4.

R_XCLK_SEL 0x00E[1:0] RW 2

11: OSCCLK / 8.

00

MCLK Domain Clock Source Select R_MCLK_MODE 0x050[7:5] RW 3

MCLK = PCLK / (R_MCLK_MODE+1) 001

Video Decoder Path Clock Source Select 0: Normal Path (ICLK1 or ICLK2) R_VD_CLK1 0x101[6] RW 1

1: Video Decoder Clock (27MHz)

0

Video Decoder Path Clock Source Select 0: Normal Path (ICLK1ICLK2PLLCLKOSCCLK) R_VD_CLK2 0x101[7] RW 11: Video Decoder Clock (27MHz)

0


May 16, 2007



OSC

PLL

MUX

MUX

MUX

R_PCLK_SEL

R_LCLK_SEL

R_PCLK_EN

R_LCLK_EN

R_POL_PCLK

0

1

10

00

011011

ICLK1

ICLK2

PCLK

LCLK

XCLK

MUX

R_POL_LCLK

0

1

DIV MUX11100100

R_XCLK_SEL

DIVMCLK

R_MCLK_MODER_VD_CLK2

R_VD_CLK1

Internal VD Clock(27Mhz)

MUX

MUX

MUX

R_PCLK_SEL

10

Internal VD Clock(135Mhz

)

MUX

R_LCLK_SEL[0]

10

0

1

OSCCLK

PLLCLK

Figure 7-5 Clock Select Function

7-9 Panel Timing Setup The output signal timing to panel can be set by BIT1611B according to EVEN or ODD field. Refer to Table 7-13.

The related timing definition please refers to Figure 7-6. Table 7-13 Panel Timing Setup register

Mnemonic Address R/W bit Description Default

R_OS_XP 0x013[5:4], 0x010[7:0]

RW 10 HSYNC Pulse Width 0x010

R_OS_XS 0x013[3:2], 0x011[7:0]

RW 10 Active Window Horizontal Start Position 0x020

R_OS_XW 0x013[1:0], 0x012[7:0]

RW 10 Active Window Horizontal End Position 0x200

R_OSE_XT_M0 0x016[5:4], 0x014[7:0]

RW 10Horizontal Total Length for EVEN Field on Mode 0

0x2C4

R_OSO_XT_M0 0x016[1:0], 0x015[7:0]

RW 10Horizontal Total Length for ODD Field on Mode 0

0x2C4

R_OSE_XT_M1 0x01C[5:4], 0x01A[7:0]

RW 10Horizontal Total Length for EVEN Field on Mode 1

0x23E

R_OSO_XT_M1 0x01C[1:0], 0x01B[7:0]

RW 10Horizontal Total Length for ODD Field on Mode 1

0x23E

R_OS_YP 0x020[7:0] RW 8 VSYNC Pulse Width 0x002R_OS_YS 0x021[7:0] RW 8 Active Window Vertical Start Position 0x005R_OS_YW 0x024[1], 0x022[7:0] RW 9 Active Window Vertical End Position 0x0EFR_OS_YT 0x024[0], 0x023[7:0] RW 9 Vertical Total Length 0x0FC


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Panel Active Window

Blank Range

(0,0)

R_OS_XS

R_OS_XW

R_OSE_XTR_OSO_XT

R_OS_XP

R_OS

_YS

R_OS

_YW

R_OS

_YT

R_OS

_YP

HSYNC Output

VSYNC Output

Figure 7-6 Panel Timing Setup

7-10 Output Data Path The output data bus can be inverted, rotated and swapped. Refer to Table 7-14 and Figure 7-7.

Table 7-14 Output Data Path Register

Mnemonic Address R/W bit Description Default

R_SWAPE_ORB 0x024[2] RW 1R data output Swap with B data output on EVEN Field 0: swap disable; 1: swap enable

0

R_SWAPE_ORG 0x024[3] RW 1R data output Swap with G data output on EVEN Field 0: swap disable; 1: swap enable

0

R_SWAPE_OGB 0x024[4] RW 1G data output Swap with B data output on EVEN Field 0: swap disable; 1: swap enable

0

R_SWAPO_ORB 0x024[5] RW 1R data output Swap with B data output on ODD Field 0: swap disable; 1: swap enable

0

R_SWAPO_ORG 0x024[6] RW 1R data output Swap with G data output on ODD Field 0: swap disable; 1: swap enable

0

R_SWAPO_OGB 0x024[7] RW 1G data output Swap with B data output on ODD Field 0: swap disable; 1: swap enable

0

R_POL_ROUT 0x025[0] RW 1 R Data output Polarity 0:normal 1:invert 0 R_POL_GOUT 0x025[1] RW 1 G Data output Polarity 0:normal 1:invert 0 R_POL_BOUT 0x025[2] RW 1 B Data output Polarity 0:normal 1:invert 0 R_ROL_ROUT 0x025[4] RW 1 R Data Rotate 0:disable 1:enable 0 R_ROL_GOUT 0x025[5] RW 1 G Data Rotate 0:disable 1:enable 0 R_ROL_BOUT 0x025[6] RW 1 B Data Rotate 0:disable 1:enable 0 R_OCLK_POL 0x025[7] RW 1 Output Clock Polarity 0:normal 1:invert 0


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Figure 7-7 Output Data Path Select

7-11 Serial RGB Output Mode The output format of BIT1611B can be a serial RGB signal. The serial RGB output format can be defined to any

one of ROUT, GOUT and BOUT ports. Please refer to Table 7-15.

Table 7-15 Serial RGB Output Register Mnemonic Address R/W Bits Description Default

Serial-RGB format output enable 0: Disable R_SERIAL_OUT 0x025[3] RW 1

1: Enable

0

7-12 Special Output Setup RTS1 (pin 121) and RTS2 (pin 122) are 2 special outputs of BIT1611B. Their functions can be decided by special

registers, please refer to Table 7-16.

Table 7-16 Special Output Pads Setup Register Mnemonic Address R/W bit Description Default

000: Output HSYNC Signal 001: Output HREF Signal 010: Output VSYNC Signal 011: Output VREF Signal 100: Output EVEN/ODD Signal 101: PWM3 110: General Output Port Bit [6] (R_GPO_REG[6])

R_RTS1_SEL 0x26[2:0] RW 3

111: Tri-State Output

111

000: Output HSYNC Signal 001: Output HREF Signal 010: Output VSYNC Signal 011: Output VREF Signal 100: Output EVEN/ODD Signal

R_RTS2_SEL 0x26[6:4] RW 3

101: PWM4

111


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110: General Output Port Bit [7] (R_GPO_REG[7]) 111: Tri-State Output

7-13 Special Timing Adjustment BIT1611B provides 2 timing adjustment modes to fit the various requirements of panels.

Please refer to Table 7-17.

7.13.1 Synchronization Timing Output Vsync signal will be synchronized with input Vsync signal by this mode.

Input VSYNC

Output VSYNC

Figure 7-8 Synchronization Timing

7.13.2 Two-Fields Synchronization Timing

Output Vsync signal will be decided by even/odd field Vsync and R_OS_YT (0x024[0], 0x023[7:0]).

Figure 7-9 Two-Fields Synchronization Timing

Table 7-17 Special Timing Adjust Register

Mnemonic Address R/W bit Description DefaultSync. With input VSYNC enable 0: Two-Fields Synchronization Mode R_SYNCO_EN 0x013[6] RW 1 1: Synchronization Mode

1

Two-Field Synchronization Mode Select 0: EVEN Field Synchronize R_SYNCO_MODE 0x013[7] RW 1 1: ODD Field Synchronize

0

Minimum Output Lines protect 0: Disable R_PROTECT_MODE 0x026[7] RW 1 1: Enable

1


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7-14 TCON Function BIT1611B has a programmable TCON function inside and that can control the analog panels directly.

Table 7-18 TCON Function Register Mnemonic Address R/W bit Description Default

R_STV_START 0x029[0], 0x027[7:0] RW 9 STV Signal Start 0x002R_STV_END 0x029[1], 0x028[7:0] RW 9 STV Signal End 0x003

VCOM Signal TYPE 00: Always 0 01: Always 1 10: FRP Invert

R_VCOM_TYPE 0x029[3:2] RW 2

11: FRP

11

FRP Output Polarity 0: Normal R_POL_FRP 0x029[4] RW 11: Invert

0

R_STH_START 0x02E[5:4], 0x02A[7:0] RW 10 STH Signal Start 0x01DR_STH_END 0x02E[7:6], 0x02B[7:0] RW 10 STH Signal End 0x020R_CKV_START 0x02E[1:0], 0x02C[7:0] RW 10 CKV Signal Start 0x027R_CKV_END 0x02E[3:2], 0x02D[7:0] RW 10 CKV Signal End 0x051R_LD_START 0x033[5:4], 0x02F[7:0] RW 10 LD Signal Start 0x001R_LD_END 0x033[7:6], 0x030[7:0] RW 10 LD Signal End 0x037R_OEH_START 0x033[1:0], 0x031[7:0] RW 10 OEH Signal Start 0x014R_OEH_END 0x033[3:2], 0x032[7:0] RW 10 OEH Signal End 0x015R_VCOM_SHIFT 0x035[1:0],0x034[7:0] RW 10 VCOM Shift 0x064

Data Bus Control on FRP 00: Disable 01: Follow Shift VCOM 10: Follow FRP

R_BUS_INV 0x035[3:2] RW 2

11: Follow Invert FRP

00

R_POL_OEH 0x036[0] RW 1 OEH Output Polarity 0 R_POL_STH 0x036[1] RW 1 STH Output Polarity 0

STV Output Polarity 0: Normal R_POL_STV 0x036[2] RW 11: Invert

0

R_TCON_GPO 0x036[5:3] RW 3 TCON GPO Register 000 OEH gated with ODE 0: Disable R_OEH_GATE 0x036[6] RW 11: Enable

1

LTPS Mode Select 0: Normal Mode R_LTPS_MODE 0x036[7] RW 11: LTPS TCON Mode

0

STH Output Select 0: STH1 = OUT STH2= IN R_STH_SEL 0x037[0] RW 11: STH1 = IN, STH2 = OUT

0

STV Output Select 0: STV1 = OUT STV2= IN R_STV_SEL 0x037[1] RW 11: STV1 = IN, STV2 = OUT

0

R_TCON_RL 0x037[2] RW 1 TCON R/L Signal 0


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0: Low Level 1: High Level TCON U/D Signal 0: Low Level R_TCON_UD 0x037[3] RW 11: High Lev

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W-DS-0004-A0 BIT1611B