William Stallings Computer Organization and Architecture5th Edition

Chapter 12Reduced InstructionSet Computers精简指令集计算机

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Topics

• Major Advances in Computers 计算机的主要改进• Instruction Execution Characteristics 指令执行的

特点• Use of Large Register File 使用大的寄存器• Compiler-Based Register Optimization 基于编译器的寄存器优化• Reduced Instruction Set Architecture 精简指令集体系结构• RISC Pipelining RISC 流水线• RISC vs. CISC Controversy RISC 和 CISC 的比较

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Major Advances in Computers(1)

• The family concept 系列概念—IBM System/360 1964—DEC PDP-8—Separates architecture from implementation

将体系结构和它的实现分开• Microporgrammed control unit 微程序控制

器—Idea by Wilkes 1951—Produced by IBM S/360 1964

• Cache memory Cache 存储器—IBM S/360 model 85 1969

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Major Advances in Computers(2)

• Solid State RAM 固态存储器—(See memory notes)

• Microprocessors 微处理器—Intel 4004 1971

• Pipelining 流水—Introduces parallelism into fetch execute cycle

• Multiple processors 多处理器

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The Next Step - RISC

• RISC-Reduced Instruction Set Computer RISC 精简指令集计算机• Key features

—Large number of general purpose registers, or use of compiler technology to optimize register use

大量通用寄存器，使用编译技术优化寄存器的使用—Limited and simple instruction set 一个有限简单的指令集—Emphasis on optimising the instruction

pipeline 强调指令流水的优化

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Comparison of processors

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Driving force for CISC （ 1 ）• CISC-Complex Instruction Set Computer CISC －复杂指令集计算机• Why CISC?

—Software costs far exceed hardware costs 软件成本高于硬件成本—Increasingly complex high level languages 越来越复杂的高级语言—Semantic gap : Difference between operations

provided in HLLs and those provided in computer architecture

语义间隙问题： HLLs 提供的操作和计算机体系结构提供的操作不同

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Driving force for CISC （ 2 ）

• to close the gapLeads to: —Large instruction sets 指令集非常大—More addressing modes 更多的寻址方式—Hardware implementations of HLL

statements– e.g. CASE (switch) on VAX

HLL 描述的硬件的实现

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Intention of CISC 复杂指令集体系结构的目的• Ease compiler writing 使编译器的编写更容

易• Improve execution efficiency 提高执行效率

—Complex operations in microcode

因为复杂操作能以微代码实现• Support more complex HLLs 提供更复杂的 HLL 支持

A totally different approach:Simpler architecture

简化体系结构

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Execution Characteristics

• Developments of RISCs were based on the study of instruction execution characteristics

RISC 的开发是基于指令的执行特性—Operations performed 完成的操作

– determine functions to be performed and interaction with memory

决定了 CPU 所要完成的功能及其与存储器的相互作用—Operands used (types and frequencies) 使用的操作数及其类型和频率

– determine memory organization and addressing modes 决定了存储器如何组织存储它们和访问它们用的寻址方式

—Execution sequencing– determines the control and pipeline organization

决定了控制和流水线的组织结构

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Execution Characteristics

• In the remainder of this section, we summarize the results of a number of studies of high-level-language programs. All of the results are based on dynamic measurements.

• Dynamic studies are measured during the execution of the program.

程序的执行中进行的动态测量。• Static measurements merely perform these

counts on the source text of a program.静态测量只是在源程序文本上进行统计，这不能给出很有用的性能信息。

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Operations

Table 4.9 reveal: • Assignment statements predominate

—Movement of data is of high importance 数据的移动重要性

• Preponderance of Conditional statements (IF, LOOP) 条件语句—Sequence control is important 指令集的顺序控制

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Relative Dynamic Frequency

Dynamic Machine Instruction Memory Reference

Occurrence (Weighted) (Weighted) PascalC PascalC PascalC

Assign 45 38 13 13 14 15Loop 5 3 42 32 33 26Call 15 12 31 33 44 45If 29 43 11 21 7 13GoTo - 3 - - - -Other 6 1 3 1 2 1

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Operations

• Procedure call-return is very time consuming

程序的调用花费大量时间• Some HLL instruction lead to many

machine code operations 一些 HLL 指令导致执行大量机器代码

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Operands

• Mainly local scalar variables 主要是局部，标量变量• Optimisation should concentrate on

accessing local variables 优化也应该集中在局部变量的访问

Pascal C AverageInteger constant 16 23 20Scalar variable 58 53 55Array/structure 26 24 25

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Procedure Calls

• Very time consuming 过程调用是编译后的 HLL 程序中最耗时的操作• To implement efficiently, two aspects are significant:

—Depends on number of parameters passed 依赖于传递的参数的数量—Depends on level of nesting 依赖于嵌套深度

• Most programs do not do a lot of calls followed by lots of returns

程序一般不作大量的调用返回• Most variables are local 大部分变量是局部的

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Implications

• Making instruction set architecture close to HLL

使指令集与 HLL 相近 not most effective 不是最有效的 • Best support is given by optimising most

used and most time consuming features 通过优化最经常使用的和最花费时间的，是最好

的方案。

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Implications

• Generalizing from the work of a number of researchers, three elements emerge that, by and large, characterize RISC architectures.

1. Large number of registers 大量寄存器— Operand referencing optimization + locality of

references memory references reduced 减少存储器访问

2. Careful design of pipelines 精心设计流水线— Conditional branch and procedure call

条件分支和过程调用3. Simplified (reduced) instruction set 精简

指令集

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Use of Large Register File

• From the analysis—Large number of assignment statements—Most accesses to local scalars 主要访问本地标量 Heavy reliance on register storage 依赖于寄存器存储 Minimizing memory access 最小化内存访问

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Approaches

• Software solution to maximize register usage 软件方法—Require compiler to allocate registers to those

most used variables in a given time 依赖于编译器，把寄存器分配给那些一定时间内使用最

多的变量—Requires sophisticated program analysis 需要复杂的程序分析

• Hardware solution 硬件方法—Have more registers 大量寄存器—Thus more variables will be in registers 寄存器中存放大量变量

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Registers for Local Variables

• Store local scalar variables in registers 在寄存器中存放本地标量变量 Reduces memory access 减少存储器访问• Some problems

—Every procedure (function) call changes locality 每一次过程调用都会改变局部性—On every call, local variables must be saved to

memory 每次调用变量必须被存储到存储器—Parameters must be passed 必须传递参数—On return, results must be returned and

variables from calling programs must be restored

必须返回结果并且恢复调用程序的变量

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Register Windows• Solution: Register windows Organization of registers to realize the goal 为了实现解决前述问题的目标，而对寄存器采用的组织结构• From the analysis

—Only few parameters and local variables 少量参数和本地变量—Limited range of depth of call 有限的调用深度—Use multiple small sets of registers 使用多个小的寄存器组—Calls switch to a different set of registers 过程调用时自动地切换来使用不同的寄存器组—Returns switch back to a previously used set of

registers 返回时切换回以前使用的寄存器组

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Overlapping Register Windows

Three areas within a register set 窗口分为 3 个域：—Parameter registers 参数寄存器域—Local registers 局部寄存器域—Temporary registers 临时寄存器域

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Register Windows cont.

• Temporary registers from one set overlap parameter registers from the next

临时寄存器用于当前过程与下一级过程 ( 被当前过程调用的过程 ) 交换参数和结果

• Temporary registers at one level are physically the same as the parameter registers at the next lower level.当前层的临时寄存器域和下一层的参数寄存器域物理上是同一个域。

• This allows parameter passing without moving data

这种重叠准许不用实际移动数据就能传递参数

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Circular Buffer diagram

The actual organization of the register file is as a circular buffer of overlapping windows.

寄存器集的实际组织结构是一个由重叠窗口组成的环形缓冲器。

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Operation of Circular Buffer

• When a call is made, a current window pointer (CWP) is moved to show the currently active register window

当一个调用发生时，当前窗口指针移动到当前活动寄存器窗口

• If all windows are in use, an interrupt is generated and the oldest window (the one furthest back in the call nesting) is saved to memory (only .in and .loc need to be saved)

当所有窗口都在使用就会产生中断，最老的窗口会保存到内存（只保存参数、局部窗口的数据）

• A saved window pointer indicates where the next saved windows should restore to

保存窗口指针表明下一个保存窗口应该恢复的地方

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Operation of Circular Buffer (2)

• Studies show: 8 windows are enough to handle up to of call/return without save/restore

8 个窗口足够处理 99% 的调用和返回• E.g., Berkeley RISC uses 8 windows of 16

registers each

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Global Variables - 2 Options

• Allocated by the compiler to memory 由编译器为全局变量指定存储器位置

—Straightforward 直截了当—Inefficient for frequently accessed variables

对经常访问的全局变量效率低下• Have a set of registers for global variables CPU 中有一组全局寄存器

—e.g., registers 0 - 7: global 8 - 31: local to current window

—Increased hardware burden 硬件负担增加—Compiler must decide which global variables

should be designed to registers 编译器也必须裁定什么样的全局变量应指派到寄存器。

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Registers v Cache

Large Register File Cache

• All local scalars Recently used local scalars 所有局部变量 最近使用的局部标量• Individual variables Blocks of memory 个别变量 存储器块• Compiler assigned global variables Recently used global

variables 编译器指派全局变量 最近使用的全局变量 • Save/restore based on Save/restore based on caching procedure nesting algorithm 保存 /恢复基于过程的嵌套深度 保存 /恢复基于 cache替换算法• Register addressing Memory addressing 寄存器寻址 存储器寻址

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Registers v Cache

• 大寄存器—保留了所有的局部标量变量—空间利用率低（窗口大，参数少）—寄存器与存储器之间的数据传送不太频繁

• Cache—有选择地保留局部标量变量—可以有效地利用空间（动态更新）—同时也存在空间利用率低的问题（成块传送，包含无

用数据）—寄存器与存储器之间的数据传送可能较频繁（组关联映像）

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Registers v Cache

寄存器优于 Cache 表现在：• 为访问基于窗口寄存器集中的一个局部标量，使用一个窗

口号和一个“虚拟的”寄存器号。这些通过一个相对简单的译码器来选择某一个具体的寄存器。

• 为访问 cache 存储器中的一个位置，必须生成全宽度的地址。这种操作的复杂性取决于寻址方式。在一个组关联的 cache 中，地址的一部分用于读取等同于组长度的几个字和标记 (tag) ，地址的另一部分用于与标记进行比较，以选择所读的一个字。

• 这一点应是很清楚的，尽管 cache 能与寄存器集一样地快，但 cache 的存取时间肯定要长。于是，从性能观点看，基于窗口的寄存器集对于局部标量是优选的。通过加入只由指令使用的 cache ，能进一步改善性能。

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Referencing a Scalar - Window Based Register File

“ virtual” register number

window number

快

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Referencing a Scalar - Cache

慢

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Compiler Based Register Optimization

• Assume small number of registers (16-32) 假设只有少量寄存器可用

—优化寄存器的使用就是编译器的责任• HLL programs have no explicit references to

registers 用高级语言写的程序没有对寄存器的显式引用• The objective of the compiler is to keep the

operands for as many computations as possible in registers rather than main memory, and to minimize load-and-store operations. 编译器的目标就是，尽可能地在寄存器中而不是在主存中为多数计算保持操作数，并且减少与内存的装入和存储操作。

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Compiler Based Register Optimization cont.

1. Each quantity is assigned to a symbolic or virtual register准备驻留在寄存器中的每个程序量先被指派到一个符号的或虚拟的寄存器中

2. Map (unlimited) symbolic registers to real registers 然后编译器再将这些末限定数目的符号寄存器映射到固定数

目的实寄存器上3. Symbolic registers that do not overlap can share

real registers 那些使用不重叠的符号寄存器能共享同一实寄存器4. If you run out of real registers, some variables use

memory 若在程序具体运行期间，需要打交道的量多于实寄存器数目、则某些量要被指派到存储器位置上

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Optimization

• The essence of the optimization task is to decide which quantities are to be assigned to registers

优化任务的本质 : 是判定程序中什么样的量应指派到寄存器中

• The technique is known as graph coloring—图着色技术—Used in RISC compiler 用在 RISC 编译器—Borrowed from the discipline of topology 这是由拓扑学借用过来的技术

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Graph Coloring

• Given a graph of nodes and edges 对于一个由结点和边组成的给定图• Assign a color to each node 为每个结点指定颜色• Adjacent nodes have different colors 使相邻节点不同色• Use minimum number of colors

要使用颜色的数目最少• Nodes are symbolic registers

结点是符号寄存器

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Graph Coloring cont.

• Two registers that are live in the same program fragment are joined by an edge

若两个符号寄存器同时“存活”于同一程序段，则相应的两个结点用一条边连接起来以指出它们相关。

• Try to color the graph with n colors, where n is the number of real registers

尝试用 n种颜色给图上色， n为实寄存器的数目• Nodes that can not be colored are placed

in memory 这些不能上色的结点必须放入存储器中

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Graph Coloring Approach•Assume a program with six symbolic registers to

be compiled into three actual registers

•Part a: 符号寄存器使用的时间顺序 Part b: 寄存器干涉图

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A Trade-Off• A trade-off between large registers and register

optimization 在使用大量的寄存器和寄存器优化之间有一个权衡考虑问题• With even simple register optimization,

there is little benefit to the use of more than 64 registers

若只有相当简单的寄存器优化，那么使用多于 64 个寄存器只带来很少的好处

• With reasonably sophisticated register optimization techniques, there is only marginal performance improvement with more than 32 registers使用相当精致的寄存器优化技术，也比使用多于 32 个的寄存器带来更多的临界性能改善

• Studies show—64 registers are enough with simple register optimization—32 registers are enough with sophisticated register

optimization

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Reduced Instruction Set ArchitectureWhy CISC (1)?

• Why CISC ？—Ease compiler writing 使编译器的编写更容易—Improve execution efficiency 提高执行效率

• Compiler simplification?—Disputed…争论—Complex machine instructions harder to exploit

– 难以使用，编译器必须找到严格满足限制的情况—Optimization more difficult

– E.g. Minimize code size, enhance pipelining 减小代码提高流水都很难实现

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Why CISC (2)?

• Smaller programs?—Program takes up less memory 程序占用内存少

– But memory is now cheap 但是内存非常便宜—Fewer instructions to be fetched, reducing page

faults.

—May not occupy less bits in symbolic machine language

符号形式的机器语言，所占据的存储器位数却不见得小– More instructions require longer op-codes

CISC 指令多，需要的操作码就长– RISC tend to emphasize register, and register references

require fewer bitsRISC 指令使用的寄存器访问要求较少位数

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Why CISC (1)?

• Code Size Relative to RISC I11 C Programs

RISC I 1.0VAX-11/780 0.8M68000 0.9Z8002 1.2PDP-11/70 0.9

CISC 比 RISC节省很少甚至没有节省VAX 比 PDP-11 减少很少，但 VAX 指令复杂的多

CISC

RISC

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Why CISC (3)?

• Faster programs?—More complex control unit 更复杂的控制单元—Microprogram control store larger 微程序控制存储更大—thus simple instructions take longer to execute 增加了简单指令的执行时间

• It is far from clear that CISC is the appropriate solution

CISC 是较合适的解决方法

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RISC Characteristics

• One instruction per cycle 每周期一条指令

• Register to register operations 寄存器到寄存器操作• Few, simple addressing modes

简单寻址方式• Few, simple instruction formats

简单指令格式

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One Instruction Per Machine Cycle• In a machine cycle 在一个机器周期

—fetch two operands from registers 从寄存器取两个操作数—Perform an ALU operation 完成一个 ALU 操作—Store the result in a register 结果存寄存器

• There is little or not need for microcode 很少或没有需要微代码• Machine instructions can be hardwired 机器指令可以用硬布线的方式实现Such instructions should execute faster than

comparable machine instructions on other machines.

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Register-to-Register Operations

• Most operations is register-to-register 大多数操作应是寄存器到寄存器的• Only LOAD and STORE accessing memory 只有简单的 LOAD 和 STORE 操作访问存储器• Simplify instruction set and control unit 简化指令集和控制器

—RISC include only 1 or 2 ADD instructions—VAX has 25 different ADD instructions

• Encourages the optimization of register use 更适合于寄存器的优化使用

—Frequently accessed operands remain in high-speed storage 频繁存取的操作数保留在高速存储装置

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Simple Addressing Modes

• Almost all RISC instructions use simple register addressing

几乎全部 RISC 指令都使用寄存器寻址方式• May include several additional modes

—Displacement and PC-relative 可能包括几种其它寻址方式，如偏移和相对

• Simplify instruction set and control unit 简化指令集和控制器

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Simple Instruction Formats

• Only one or a few formats are used 仅使用一种或少数几种格式• Instruction length is fixed and aligned on word

boundaries 指令长度固定并且在字边界上对齐—A single instruction does not cross page

boundaries 单一指令不会跨越内存分页的边界

• Field locations, especially the opcode, are fixed 字段位置，特别是操作码字段位置是固定的

—Opcode decoding and register operand accessing can occur simultaneously

操作码的译码和寄存器操作数的访问能同时出现—Simplify control unit 简化控制器

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CISC v RISC Typical of a RISC

— A single instruction size (typically 4 bytes) 单一指令长度（典型 4 个字节）

A small number of data addressing modes (typically less than five)

较少的寻址方式（典型小于 5 种）

— No indirect addressing 无间接寻址No operations that combine load/store with arithmetic

装入／存储操作不会与算术操作混在一起No more than one memory-addressed operand per instruction每条指令不会有多于—个的存储器操作数Does not support arbitrary alignment of data for load/store operations对装入／存储操作．不支持数据的任意对齐

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CISC v RISC

• RISC designs may benefit from the inclusion of some CISC features

RISC 设计包括某些 CISC 特色会有好处• CISC designs may benefit from the

inclusion of some RISC featuresCISC 设计包括某些 RISC 特色也会有益

• PowerPC 不再是纯 RISC 机• Pentium 也结合了 RISC 的特征

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RISC Pipelining

• RISC: Most instructions are register to register 大多数指令是寄存器到寄存器的• Two phases of execution 指令周期分为两个步骤：

—I: Instruction fetch 取指令—E: Execute ( ALU operation with register input and output )

执行指令（带寄存器输入和输出，完成一个ALU 操作）

• For load and store 装入和存储操作需要三个步骤：—I: Instruction fetch 取指令—E: Execute ( Calculate memory address )

执行指令（计算存储器地址）—D: Memory( Register to memory or memory to register

operation ) 存储器（寄存器到存储器或反向操作）

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Effects of PipeliningOnly one memory access per phase

Permitting two memory access per phase

1 2 3 4 5 6 7 8 9 10111213

1 2 3 4 5 6 7 8 9 10

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8 109

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Effects of Pipelining

1 2 3 4 5 6 7 8 9 10 11 12 13

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Effects of Pipelining

• Only one memory access per phase

1 2 3 4 5 6 7 8 9 10

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Effects of Pipelining

• Permitting two memory access per phase

1 2 3 4 5 6 7 8

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Effects of Pipelining

1 2 3 4 5 6 7 8 109

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Optimization of Pipelining

• Delayed branch 延迟转移—Makes use of a branch that does not take

effect until after execution of the following instruction. The instruction location immediately following the branch is referred to as the delay slot.

它利用了转移指令直到下面一条指令之后才产生影响这一特点，在转移指令之后安排一条有用指令来替代仅为延迟的空操作。紧跟转移指令之后的指令位置称为延迟槽。

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Normal and Delayed Branch

AddressNormal Delayed Optimized100 LOAD X,A LOAD X,A LOAD X,A101 ADD 1,A ADD 1,A JUMP 105102 JUMP 105 JUMP 106 ADD 1,A103 ADD A,B NOOP ADD A,B104 SUB C,B ADD A,B SUB C,B105 STORE A,Z SUB C,B STORE A,Z106 STORE A,Z

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Use of Delayed Branch

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Use of Delayed Branch

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Use of Delayed Branch

1 2 3 4 5 6 7

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Use of Delayed Branch

1 2 3 4 5 6 7

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Controversy

• Problems—No pair of RISC and CISC that are directly comparable没有可以直接比较的 RISC 和 CISC 机器

—No definitive set of test programs 没有正式的测试程序—Difficult to separate hardware effects from complier effects 难于将硬件效应勺编译器编写技巧的效应分开—Most comparisons done on “toy” rather than production

machines 对它们的分析比较．大都是在模型机上完成的而不是在商品机上—Most commercial devices are a mixture 大多数商品机都具有 RISC 和 CISC 的混合特征