Xilinx_Pci Databook

8/9/2019 Xilinx_Pci Databook

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, XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Archindry, NeoCAD, NeoCAD EPIC, NPRISM, NeoROUTE, Plus Logic, Plustran, P+, Timing Wizard, and TRACE are registered trademarks of Xilinx, Inc.

, all XC-prefix product designations, XACTstep , XACTstep Advanced, XACTstep Foundry, XACT-Floorplanner, XACPerformance, XAPP, XAM, X-BLOX, X-BLOX plus, XChecker, XDM, XDS, XEPLD, XPP, XSI, Foundation SerieanceCORE, BITA, Configurable Logic Cell, CLC, Dual Block, FastCLK, FastCONNECT, FastFLASH, FastMap, HardLCA, Logic Cell, LogiCORE, LogiBLOX, LogicProfessor, MicroVia, PLUSASM, PowerGuide, PowerMaze, SelectSMARTswitch, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, and ZERO+ are trademarks of Xilinx, Inc. The Progmable Logic Company and The Programmable Gate Array Company are service marks of Xilinx, Inc.All other trademarks are the property of their respective owners.

Xilinx does not assume any liability arising out of the application or use of any product described or shown herein; nor dit convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx reserves the righmake changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xiwill not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its pucts. Xilinx devices and products are protected under one or more of the following U.S. Patents: 4,642,487; 4,695,744,706,216; 4,713,557; 4,746,822; 4,750,155; 4,758,985; 4,820,937; 4,821,233; 4,835,418; 4,853,626; 4,855,614,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,195,148,390; 5,155,432; 5,166,858; 5,224,056; 5,243,238; 5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,865,319,252; 5,319,254; 5,321,704; 5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,405,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153; 5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,205,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189; 5,410,194; 5,414,377; 5,422,833; 5,426,378; 5,426,375,430,687; 5,432,719; 5,448,181; 5,448,493; 5,450,021; 5,450,022; 5,453,706; 5,466,117; 5,469,003; 5,475,255,477,414; 5,481,206; 5,483,478; 5,486,707; 5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,195,498,979; 5,498,989; 5,499,192; 5,500,608; 5,500,609; 5,502,000; 5,502,440; RE 34,363, RE 34,444, and RE 34,80Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein arfree from patent infringement or from any other third party right. Xilinx assumes no obligation to correct any errors contaherein or to advise any user of this text of any correction if such be made. Xilinx will not assume any liability for the accuor correctness of any engineering or software support or assistance provided to a user.Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such apcations without the written consent of the appropriate Xilinx officer is prohibited.Copyright 1999 Xilinx, Inc. All Rights Reserved.

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Xilinx PCI Solutions (www) www.xilinx.com/pciXilinx Home Page www.xilinx.com

Application Service CentersNorth America Hotline: +1 408-879-5199 (USA, Xilinx Headquarters)

+1 800-255-7778Fax: +1 408-879-4442

Email: [email protected]

United Kingdom Hotline: (44) 1932-820821Fax: (44) 1932-828522


France Hotline: (33) 1-3463-0100Fax: (33) 1-3463-0959


Germany Hotline: (49) 89-93088-130Fax: (49) 89-93088-188


Japan Hotline: (81) 3-3297-9163Fax: (81) 3-3297-0067Email: [email protected]

Korea Hotline: (82) 2-761-4277Fax: (82) 2-761-4278


Hong Kong Hotline: (85) 2-2424-5200Fax: (85) 2-2424-7159


Data Book

2100 Logic DriveSan Jose, CA 95124

United States of AmericaTelephone: +1 408-559-7778

Fax: +1 408-559-7114

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Dear PCI customer,On behalf of the PCI Team at Xilinx, and our CORE partners, welcome to our March 1999 PCI Data Book, and thank youyour interest in Xilinx PCI Solutions.As the inventor and leading provider of Field Programmable Gate Array Technology, we want to pledge our continuing cmitment to support your great ideas in logic design and PCI applications.Since the last version of this databook we have added the Real 64/66 PCITM, the industry's first general-purpose 64-Bit, 6MHz PCI Solution, and the PCI32 Spartan XL, a single-chip PCI solution at half the cost of standard PCI bridge chips.Our mission is to provide you with a high-quality PCI solution that offers better flexibility, higher performance, and lowethan any other available solution. Xilinx PCI allows you to integrate a PCI interface with your unique logic, into one fle

programmable device. Since the first PCI product introduction in February 1996, we have developed a complete solution PCI including super-fast FPGAs, easy-to-use predictable LogiCORE modules with guaranteed timing, as well as Pboards, drivers, and design examples. We believe you will find Xilinx PCI Solution interesting and we hope that you will sider us for future designs.Together we can bring the great ideas to life!

Sincerely

Per Holmberg

LogiCORE Product ManagerCORE Solutions Group


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1 Introduction

2 PCI Products

3 FPGA Products

4 Design Methodology

5 PCI Compliance Checklists

6 Pinout and Configuration

7 Resources

8 Waveforms

9 Ordering Information and License Agreement

10 Sales Offices, Sales Representatives, and Distributors

Section Titles
http://intro.pdf/http://resources.pdf/http://agreement.pdf/http://offices.pdf/http://resources.pdf/http://offices.pdf/http://agreement.pdf/http://intro.pdf/


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7/258May, 1999 iii

IntroductionIntroduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 1

Using an FPGA for PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 1Using Xilinx for PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 1Highest-Performance PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 1Lowest-cost PCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 1

The Real-PCI from Xilinx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 1Real Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 1Real Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 2Real Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 2Real Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 3Xilinx PCI Design Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 3PCI over the Internet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 4About this Databook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 4

PCI ProductsPCI64 Virtex Interface Version 3.0

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 1Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 2General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 2Smart-IP Technology - guaranteed timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3

PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3PCI I/O Interface Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4Parity Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4Target State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4Initiator State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4User Application with Optional Burst FIFOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4

Interface Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4Supported PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4Burst Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 5Verification Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 5Ping Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 5Device Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 6Recommended Design Experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 6

PCI32 Virtex Version 3.0Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 7Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 7Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 8General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 8Smart-IP Technology - guaranteed timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 9Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 9

PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 9PCI I/O Interface Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 10Parity Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 10Target State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 10Initiator State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 10User Application with Optional Burst FIFOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 10

Interface Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 10Supported PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 10Burst Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 10Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 11

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Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 11Verification Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 11Ping Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 11Device Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 12Recommended Design Experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 12

PCI32 4000 XLA Interface Version 3.0Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 13Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 13Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 14General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 14Smart-IP Technology - guaranteed timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 15Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 15

PCI I/O Interface Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 15Parity Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 15Target State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 15Initiator State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 15PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 15User Application with Optional Burst FIFOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 16

Interface Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 16Supported PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 16

Burst Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 16Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 17Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 17Verification Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 18Ping Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 18Synthesizable PCI Bridge Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 18Device Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 18Recommended Design Experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 18

PCI32 SpartanXL Interface Version 3.0Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 19Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 19Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 20General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 20Smart-IP Technology - guaranteed timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 21Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 21

PCI I/O Interface Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 21Parity Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 21Target State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 21Initiator State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 21PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 21User Application with Optional Burst FIFOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 22

Interface Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 22Supported PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 22Burst Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 22Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 23

Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 23Verification Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 23Ping Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 24Synthesizable PCI Bridge Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 24Device Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 24Recommended Design Experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 24


9/258May, 1999 v

PCI32 Spartan Master & Slave InterfaceIntroduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 25Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 25Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 26General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 26Smart-IP Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 27Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 27

PCI I/O Interface Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 27

Parity Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 27Target State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 27Initiator State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 27PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 27User Application with Optional Burst FIFOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 27

Interface Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 28Supported PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 28Burst Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 28Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 28Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 29Verification Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 29Ping Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 30Synthesizable PCI Bridge Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 30Device Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 30Recommended Design Experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 30

Synthesizable PCI Bridge Design ExamplesIntroduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 31General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 31Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 33

BAR0 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 33BAR1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 34Register File Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 34Target FIFO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 34Initiator FIFO Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 34

Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 35Core Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 35Verification Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 35Recommended Design Experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 35Reference Design License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 35

PCI64 PCI Prototyping BoardNallatech Limited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 37Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 37Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 37Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 38General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 38Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 38Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 39

HotPCI Spartan Prototyping BoardVirtual Computer Corporation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 41Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 41Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 41Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 41General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 42

Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 42Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 42

Configuration with the CCM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 42Configuration with an Xchecker cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 43


10/258vi May, 1999

DriverWorks Windows Device Driver Development Kit Version 2.0Compuware NuMega . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 45Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 45Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 45Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 45Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 45Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 47

VtoolsD Windows Device Driver Development Kit Version 3.0Compuware NuMega . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 49Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 49Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 49Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 49Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 50Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 50

Synthesizable PCI Power Management Design ExampleFeatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 51General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 52Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 52

Capabilities Linked List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 52Power Management Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 53User-defined Configuration Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 54PME Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 54

Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 54Core Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 54

The cfg file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 54The pcim_top/pcis_top file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 54Web download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 54Editing the cfg file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 55

Verification Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 55Recommended Design Experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 55

FPGA Products

LogiCORE PCI Supported Virtex FPGAsFeatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1

LogiCORE PCI32 Supported Spartan and SpartanXL FPGAsIntroduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 3Spartan Series Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 3Additional SpartanXL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 4Universal PCI Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 4

Design MethodologyLogiCORE PCI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1

Core Configuration in VHDL and Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2Selectable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2

Enable 66 MHz (Virtex PCI64 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2Latency Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2Base Address Register Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2External Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2Cap List Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2INTA# Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2User Config Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2

Core Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2


11/258May, 1999 vii

PCI Compliance ChecklistsVirtex PCI Compliance Checklist

Component Product Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1Component Electrical Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 15 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 23.3 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 4Loading and Device Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 6Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 764-bit Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 8

XC4000XLA PCI Compliance ChecklistComponent Product Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 9Component Electrical Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 95 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 103.3 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 12Loading and Device Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 14Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1564-bit Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 16

Spartan-XLPCI Compliance ChecklistComponent Product Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 17

Component Electrical Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 175 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 183.3 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 20Loading and Device Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 22Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 2364-bit Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 24

LogiCORE PCI V3.0 Cores PCI Compliance ChecklistComponent Product Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 25Component Configuration Checklist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 26

Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 26Device Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 28Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 28Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 29VGA Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 30General Component Protocol Checklist (Master). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 31General Component Protocol Checklist (Target) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 33Component Protocol Checklist for a Master Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 35

Test Scenario: 1.1. PCI Device Speed Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 35Test Scenario: 1.2. PCI Bus Target Abort Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 36Test Scenario: 1.3. PCI Bus Target Retry Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 38Test Scenario: 1.4. PCI Bus Single Data Phase Disconnect Cycles . . . . . . . . . . . . . . . . . . . . . . . . 5 - 39Test Scenario: 1.5. PCI Bus Multi-Data Phase Target Abort Cycles . . . . . . . . . . . . . . . . . . . . . . . . 5 - 40Test Scenario: 1.6. PCI Bus Multi-Data Phase Retry Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 43Test Scenario: 1.7. PCI Bus Multi-Data Phase Disconnect Cycles . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 44Test Scenario: 1.8. Multi-Data Phase and TRDY# Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 45

Test Scenario: 1.9. Bus Data Parity Error Single Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 48Test Scenario: 1.10. Bus Data Parity Error Multi-Data Phase Cycles . . . . . . . . . . . . . . . . . . . . . . . 5 - 49Test Scenario: 1.11. Bus Master Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 50Test Scenario: 1.12. Target Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 50Test Scenario: 1.13. PCI Bus Master Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 51Test Scenario: 1.14. PCI Bus Master Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 51Test Scenario 1.x Explanations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 51

Component Protocol Checklist for a Target Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 52Test Scenario: 2.1. Target Reception of an Interrupt Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 52Test Scenario: 2.2. Target Reception of a Special Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 52


12/258viii May, 1999

Test Scenario: 2.3. Target Detection of Address and Data Parity Error for Special Cycle. . . . . . . . 5 - 52Test Scenario: 2.4. Target Reception of I/O Cycles with Legal and Illegal Byte Enables.. . . . . . . . 5 - 52Test Scenario: 2.5. Target Ignores Reserved Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 52Test Scenario: 2.6. Target Receives Configuration Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 53Test Scenario: 2.7. Target Receives I/O Cycles with Address and Data Parity Errors.. . . . . . . . . . 5 - 53Test Scenario: 2.8. Target Configuration Cycles with Address and Data Parity Errors. . . . . . . . . . 5 - 53Test Scenario: 2.9. Target Receives Memory Cycles.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 53Test Scenario: 2.10. Target Gets Memory Cycles with Address and Data Parity Errors. . . . . . . . . 5 - 54

Test Scenario: 2.11. Target Gets Fast Back to Back Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 54Test Scenario: 2.12. Target Performs Exclusive Access Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 54Test Scenario: 2.13. Target Gets Cycles with IRDY# Used for Data Stepping. . . . . . . . . . . . . . . . 5 - 54Test Scenario 2.x Explanations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 55

Pinout and ConfigurationPinout and Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1

Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1Compatibility Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1Pinout Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1Pinout for the XC4013XLA PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 2Pinout for the XC4013XLA PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 5Pinout for the XC4028XLA HQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 8Pinout for the XC4062XLA HQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 11Pinout for the XC4062XLA BG432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 14Pinout for the XCS20 TQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 18Pinout for the XCS30 PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 20Pinout for the XCS30 PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 23Pinout for the XCS40 PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 26Pinout for the XCS40 PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 29Pinout for the XCV300 BG432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 32

ResourcesResources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1

PCI Special Interest Group (PCI-SIG) Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1PCI and FPGA XPERT Partners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1Supporting PCI Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 2PCI Reference Books . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3Xilinx Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3LogiCORE User's Lounge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3

WaveformsWaveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1

Target Configuration Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 2Target Configuration Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 4Initiator 32-bit Single Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 6

Initiator 32-bit Single Memory Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 8Initiator 32-bit Burst Memory Read Multiple. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 10Initiator 32-bit Burst Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 12Initiator 32-bit Burst Memory Write with Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 14Target 32-bit Single Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 16Target 32-bit Single Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 18Target 32-bit Burst Memory Read Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 20Target 32-bit Burst Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 22Target 32-bit Burst Memory Write with Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 24Target 32-bit Retry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 26Target 32-bit Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 28


13/258May, 1999 ix

Initiator 64-bit Burst Memory Read Multiple. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 30Initiator 64-bit Burst Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 32Initiator 64-bit Burst Memory Write with Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 34Initiator 64-bit Memory Read of a 32-bit Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 36Initiator 64-bit Memory Write of a 32-bit Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 38Target 64-bit Burst Memory Read Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 40Target 64-bit Burst Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 42Target 64-bit Burst Memory Write with Disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 44

Target 64-bit Retry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 46Target 64-bit Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 48

Ordering Information and License AgreementXilinx PCI64 Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 1Xilinx PCI64 Virtex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 2Xilinx PCI32 Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 2LogiCORE PCI32 Spartan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 2Support, Updates, and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 3Product Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 3Additional PCI Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 4Obsolete products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 4

Sales Offices, Sales Representatives, and DistributorsHeadquarters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1Xilinx Sales Offices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1North American Distributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 2U.S. Sales Representatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 2International Sales Representatives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4


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2 PCI Products

3 FPGA Products




7 Resources

8 Waveforms



11

Introduction
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Introduction


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IntroductionPCI (Peripheral Component Interconnect) has become oneof the most popular bus standards, not only for personalcomputers, but also for industrial computers, communica-tion switches, routers, and instrumentation.PCI is also a significant design challenge; the stringentelectrical, functional, and timing specifications are difficult

to meet in any technology and the standard keeps evolvingto meet the dynamic needs of our industry.This is why you need a flexible PCI solution that will meetboth your current and future requirements, while guaran-teeing full PCI compliance with no limitations on perfor-mance or functionality.

Using an FPGA for PCIBy integrating a fully-compliant PCI interface with an appli-cation-specific back-end design into one FPGA, you canachieve higher integration, higher performance and lowercost than other PCI solutions.

Further, the Xilinx PCI solution can be customized for aspecific application and, as a result, the highest possibleperformance is achieved.The flexibility of an FPGA makes it possible to update thePCI board, through software alone, in development or in thefield. This significantly reduces your design risk and cutsdevelopment time.

Using Xilinx for PCIWe provide the most cost-effective and high-performancePCI solution in the market by leveraging the flexibility of Xil-inx Field Programmable Gate Arrays (FPGAs). We make

PCI easy to design by providing a complete solution ofproven cores, intuitive development tools, and world-classtechnical support.

Highest-Performance PCIWhen we introduced the Real 64/66 PCI, we were first outwith a fully compliant, general-purpose 64-bit 66MHz PCIsolution. By using our LogiCORE PCI64 for Virtex, you canachieve the highest possible PCI performance, 528 MB/s.

Lowest-cost PCIWith our low-cost FPGA family, Spartan and SpartanXL,

you can design your own unique PCI bridge with integratedFIFOs, DMA, and custom logic, at a cost only half of otheravailable standard PCI bridge chips.

The Real-PCI from XilinxThe Real-PCI from Xilinx is engineered to address all yorequirements on a fully compliant PCI system. It provideyou with Real Compliance Real Flexibility Real Performance Real Availability

Real ComplianceOur PCI cores have been used in over 1,000 customerdesigns. They are fully verified using our industry-provtestbench that simulates over six million unique PCI cycleWe also characterize our PCI cores together with ourFPGAs to verify not only maximum timing, but also mimum and hold timing. Then, when we know that the timinconstraints are met, we apply our unique Smart-IP technology to ensure that you achieve the same timing and functionality every time you implement the core. Thanks to oregular FPGA architecture with segmented routing, anbecause we use a modular core architecture where theFIFOs, DMA channels, and your unique back-end logic arde-coupled from the core, your own design will not affethe PCI interface timing.

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Real FlexibilityOur PCI cores are targeted to our standard off-the-shelfFPGAs, which were designed to be PCI compliant. Thisgives you a range of device sizes and packages to choosefrom, allowing you to integrate a fully-compliant Initiator/ Target PCI interface, scalable dual-port FIFOs, customiz-able DMA channels, and 7,000 to 1,000,000 system gatesof your own unique logic, all on a single device, for the low-est possible cost.Because the FPGA is programmable, you can adapt tofuture needs and changes in the PCI standard by reconfig-uring the FPGA device on your board.

Real PerformanceAll Xilinx PCI cores operate at maximum throughput, with 0wait-state bursts. For example, the Xilinx Real-PCI 64/66solution allows you to create 64-bit PCI systems that oper-ate at up to 66MHz, delivering a sustained throughput of upto 528 Mbytes per second - the maximum performance youcan get from PCI. Our PCI 32/33 cores supports up to 132Mbytes per second.


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*Limited CompactPCI Hot Swap Support. See Xilinx App. NoteImplementing CompactPCI and Hot Swap CompactPCI with Xilinx PCI

Real AvailabilityReal-PCI is here today. It includes a complete family of Log-iCORE designs that are fully characterized for ourXC4000XLA, Spartan, SpartanXL, and Virtex FPGAs. Byusing our standard, off-the-shelf manufacturing capability,leading edge silicon processes, excellent quality and test-ability, and lower manufacturing costs. Plus Real-PCI is not just cores and devices, its also a complete system of devel-opment tools, support, services, and third-party Xilinx-authorized XPERTS to help you every step of the way.

Xilinx PCI Design KitsTo help you reduce your development time even further, Xil-inx has teamed with Nallatech LTD and Virtual ComputerCorp., both providing PCI prototyping boards, NuMegaSoftware providing SW driver development tools, andMemec Design Services providing PCI expertise anddesign services. With our partners, we offer two completePCI Design Kits, PCI64-DK for 64-bit 66MHz PCI, andPCI32-DK for 32-bit 33MHz PCI. The kits include prototyp-ing boards, reference software drivers for Windows 95/98/ NT, full-featured SW driver development tools, and synthe-sizable PCI bridge design examples in VHDL and Verilog.

Xilinx PCI64 Design Kit


20/2581 - 4 May, 1999

PCI over the InternetAs a part of our Silicon Xpresso initiative, we provide theLogiCORE products with all design files you need over theInternet. You will instantly have access to new versions ofthe core, new features, new application notes, and refer-ence designs. As a Xilinx PCI customer, you select yourown unique user name and password to access the coreproduct. To help you configure the PCI core we have anintuitive graphical user interface (GUI) where you easilyselect the settings and features that you need. The processis simple:1. Enter your configuration data into the GUI.2. Click Download, and our Web tool builds your unique

PCI interface with guaranteed timing, which you thendownload to your local computer.

The design files include the PCI design netlist, VHDL/Ver-ilog simulation model and instantiation wrapper, and imple-mentation constraints files.

About this DatabookThe information in this databook is also available on the Xinx web-site, WebLINX atwww.xilinx.com/pci

Xilinx will use the web as primary means of delivering aupdating this information since it is so dynamic by naturWe strongly recommend that customers consult the web fothe latest information on new product availability andatasheet revisions.


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1 Introduction

2 PCI Products

3 FPGA Products




7 Resources

8 Waveforms



11

PCI Products
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PCI Products


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PCI64 Virtex InterfaceVersion 3.0

Xilinx Inc.2100 Logic DriveSan Jose, CA 95124Phone: +1 408-559-7778Fax: +1 408-377-3259E-mail: Techsupport:[email protected]

Feedback: [email protected]: www.xilinx.com/pci

Introduction

With Xilinx LogiCORE PCI64 Virtex interface, a designercan build a customized, 64-bit, 0-66 MHz fully PCI compli-ant system with the highest possible sustained perfor-mance, 528 Mbytes/sec, and up to 1 Million System Gatesin the Virtex family FPGA.

Features Fully 2.2 PCI compliant 64-bit, 0-66 MHz PCI Initiator/

Target Interface Zero wait-state burst operation Programmable single-chip solution with customizable

back-end functionality

Pre-defined implementation for predictable timing inXilinx Virtex Series FPGAs Incorporates Xilinx Smart-IP Technology 3.3 V Operation at 33-66 MHz 3.3 V and 5 V Operation at 0-33 MHz Master automatically handles 64-bit or 32-bit PCI

transactions without knowing the bus width of the target Fully verified design tested with Xilinx testbench and

hardware Configurable on-chip dual-port FIFOs can be added for

maximum burst speed Supported Initiator functions (PCI Master only)

- Memory Read, Memory Write, Memory ReadMultiple (MRM), Memory Read Line (MRL)commands

- I/O Read, I/O Write commands- Configuration Read, Configuration Write commands- Bus Parking- Special Cycles, Interrupt Acknowledge- Basic Host Bridging

R

LogiCORE

FactsCore SpecificsDevice Family VirteSlices Used1 381-403IOBs Used 88System Clock fmax 0-66MHzDevice Features Used Bi-directional data buses

SelectIOBlock SelectRAM+(optional user FIFO

Boundary scan (optional

Supported Devices2/Percent Resources Used

I/O SlicesXCV300-5/6 BG4323 28% 12%XCV1000-5/6 FG6803 17% 3%

Provided with CoreDocumentation PCI Design Guide

PCI Implementation Guide PCI Data Book

Design File Formats Verilog/VHDL Simulation MoVerilog/VHDL Instantiation Co

NGO NetlisConstraint Files M1 User Constraint File (UC

M1 Guide fileVerification Tools Verilog/VHDL TestbenReference designs &application notes

Example designs:PING64 Reference Design

Synthesizable PCI64 Bridge(SB07Design Tool Requirements

Xilinx Core Tools M1.5i SPTested Entry/Verifica-tion Tools4

For CORE instantiationSynopsys FPGA Express

Synopsys FPGA CompileSynplicity Synplif

For CORE verificationCadence Verilog XLMTI ModelSim PE/Plus V4.7

Xilinx provides technical support for this LogiCORE product whenused as described in the Users Guide and in the Application NotesXilinx cannot guarantee timing, functionality, or support of produimplemented in devices not listed above, or if customized beyondthat referenced in the product documentation, or if any changes aremade in sections of design marked as DO NOT MODIFY.

May, 1999 Advanced Data Sheet

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PCI64 Virtex Interface Version 3.0

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Features (cont.) Supported Target functions (PCI Master and Slave)

- Type 0 Configuration Space Header- Up to 3 Base Address Registers (memory or I/O with

adjustable block size from 16 Bytes to 2 GBytes,medium decode speed)

- Parity Generation (PAR), Parity Error Detection(PERR# and SERR#)

- Memory Read, Memory Write, Memory ReadMultiple (MRM), Memory Read Line (MRL), MemoryWrite Invalidate (MWI) commands

- I/O Read, I/O Write commands- Configuration Read, Configuration Write commands- 64-bit data transfers and 32-bit data transfers, burst

transfers with linear address ordering- Target Abort, Target Retry, Target Disconnect- Full Command/Status Registers

Available for configuration and download on the web- Web-based configuration tool- Generation of proven design files- Instant access to new releases

Applications Embedded applications within networkin

telecommunication and industrial systems PCI add-in boards such as graphic cards, video

adapters, LAN adapters and data acquisition boards Hot Swap CompactPCI boards Other applications that need PCI

General DescriptionThe LogiCORE PCI64 Interfaces are pre-implementedand fully tested modules for the Xilinx Virtex Series FPGAThe pinout for the device and the relative placement of thinternal Configurable Logic Blocks (CLBs) are pre-defineCritical paths are controlled by TimeSpecs and guide fileto ensure predictable timing. This significantly reduceengineering time required to implement the PCI portion oyour design. Resources can instead be focused on theunique back-end logic in the FPGA and on the system levedesign. As a result, LogiCORE PCI products can minimize your product development time.Xilinx Virtex Series FPGAs enable designs of fully PCcompliant systems. The devices meet all required electricaand timing parameters including AC output drive characteistics, input capacitance specifications (10pF), 3 ns setupand 0 ns hold to system clock, and 6 ns system clock to output. These devices meet all specifications for both 3.3 V (066 MHz) and 5 V PCI (0-33 MHz).The PCI Compliance Checklist has detailed informatioabout electrical compliance. Other features that enable efficient implementation of a complete PCI system in the Vitex Series includes:

1. The exact number of CLBs depends on user configuration of thecore and level of resource sharing with adjacent logic. For exam-ple, a factor that can affect the size of the design are the numberand size of the BARs.

2. Re-targeting the PCI core to an unlisted device or package willvoid the guarantee of timing. See Smart-IP Technology - guar-anteed timing on page 3 for details.

3. Use -6 for 0-66 MHz operation and -5 for 0-33 MHz operation.4. See Xilinx Web Site for update on tested design tools.

ParityGenerator/

Checker

PCI Configurat ion Space

Initiator

StateMachine

InterruptPin and

Line

Register

LatencyTimer

Register

Vendor ID,Rev ID,

Other User

Data

LC003

TargetState

Machine

P C I I / O

I N T E R F A C E

U S E R

A P P L I C A T I O N

ADIO[63:0]

AD[63:0]

PAR

GNT-

PERR-

SERR-

FRAME-

IRDY-

REQ-

TRDY-

DEVSEL-

STOP-

BaseAddressRegister

0

BaseAddressRegister

1

Command/Status

Register

BaseAddressRegister

2

REQ64-

ACK64-

PAR64

Figure 1: LogiCORE PCI64 Interface Block Diagram


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Block SelectRAM+ memory: Blocks of on-chip ultra-fast RAM with synchronous write and dual-port RAMcapabilities. Used in PCI Interfaces to implement FIFO

Select-RAM memory: on-chip ultra-fast RAM withsynchronous write option and dual-port RAM option.Used in PCI Interfaces to implement FIFO

Individual output enable for each I/O Internal 3-state bus capability

8 global low-skew clock or signal distribution networks IEEE 1149.1-compatible boundary scan logic supportThe Master and Slave Interface module is carefully opti-mized for best possible performance and utilization in theVirtex FPGA architecture. When implemented in aXCV300, 12% of the FPGAs slices are used.

Smart-IP Technology - guaranteedtimingDrawing on the architectural advantages of Xilinx FPGAs,new Xilinx Smart-IP technology ensures highest perfor-mance, predictability, repeatability, and flexibility in PCIdesigns. The Smart-IP technology is incorporated in everyLogiCORE PCI Core.Xilinx Smart-IP technology leverages the Xilinx architec-tural advantages, such as look-up tables (LUTs), distrib-uted RAM, and segmented routing, as well as floorplanninginformation, such as logic mapping and relative locationconstraints. This technology provides the best physical lay-out, predictability, and performance. Additionally, these pre-determined features allow for significantly reduced compiletimes over competing architectures.PCI Cores made with Smart-IP technology are unique by

maintaining their performance and predictability regardlessof the device size.To guarantee the critical setup, hold, and min. and max.clock-to-out timing, the PCI core is delivered with Smart-IPconstraint files that are unique for a device and packagecombination. These constraint files guide the implementa-tion tools so that the critical paths always are within PCIspecification. Retargeting the PCI core to an unsupporteddevice will void the guarantee of timing. Contact one of theXilinx XPERTs partners for support of unlisted devices andpackages. See the XPERTs section in chapter 7 of the Xil-inx PCI Data Book for contact information.

Functional DescriptionThe LogiCORE PCI64 Master and Slave Interface is parti-tioned into five major blocks and an user application asshown in Figure 1. Each block is described below.

PCI Configuration SpaceThis block provides the first 64 Bytes of Type 0, version 2.1Configuration Space Header (CSH) (see Table 1) to sup-port software-driven Plug-and Play initialization and con-

figuration. This includes information for Command, Statuand three Base Address Registers (BARs). These BARsillustrate how to implement memory- or I/O-mappeaddress spaces.Table 1: PCI Configuration Space Header

Each BAR sets the base address for the interface andallows the system software to determine the addressablerange required by the interface. Each BAR designated as amemory space can be made to represent a 32-bit or a 64-bit space.

Using a combination of Configurable Logic Block (CLB) fflops for the read/write registers and CLB look-up tables fthe read-only registers results in optimized logic mappinand placement.The capability for extending configuration space has beenbuilt into the backend interface. This capability, includithe ability to implement a CapPtr in configuration spacallows the user to implement functions such as AdvanceConfiguration and Power Interface (ACPI) in the backendesign.

31 16 15 0Device ID Vendor ID 00h

Status Command 04h

Class Code Rev ID 08h

BIST HeaderType

LatencyTimer

Cache Line Size

0Ch

Base Address Register 0 (BAR0) 10h



Base Address Register 3 (BAR3) 1Ch



Cardbus CIS Pointer 28h

Subsystem ID Subsystem Vendor ID 2Ch

Expansion ROM Base Address 30h

Reserved CapPtr 34h

Reserved 38h

Max_Lat Min_Gnt InterruptPin

InterruptLine

3Ch

Reserved 40h-FFh

Note:Italicized address areas are not implemented in the LogiCOREPCI64 Virtex Interface default configuration. These locations retuzero during configuration read accesses.


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2 - 4 May, 1999

PCI I/O Interface BlockThe I/O interface block handles the physical connection tothe PCI bus including all signaling, input and output syn-chronization, output three-state controls, and all request-grant handshaking for bus mastering.

Parity Generator/Checker

This block generates/checks even parity across the ADbus, the CBE lines, PAR and the PAR64 signal. It alsoreports data parity errors via PERR- and address parityerrors via SERR-.

Target State MachineThis block controls the PCI interface for Target functions.The states implemented are a subset of equations definedin Appendix B of thePCI Local Bus Specification . Thecontroller is a high-performance state machine usingone-hot (state-per-bit) encoding for maximum performance.State-per-bit encoding of the next-state logic functions facil-itates a high performance implementation in the XilinxFPGA architecture.

Initiator State MachineThis block controls the PCI interface for Initiator functions.The states implemented are a subset of equations definedin Appendix B of thePCI Local Bus Specification . The Ini-tiator Control Logic also uses state-per-bit encoding formaximum performance.

User Application with Optional Burst FIFOsThe LogiCORE PCI64 Interface provides a simple, general-purpose interface with a 64-bit data path and latchedaddress for de-multiplexing the PCI address/data bus. Thegeneral-purpose user interface allows the rest of the deviceto be used in a wide range of 64-bit and 32-bit applications.Typically, the user application contains burst FIFOs toincrease PCI system performance. An on-chip read/writeFIFO, built from the on-chip synchronous dual-port RAM(Block SelectRAM+) available in Virtex Series FPGAs,supports data transfers in excess of 66 MHz.Several synthesizable re-usable bridge designs includingcommonly used backend functions, such as doorbells andmailboxes, are provided with the core.

Interface ConfigurationThe LogiCORE PCI64 Interface can easily be configured tofit unique system requirements by using Xilinx web-basedPCI configuration tool or by changing the Verilog, VHDL, orVIEWlogic configuration file. The following customizationoptions are supported by the LogiCORE product anddescribed in product documentation. Initiator or target functionality (PCI Master only) Base Address Register configuration (1 - 3 Registers,

size and mode) Configuration Space Header ROM Initiator and target state machine (e.g., terminatio

conditions, transaction types and request/transactionarbitration)

Burst functionality User Application including FIFO (back-end design)

Supported PCI CommandsTable 2 illustrates the PCI bus commands supported by theLogiCORE PCI64 Interface. The PCI Compliance Checklist has more details on supported and unsupported com-mands.Table 2: PCI Bus Commands

Burst TransferThe PCI bus derives its performance from its ability to suport burst transfers. The performance of any PCI application depends largely on the size of the burst transfer. AFIFO to support PCI burst transfer can efficiently be impl

mented using the Virtex on-chip RAM features, both Ditributed and Block SelectRAM+.Each Virtex CLB supports four 16x1 RAM blocks. Tcorresponds to 64 bits of single-ported RAM or 32 bits dual-ported RAM, with simultaneous read/write capabiliThe Block SelectRAM+ can be used to create deep FIFOs

BandwidthXilinx LogiCORE PCI64 Interface supports fully complizero wait-state bust operations for both sourcing and

CBE [3:0] CommandPCI

MasterPCI

Slave0000 Interrupt Acknowledge No1 Yes0001 Special Cycle No1 Ignore0010 I/O Read Yes Yes0011 I/O Write Yes Yes0100 Reserved Ignore Ignore0101 Reserved Ignore Ignore0110 Memory Read Yes Yes0111 Memory Write Yes Yes1000 Reserved Ignore Ignore1001 Reserved Ignore Ignore1010 Configuration Read Yes Yes1011 Configuration Write Yes Yes1100 Memory Read Multiple Yes Yes1101 Dual Address Cycle No1 Ignore1110 Memory Read Line Yes Yes1111 Memory Write Invalidate No1 Yes

Note:1. The Initiator can present these commands, however, they eitherequire additional user-application logic to support them or have nbeen thoroughly tested.


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receiving data. This Interface supports a sustained band-width of up to 528 MBytes/sec. The design can be config-ured to take advantage of the ability of the LogiCOREPCI64 Interface to do very long bursts. Since the FIFO isnot of fixed size, bursts can go on for as long as the chipsetarbiter will allow. Furthermore, since the FIFOs and DMAare decoupled from the proven core, a designer can modifythese functions without affecting the critical PCI timing.

The flexible Xilinx backend, combined with support formany different PCI features, gives users a solution thatlends itself to being used in many high-performance appli-cations. Xilinx is able to support different depths of FIFOsas well as dual port FIFOs, synchronous or asynchronousFIFOs and multiple FIFOs. The user is not locked into oneDMA engine, hence, a DMA that fits a specific applicationcan be designed.The theoretical maximum bandwidth of a 64-bit, 66 MHzPCI bus is 528 MBytes/sec. Attaining this maximum band-width will depend on several factors, including the PCIdesign used, PCI chipset, the processors ability to keep up

with your data stream, the maximum capability of your PCIdesign, and other traffic on the PCI bus. Older chipsets andprocessors will tend to allow less bandwidth than newerones.No additional wait-states are inserted in response to a wait-state from another agent on the bus. Either IRDY or TRDYis kept asserted until the current data phase ends, asrequired by the V2.2 PCI Specification.See Table 3 for PCI bus transfer rates for various opera-tions.Table 3: LogiCORE PCI64 Transfer Rates

Timing SpecificationThe Virtex Series FPGA devices, together with the Logi-

CORE PCI64 product enable design of fully compliant PCIsystems. The maximum speed at which your back-end is

capable of running can be affected by the size of the designas well as by the loading of the hot signals coming directlyfrom the PCI bus.Table 4 shows the key timing parametersfor the LogiCORE PCI64 Interface that must be met for fullPCI compliance.

Table 4: 66 MHz Timing Parameters [ns]

Verification MethodsXilinx has developed a system-level testbench that allowsimulation of an open PCI environment in which a LogCORE-PCI-based design may be tested by itself or witother simulatable PCI agents. Included in these agents area behavioral host and target, and several plug-in modulesincluding a PCI signal recorder and a PCI protocol monitoThe Xilinx PCI testbench is a powerful verification tool tis also used as the basis for verification of the PCI LogCORE. The PCI LogiCORE is also tested in hardware fo

electrical, functional, and timing compliance.Ping Reference DesignThe Xilinx PING64 Application Example, delivered in ilog and VHDL, has been developed to provide an easy-tounderstand example which demonstrates many of the principles and techniques required to successfully use a LogiCORE PCI64 Interface in a System On A Chip solutioThe PING64 design is also used as a test vehicle when ver-ifying the PCI core.

Zero Wait-State ModeOperation Transfer Rate

Initiator Write (PCI LogiCORE) 3-1-1-1Initiator Read (PCI LogiCORE) 4-1-1-1Target Write (PCI LogiCORE) 5-1-1-1Target Read (PCI LogiCORE) 6-1-1-1***Note: Initiator Read and Target Write operations have effectivelythe same bandwidth for burst transfer.

Parameter Ref.PCI Spec.

LogiCOREPCI64

XCV300-06 4

Min Max Min MaxCLK Cycle Time Tcyc 15 30 151 30CLK High Time Thigh 6 6

CLK Low Time Tlow 6 6CLK to Bus Sig-nals Valid3

TICKOF 2 6 22 6

CLK to REQ# andGNT# Valid3

TICKOF 2 6 22 6

Tri-state to Active Ton 2 22

CLK to Tri-state Toff 14 141

Bus Signal Setupto CLK (IOB)

TPSD 3 3

Bus Signal Setupto CLK (CLB)

5 51

GNT# Setup toCLK TPSD 5 5GNT# Setup toCLK (CLB)

TPSD 5 5

Input Hold TimeAfter CLK (IOB)

TPHD 0 0

Input Hold TimeAfter CLK (CLB)

0 02

RST# to Tri-state Trst-off 40 402Notes:1. Controlled by TIMESPECS, included in product2. Verified by analysis and bench-testing3. IOB configured for Fast slew rate

4. Virtex Timing will be included when silicon testing is finished


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Synthesizable PCI Bridge Design(SB07)The synthesizable PCI bridge design, SB07, is an applica-tion bridge for use with the LogiCORE PCI64 Interface. It isdelivered in Verilog and VHDL and has been fully testedwith various devices. This example demonstrates how to in-terface to the PCI core and provide a modular foundationupon which to base other designs. The reference designcan be easily modified to remove select portions of func-tionality.

This design is a general purpose data transfer engine to beused with the LogiCORE PCI64 Interface. Figure 3 presents a block diagram of the SB07 design. Typically, thuser will customize the local interface to conform to a paticular peripheral bus (ISA, VME, i960) or attach to a memory device. The design is modular so that unused portionmay be removed. Other bridge applications can be de-signed using subsets of SB07. The Synthesizable PCI

Bridge Design Data Sheet lists the set of features and spe-cifics for the SB07 design.

Device UtilizationThe Target/Initiator options require a variable amount ofCLB resources for the PCI64 Interface.Utilization of the device can vary slightly, depending on theconfiguration choices made by the designer. Factors that

can affect the size of the core are: Number of Base Address Registers Used. Turning off

any unused BARs will save resources. Size of the BARs. Setting the BAR to a smaller size

requires more flip-flops. A smaller address spacerequires more flip-flops to decode.

Latency timer. Disabling the latency timer will saveresources. It must be enabled for bursting.

Recommended Design ExperienceThe LogiCORE PCI64 Interface is pre-implemented allowing engineering focus at the unique back-end functions of PCI design. Regardless, PCI is a high-performance systemthat is challenging to implement in any technology, ASIC FPGA. Therefore, previous experience with building higperformance, pipelined FPGA designs using Xilinx impmentation software, TIMESPECs, and guide files is recommended. The challenge to implement a complete PCdesign including back-end functions varies depending oconfiguration and functionality of your application. Contyour local Xilinx representative for a closer review and esmation for your specific requirements.

Figure 1: Block Diagram of Synthesizable Bridge Design for PCI64 LogiCORE Interface, SB07

RESOLVE

TARGET STATE

L o g i C O R E P C I I n t e r f a c e

ADIO

S_CBE

TARGET

CONTROL

INITIATOR

CONTROL

INITIATOR