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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

7.5 15 22.5 30 37.5 45 52.5 60 67.5 75 82.5 90 97.5 105 112.5 120 127.5 135 142.5 150 157.5 165 172.5 180 187.5 195 202.5 210 217.5 225 232.5 240 247.5 255 262.5 270 277.5 285 292.5 300 307.5 315 322.5 330 337.5 345 352.5 360

Sin 0.1305 0.2588 0.3827 0.5 0.6088 0.7071 0.7934 0.8660 0.9239 0.9659 0.9914 1.0 0.9914 0.9659 0.9239 0.8660 0.7934 0.7071 0.6088 0.5 0.3827 0.2588 0.1305 0.0 -0.1305 -0.2588 -0.3827 -0.5 -0.6088 -0.7071 -0.7934 -0.8660 -0.9239 -0.9659 -0.9914 -1.0 -0.9914 -0.9659 -0.9239 -0.8660 -0.7934 -0.7071 -0.6088 -0.5 -0.3827 -0.2588 -0.1305 0.0

Cos 0.9914 0.9659 0.9239 0.8660 0.7934 0.7071 0.6088 0.5 0.3827 0.2588 0.1305 0 -0.1305 -0.2588 -0.3827 -0.5 -0.6088 -0.7071 -0.7934 -0.8660 -0.9239 -0.9659 -0.9914 -1.0 -0.9914 -0.9659 -0.9239 -0.8660 -0.7934 -0.7071 -0.6088 -0.5 -0.3827 -0.2588 -0.1305 0.0 0.1305 0.2588 0.3827 0.5 0.6088 0.7071 0.7934 0.8660 0.9239 0.9659 0.9914 1.0

1 11h 21h 31h 3Fh 4Dh 5Ah 65h 6Eh 75h 7Bh 7Eh 7Fh 7Eh 7Bh 75h 6Eh 65h 5Ah 4Dh 3Fh 31h 21h 11h 0h 91h A1h B1h BFh CDh DAh E5h Eeh F5h FBh Feh FFh FEh FBh F5h EEh E5h DAh CDh BFh B1h A1h 91h 80h

1 16.6 32.9 48.6 63.5 77.3 89.8 100.8 110 117.3 122.7 125.9 127 125.9 122.7 117.3 110 100.8 89.8 77.3 63.5 48.6 32.9 16.6 0 1 + 16.6 1 + 32.9 1 + 48.6 1 + 63.5 1 + 77.3 1 + 89.8 1 + 100.8 1 + 110 1 + 117.3 1 + 122.7 1 + 125.9 1 + 127 1 + 125.9 1 + 122.7 1 + 117.3 1 + 110 1 + 100.8 1 + 89.8 1 + 77.3 1 + 63.5 1 + 48.6 1 + 32.9 1 + 16.6 1+0

2 2 7Eh 7Bh 75h 6Eh 65h 5Ah 4Dh 3Fh 31h 21h 11h 0h 91h A1h B1h BFh CDh DAh E5h EEh F5h FBh FEh FFh Feh FBh F5h Eeh E5h Dah CDh BFh B1h A1h 91h 80h 11h 21h 31h 3Fh 4Dh 5Ah 65h 6Eh 75h 7Bh 7Eh 7Fh 125.9 122.7 117.3 110 100.8 89.8 77.3 63.5 48.6 32.9 16.6 0 1 + 16.6 1 + 32.9 1 + 48.6 1 + 63.5 1 + 77.3 1 + 89.8 1 + 100.8 1 + 110 1 + 117.3 1 + 122.7 1 + 125.9 1 + 127 1 + 125.9 1 + 122.7 1 + 117.3 1 + 110 1 + 100.8 1 + 89.8 1 + 77.3 1 + 63.5 1 + 48.6 1 + 32.9 1 + 16.6 1+0 16.6 32.9 48.6 63.5 77.3 89.8 100.8 110 117.3 122.7 125.9 127


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Title

GEN Document Number

Size B D ate:2

1

R ev 01 Sheet1

Saturday, June 12, 2004

1

of

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DC PK VCC COMP

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8 7 6 5

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C GENN.ASM

;***************************************************************** ;* PWM based sinewave generator, table based ;************************************************************************** .include "8535def.inc" ; Registers definitions ; .def tmp = r16 .def sin_angle = r17 .def cos_angle = r18 .def amp = r19 .def itmph = r20 .def itmp = r21 .def adclb = r22 .def adchb = r23

; (0- 255) ; ; ( 0 -255 )

;************************************************************************** ; Reset and interrupt vectors handlers ; .cseg .org $00 reset_hnd: rjmp start ; .org OVF1addr tim1_hnd: rjmp tim1_ovf .org ADCCaddr rjmp ADC_intr ;.org ADCIaddr ; rjmp ana_comp ;Analog Comparator Handle ;************************** mul******************************************** multb: ; , push amp mula_0: clr itmph ldi itmp,8 lsr amp ;clear result High byte ;init loop counter ;rotate multiplier

mula_1: brcc mula_2 ;carry set add itmph,r0 ; add multiplicand to result High byte mula_2: ror itmph ;rotate right result High byte ror amp ;rotate right result L byte and multiplier dec itmp ;decrement loop counter brne mula_1 ;if not done, loop more pop amp ret ;************************************************************************** ; Timer 1 interrupt handler ; tim1_ovf: push amp ; 1 sbi PORTD, PD2

inc sin_angle inc cos_angle ldi ZL,low(sine_tbl*2) ldi ZH,high(sine_tbl*2) add ZL,sin_angle clr tmp adc ZH, tmp lpm lsl r0 brcc set_ph1 brcs clr_ph1 next1:

;

;

;

rcall multb out OCR1AH, tmp out OCR1AL,itmph ldi ldi add adc lpm lsl ZL,low(sine_tbl*2) ZH,high(sine_tbl*2) ZL,cos_angle ZH, tmp

; ; ;

r0 brcc set_ph2 brcs clr_ph2 out OCR1BH, tmp next2: rcall multb out OCR1BL, itmph rjmp return set_ph1: sbi PORTD,PD0 rjmp next1 clr_ph1: cbi PORTD,PD0 rjmp next1 set_ph2: sbi PORTD,PD1 rjmp next2 clr_ph2: cbi PORTD,PD1 rjmp next2 return: cbi PORTD,PD2 pop amp sbi ADCSR, ADSC reti

; U4 ;

;*************** ***************************** ADC_intr: AD0_1: sbic ADCSR,ADSC ; rjmp AD0_1 in adclb,ADCL lsr adclb ; 10- 8- lsr adclb in adchb,ADCH lsl adchb lsl adchb lsl adchb lsl adchb lsl adchb lsl adchb or adchb,adclb mov amp,adchb ; amp reti ;ana_comp: ; dec amp ;reti ;************************************************************************** ; Reset handler. Initalizes port and Timer 1, and stay in a endless loop ; start: sbi DDRD, PD4 sbi DDRD, PD5 ; Set pin PD4 PD5 as output (is OC1A OC1B pin) sbi DDRD, PD0 sbi DDRD, PD1 ; Set pin PD0 PD1 as output (is ph1 ph2 ) sbi DDRD, PD2 ; Set pin PD2 as output (is trigger clock ) ldi out ldi out tmp,low(RAMEND) SPL,tmp tmp,high(RAMEND) SPH, tmp ; Init Stack pointer

ldi tmp,(1