2.1 8051 Family 2.1 8051 Pin 2.3 8051 Memory 2.4 8051 Timing2 8051
8051 Family Hardware 4K (ROM) 128 (RAM) 8 4 4 2 16 / (full duplex) UART(Universal Asynchronous Receiver & Transmitter) 5 2 Clock Oscillator 64KB 64KB 8 ( )2.1 8051 Family 1. 8051
8051
2. 8051 Family 8051 Core Micro Controller . 8051 : Masking Type ROM . Mask ROM type, OTP(One-Time Programming) type . 8031 : Chip ROM . 8751 : EPROM type ROM 89C51 : Flash Memory type ROM , Erase, Write (Atmel )
2.2 Philips 8051 Family.
2.3 Atmel 8051 Family
2.1 8051
2.2 8051
(Port) 0 (P0.0 - P0.7) : ROM RAM Interface I/O EPROM write .
(Port) 1 (P1.0 - P1.7) : Pull-up 8 (Port). EPROM A0 -A7 .
(Port) 2 (P2.0 - P2.7) : ROM (A8 -A15) Port Interface I/O 1. 8051
(Port) 3 (P3.0 - P3.7) : (Pull-up) 8 ( I/O) 2.4 3
RESET : Master Reset Active HIGH Machine Cycle High .
ALE/ PROG (Address Latch Enable output/ PROGram pulse input ) Memory Interface Latch EPROM ( /PROG ) .
/PSEN (Program Strobe ENable) ROM Data Active LOW Strobe ROM OE(Output Enable) Pin .
(PC) ROM 16bit Register . PC Reset 0000h . / . .
ALU (Arithmetic and Logic Unit ) 8 . - Carry , Carry / - +1, - 1 - / - AND, OR, XOR, Rotate - - Nibble Data Branch
2.3 8051
2.3 8051 Memory 1. Program Data Memory /PSEN : ROM Access /RD, /WR : RAM Access
2. Program Memory (ROM) 64KByte . , ROM /EA(External Access) Pin . Access MOVC/EA=0 :000H~0FFFH(4KB) ROM ( ROM )/EA=1 : 000H~0FFFH ROM
3. Data Memory (RAM)(1) 8051 64[Kbyte] Access Access : MOVX Access H/W /RD, /WR
(2) 8051 RAM : 128 Byte(00H~7FH) SFR (Special Function Register) : 128 Byte (80H~0FFH) MOV Access .
Register Bank - REG. Bank : R0-R7- REG. Bank : PSW() .- REG. Bank Access :
:00H - 7FH 20.1H - 2F.7H (Bit-addressable)
- 30H- 7FH RAM - , Addressing Mode Access
MOV A, 5FH ; MOV R0, #5FH ; MOV A, @R0 ;
(Addressing Mode)8 (address) 128 SFR Access .MOV A, direct ; (Acc) (address)MOV direct, A ; (address) (Acc)< > 8051 (Addressing Mode)8051
MOV ,
(Addressing Mode)Operand Reg. Operand . Register R0 R1 . @ R0, R1 MOV @Rn, #data ; ((Rn)) data ( n = 0 or 1)MOV @Rn, direct ; ((Rn)) (direct address)) MOV R0, #5FH MOV A, @R0
(Addressing Mode)
R0-R7 Bank Byte
MOV A, Rn ; (Acc)(Rn), (n=0 ~ 7)MOV Rn, A ; (Rn)(Acc)
(Immediate) (Addressing Mode) DPTR 8. # .
MOV A, #data ; (ACC) data
(Special Function Register)8051 RAM 80H~F(128) 21 Register.- SFR Port Latch Register P0,P1,P2,P3, PCON,TCON.. Register ACC, B, DPTR, PSW, SP
(Special Function Register)
B Register - 8 bit ACC .
Stack Pointer(SP) - 8 bit (Stack) .
Stack (pushing ) : (SP) . (popping ) : Stack SP .
( RAM) . Reset 07H 08H Stack (60H ) MOV SP, #5FH
PSW(Program Status Word)CPU D0H.
DPTR(Data Pointer Register) 16Bit Register. DPH, DPL 8Bit . (RAM) Address Pointer Timer/Counter TH1, TL1, TH0, TL0, TMOD, TCON Serial Port SBUF, SCON, PCON Interrupt Control IE, IP I/O Port Control P0, P1, P2, P3
2.4 8051
Machine Cycle : CPU 1 machine cycle : 6 , 12 Clock 12[MHz] X-tal 1Machine Cycle 1[usec.] .
1Byte 1Cycle (, INC A) S1 FetchS4 OP Code , Cycle S1 OP Code .
2Byte 1Cycle (, ADD A, #data) S1 OP Code Fetch, S4 Operand .
1Byte 2Cycle ( , INC DPTR ) S1 OP Code Fetch, S4 Cycle S1,S4 Dummy Read.
1Byte 2Cycle MOVX Access . OP Code .
2. (ROM) ROM Hardware Access : /PSEN
(RAM) RAM Hardware Access : /RD, /WR
RAM
RAM
/ (1)
/ (2)
; ARITH4.ASM()ORG 4000HMOV PSW, #08H; BANK 1 ;MOV R0, #9MOV R1, #11;MOV B, R0MOV A, R1MUL AB;MOV R3, AMOV R2, B;MOV PSW, #0H; BANK 0 JMP 0057H; END
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