Download ppt - All-digital RF signal generation using ΔΣ modulation for mobile communication terminals

1PhD Defense (December 7th 2007)

All-digital RF signal generation using ΔΣ modulation for mobile communication

terminals

Antoine Frappé[email protected]

Directeur de Thèse : Andreas Kaiser

Equipe Microélectronique Silicium

http://www.isen.fr/~electronique_lille


Outline

Background

Digital transmitter architecture

ΔΣ modulator system design

Digital transmitter circuit design

Experimental results

Conclusion and future directions


Outline

Background– Worldwide Communications Systems– Ideal Software Radio– State-of-the-art in digital transmitters

Digital transmitter architectureΔΣ modulator system designDigital transmitter circuit designExperimental resultsConclusion and future directions


Worldwide Communications Systems

Each area has its own mobile standards

Broadband standards– Wi-Fi, IEEE802.11

Cordless systems– DECT

Short-range systems– Bluetooth

Europe : GSM900 / DCS1800 / UMTS

United-States : IS-95 / CDMA2000

China : TD-SCDMA

Standards diversity

Gabon : GSM900

Fre-quency

Power

Standard frequency band

channel


UMTS

Worldwide Communications SystemsBi-standard or tri-standard mobile phones

GSM

IS-95

VOICESMSDATAVIDEO

…

Large area needed and high power consumptionNo reconfigurabilityHigh manufacturing cost

Single chip

Design of a reconfigurable RF transmitter IC able to address every standard


Evolution towards ideal software radio

DACDSP


P. Asbeck et al., 2001– Concept of a digital transmitter based on

bandpass ΔΣ modulation and switching PA

Early proposed concept

P. M. Asbeck, L. E. Larson, and I. G. Galton, "Synergistic design of DSP and power amplifiers for wireless communications," IEEE Trans. on Microwave Theory and Techniques, vol. 49, pp. 2163-2169, 2001.


J. Sommarek et al, 2004– Digital IF implementation (175MHz)– ΔΣ bandwidth is 5MHz (channel width)

State-of-the-art in digital transmitters

J. Sommarek, et al., "A digital modulator with bandpass delta-sigma modulator," IEEE ESSCIRC, pp. 159-162, 2004.


Outline

BackgroundDigital transmitter architecture– Digital transmitter concept– Proposed architecture for UMTS– Architecture choices

ΔΣ modulator system designDigital transmitter circuit designExperimental resultsConclusion and future directions


Digital Transmitter Concept

Power-DACDigital Signal

Processing1 bit

VDD = 1V

Switching-mode Power Amplifier– Voltage mode Good efficiency– Implemented with an inverter

Generation of a 1-bit digital RF signal


UMTS standard specifications

WCDMA access mode with Frequency Division Duplex

Emission : 5MHz wide channels at 1.92 – 1.98GHz

EVM < 17.5%Typical transmitter ~ 7-8%

Must be increased by ~10dB for margin


Proposed architecture

30MHz

5MHz

30MHz

Outside-band Noise-shaping

60MHz

UMTS: Fc=1.95GHzFs=3.84MHz 4Fc=7.8GHzLxFs=122.88MHz 2Fc=3.9GHz


Architecture choices (1)

frequency

pow

er

Variable carrier

frequency

ΔΣ-shaped quantization

noise

ΔΣ bandwidth

Analog filter frequency response

Direct upconversionTwo-step upconversion

Standard band

frequency

pow

er

Fixed carrier

frequency

ΔΣ-shaped quantization

noise

ΔΣ bandwidth

Analog filter frequency response

Standard band



IF upconversion– 5MHz channel placed in [-30MHz ; 30MHz]

RF upconversion– [-30MHz ; 30MHz ] band placed around 1.95GHz

EXAMPLE UMTS standard

Digital RF mixerSampling frequency is equal to 4 x fc

Interleaving operation between I and Q channels

– One sample on two is unused on each channel

)2cos( tfc

)2sin( tfc

n = 0,4,8,12,…



Bandpass ΔΣ implementation

Lowpass ΔΣ implementation– Equivalent complexity– Digital mixer on 1 bit– LP ΔΣ sampling frequency is twice lower

I

Q

LP ΔΣ

LP ΔΣ

cs ff 4

cs ff 4n

n

1

1

1

{1,0,-1,0}

{0,1,0,-1}sf

I

QBP ΔΣ

cs ff 4

n

n

n 1

{1,0,-1,0}

{0,1,0,-1}sf

I

Q

LP ΔΣ

LP ΔΣ

cs ff 2

n

n

1

1

1

{1,0,-1,0}

{0,1,0,-1}cf2 cf2

cf4

ΔT

ΔT = 1/4fc


Architectures choices (4)

Synchronized operation– Phase shift issue– Resolved by interpolation

on Q channel

I

Q

LP ΔΣ

LP ΔΣ

cs ff 2

n

n

1

1

1

{1,0,-1,0}

{0,1,0,-1}cf2 cf2

cf4

ΔT

I

Q

LP ΔΣ

LP ΔΣ

cs ff 2

n

n

1

1

1

{1,0,-1,0}

{0,1,0,-1}cf2 cf2

cf4

INT

ΔT’

ΔT’ 2

ΔT’ = 1/2fc

Digital upconverter output spectrum


Digital RF transmitter architecture

Based on ΔΣ modulation and switching-mode power amplification

ΔΣ modulator architecture for UMTS test case– Bandwidth 100MHz– Sampling frequency 3.9GS/s– Around 70dB of SNDR 12 effective bits

~25dB of digital gain control

Conclusion


Outline

Background


ΔΣ modulator system design– Architecture optimization– Implementation strategies






3rd order lowpass ΔΣ modulator Major feedback creates a 40MHz notchOSR=~40

– Bandpass is ~100MHz– Sampling rate is 3.9GS/s

16 bits1 bit


Simulation results

SNDR vs Amplitude level

SNDR (Signal to noise and distortion ratio)

76.6dB

ENOB (Effective number of bits)

~13bits

SFDR (Spurious-free dynamic range)

87.2dB

ACLR@5MHz 76.3dB

ACLR@10MHz 78.4dB

Matlab simulation results

-3dBFS


Architecture optimization

Power-of-two coefficients

Accumulator Integrator (minimize longest path)

Signals quantization (VHDL simulations)


Simulation results

ACLR@5MHz = 74.7dB

ACLR@10MHz = 72.2dB


Implementation issues

Sample rate is 3.9GS/s (~250ps period) Critical path

– 4 signals to add– 2 consecutive adders in the signal path

Classical implementation in 2’s complement– Carry propagation Incompatible with the available period


Implementation strategies

Advantages:– No carry propagation– Several additions at the same time

Disadvantages:– Twice more bits to implement– Full custom design

LSB

MSB

EXAMPLE Addition of 2 BS

Borrow-Save arithmetic



Borrow-Save arithmetic instead of 2’s-complement

No carry propagation and constant-time additions

Maximum delay in critical path is 3.δ(FA)

Design of a logic cell with a delay less than 250ps / 3 ~ 80ps

- Differential dynamic logic cells controlled by 3-phase clocks (DLL)

Sample rate 3.9GS/s

FA

FA

FA

FA

FA

FAFA

FA

FA

250ps period

Borrow-Save arithmetic

Logic comparator



New problem: Sign evaluation needs carry propagation

Non-exact quantization

ACLR @ 5MHz ACLR @ 10MHz

2’s complement 74.7dB 72.2dB

Ideal BS 76.2dB 73.7dB

Truncated BS 68.8dB 67.4dB

Performances remain good with low complexity


Sample rate 3.9GS/s

FA

FA

FA

FA

FA

FAFA

FA

FA F

A

FA

FA

250ps period

Implementation strategiesOutput Signal Precomputation


ΔΣ modulator system designConclusion

Implementation of a very high-speed digital ΔΣ modulator with :

– redundant arithmetic– non-exact quantization– output signal precomputation

Covered by a patent FR0752701 (US application in progress)


Outline

Background



Digital transmitter circuit design– IC block structure and chip overview– ΔΣ core layout




IC block structure


First chip overview in 90nm CMOS

(Without M7)

Compensation cell

Q inputsVddDS

Vdd

CL

K

Vdd

AN

A

Clock shaper & DLL

ΔΣ core & Sample rate conversion

Clock tree (adjusted to equalize the delay)

Output buffers

I inputs

Multiplexer

3mm

1mm


ΔΣ core layout

Area :– 350 x 160µm² = 0.056mm²

~8000 transistors

Slice


Slice example layout

Full Adder


Dynamic logic style

Carry evaluation

Sum evaluation Sum dynamic logic

Carry dynamic logic

Sum (or carry) calculation block :

Can be modified to obtain any logic function


Outline

Background




Experimental results– First and second chip overview– Test setup– Headlines of measurement results– Comparison with other works



First chip test & Measurement results

Measurement results on output stages

2 main issues for core functionality:– Oscillations on power and ground inside the chip– Bad initialization of the delta-sigma core

Corrections are implemented on a second chip in 90nm CMOS


Second chip overview (90nm CMOS)


Test setup

Arbitrary Waveform Generator (AWG420) or Pattern Generator

Matlab File with WCDMA signal

.m.m

FPGA CycloneII with upconverting &

filtering software

DUT

IQ signals @ 121.875MS/s+ data clocks

IQ signals @ 243.75MS/s+ data clocks

10MHz reference

7.8GHz frequency synthesizer

Mas

ter

cloc

kSpectrum analyzer

orDigitizing oscilloscope

Bias tee

DC blockBalun


Headlines of measurement results

Full functionality up to 4GHz (instead of the expected 8GHz rate)– Standard bands addressed up to 1GHz– Maximum bandwidth is 50MHz (proportional to the sampling rate)

RF output spectrum RF output spectrum


SNDR measurement

Input : sine wave

SIMULATIONof the ΔΣ core

MEASUREMENT

~20dB


Digital core functionality

MUX

4fcExample of an output spectrum with a DC input and a 2.5GHz clock (single-ended output)

Digital data stream

Analog output

Jitter = 13.24psRMS

Eye diagram at the RF output


UMTS test case (fc=1.95GHz)– Measurements at a 2.6GHz clock frequency

Fundamental band at 650MHz Image band at 1.95GHz (degraded results) Relative bandwidth is 30MHz

fsfrequency

power

f s/4 3fs/4

sinx/x

Relative bandwidth

GHz

fMHzBW s

8.7

100

10.45dB

Measurement results (2.6GHz clock) (1)



650MHzfundamental band

1.95GHz image band

5MHz QPSK channel with -3dBFS power

+1

0M

Hz

+5

MH

z

-5M

Hz

-10M

Hz

+1

0M

Hz

+5

MH

z

-5M

Hz

-10M

Hz

5MHz

5MHz

ACPR~52dB

ACPR~44dB



5MHz QPSK channel with 8.1dB PAPR

ACPR

VHDL SIMULATIONS :

ACPR max = 74.7dB

ACPR vs amplitude for fundamental and image bands



650MHz band 1.95GHz band

5MHz QPSK channelwith -3dBFS power

UMTS EVM requirements : <17.5%

Typical transmitter EVM : 7~8%

EVM


Power consumption

0

0,2

0,4

0,6

0,8

1

1,2

1,4

0 0,5 1 1,5 2 2,5 3 3,5 4

Clock Frequency (GHZ)

Vo

lta

ge

(V

)

0

20

40

60

80

100

120

140

160

180

200

Po

we

r c

on

su

mp

tio

n (

mW

)

Voltage (V)

Power consumption (mW scaled to 1V)

Power consumption (mW)

Tendency curve


Summary of measurements

2.6GHz clock

650MHz channel1.95GHz channel

(image)

ACPR (5MHz wide channel) 53.6dB 44.3dB

Max Channel Power -3.9dBm -15.8dBm

EVM 1.24% 3.42%

Output jitter 13.2psRMS

SNDR (BW = 30MHz) 53.6dB 40.3dB

In-band noise floor -129.5dBm/Hz -129.4dBm/Hz

Peak output power 3.1dBm -8.59dBm

Power consumption

total 69mW (1V)

output stages 39mW

core 2 × 15mW


Comparison with other works

This work [1]

Max Clock Frequency 4GHz clock 700MHz clock

Max Carrier Frequency 1GHz channel3GHz channel

(image)175MHz channel

Max Adjacent ACPR (5MHz wide channel)

55dB @ 500MHz clock

44.5dB @ 2.4GHz clock

50.26dB

Max Alternate ACPR (5MHz wide channel)

57.2dB @ 500MHz clock

47dB @ 2.4GHz clock

40.27dB

Total Power Consumption25mW (1V) @ 700MHz clock69mW (1V) @ 2.6GHz clock

139mW (1.5V) @ 700MHz clock

Total Silicon Area 3.2mm² (core: 0.06mm²) 5.2mm² (core?)

Process 90nm CMOS (GP) 130nm CMOS

[1] J. Sommarek, et al., "A digital modulator with bandpass delta-sigma modulator," IEEE ESSCIRC, pp. 159-162, 2004.



[2] Digital-to-RF converter (DRFC)– 2nd order MASH ΔΣ modulator providing 3-bit input signals

SNR=30dB over 200MHz

– Current-mode output stage– ΔΣ sampling frequency is 2.5GS/s simple structure

[2] A. Jerng and C. G. Sodini, "A Wideband Delta-Sigma Digital-RF Modulator for High Data Rate Transmitters," IEEE J. Solid-State Circuits, vol. 42, pp. 1710-1722, 2007.



[3] DRFC with 10-bit 307.2MS/s oversampled input signals– 41/56dB ACPR (for 5MHz channels and 25dBm output power)– EVM<2% over 60dB of control range

[3] P. Eloranta, et al., "A WCDMA Transmitter in 0.13µm CMOS Using Direct-Digital RF Modulator," ISSCC Dig. Tech. Papers, pp. 340-341, 2007.


Outline

Background





Conclusion and future directions– Conclusion and discussion– Future work


Conclusion

First reported transmitter chain using 1-bit digital RF delta-sigma modulation

– Borrow-Save arithmetic– Non-exact quantization

Prototype demonstration in 90nm CMOS– Measurement results for a clock frequency until 4GHz

Good performances of the digital ΔΣ modulator Analog RF output performances to be improved

– For UMTS Possibility to use the first image band with a 2.6GHz clock with slightly degraded results


Future directions (1)

Integration inside a whole transmitter chain– European IST MOBILIS project

Higher frequency functionality?– Analysis of the critical issues (clock input, logic, parasitics…)– Solutions for higher frequency operation

Implementation of a prototype in a faster technology (65nm CMOS or 65nm SOI CMOS)


Future directions (2)

Reduction of out-of-band noise– Higher order ΔΣ modulators– Complex ΔΣ modulator architectures– Digital RF filtering

Study of reconfigurability issues

Discussion on output stage– Voltage-mode vs. current-mode– Single-bit vs. multi-bit


Publications & ConferencesInternational Conferences

– A. Frappé, B. Stefanelli, A. Flament, A. Kaiser, A. Cathelin, “An all-digital delta-sigma RF signal generator for mobile communication transmitters in 90nm CMOS”, to be submitted to RFIC 2008.

– A. Frappé, A. Flament, B. Stefanelli, A.Kaiser, A. Cathelin, R. Daouphars, “Design techniques for very high-speed digital delta-sigma modulators aimed at all-digital RF transmitters”, IEEE International Conference on Electronics, Circuits and Systems, ICECS 2006, Nice.

– A. Frappé, A. Flament, B. Stefanelli, A. Cathelin, A. Kaiser, “All-digital RF signal generation for software defined radios”, IEEE International Conference on Circuits and Systems for Communications, ICCSC 2006, Bucarest, pp 171-174.

– C. Nsiala Nzéza, A. Frappé, J. Gorisse, A. Flament, B. Stefanelli, A. Cathelin, A. Kaiser, “Direct digital RF signal generation for Software-Defined Radio transmitters using reconfigurable Delta-Sigma modulators”, Proceedings of the 11th International Symposium on Microwave and Optical Technology (ISMOT-2007), Monte Porzio Catone, Italy, December 2007, to appear.

– C. Nsiala Nzéza, J. Gorisse, A. Frappé, A. Flament, A. Kaiser, A. Cathelin, « Reconfigurable digital delta-sigma modulator synthesis for digital wireless transmitters », Proceedings of the IEEE European Conference on Circuit Theory and Design, ECCTD 2007, Sevilla, Spain, August 2007, pp. 480-483.

National Conferences and Symposiums– A. Frappé, A. Flament, B. Stefanelli, A. Cathelin, A. Kaiser, “All-digital RF signal generation for software

defined radio transmitters”, Colloque du GDR SoC-SiP 2007, Paris.– C. Nsiala Nzéza, A. Frappé, J. Gorisse, A. Flament, B. Stefanelli, A. Kaiser, “Reconfigurable RF signal

generation for software radio transmitters”, Actes du 8ème colloque sur le Traitement Analogique de l’Information, du Signal et ses Applications (TAISA’2007), Lyon, France, Octobre 2007, pp. 89-92..

– A. Flament, A. Frappé, B. Stefanelli, A. Kaiser, A. Cathelin, « Convertisseur numérique analogique 1 bit à 7,8Gech/s pour émetteurs RF numériques en technologie CMOS 90nm », in TAISA 2006, Strasbourg, pp 115-118.

Patents– A. Frappé, A. Kaiser, A. Cathelin, « Procédé de traitement d’un signal numérique au sein d’un

modulateur delta-sigma, et modulateur delta-sigma numérique correspondant », FR0752701 filled on January 16th 2007. US application filing request.