7/28/2019 CSE2304_Lecture08_chp03(3)
1/25
Chapter 3
Arithmetic for Computers
7/28/2019 CSE2304_Lecture08_chp03(3)
2/25
Next: Integer Addit ion 2
Arithmetic for Computers
Operations on integers Addition and subtraction
Multiplication and division
Dealing with overflow
3.1Introduction
7/28/2019 CSE2304_Lecture08_chp03(3)
3/25
Next: Integer Subtraction 3
Integer Addition
Example: 7 + 6
3.2Addition
andSubtraction
Overflow if result out of range
Adding +ve and ve operands, no overflow
Adding two +ve operands Overflow if result sign is 1
Adding two ve operands
Overflow if result sign is 0
7/28/2019 CSE2304_Lecture08_chp03(3)
4/25
Next: Dealing with Overflow 4
Integer Subtraction
Add negation of second operand
Example: 7 6 = 7 + (6)
+7: 0000 0000 0000 01116: 1111 1111 1111 1010
+1: 0000 0000 0000 0001 Overflow if result out of range
Subtracting two +ve or two ve operands, no overflow
Subtracting +ve from ve operand
Overflow if result sign is 0
Subtracting ve from +ve operand
Overflow if result sign is 1
7/28/2019 CSE2304_Lecture08_chp03(3)
5/25
Next: Arithmetic for Multimedia 5
Dealing with Overflow
Some languages (e.g., C) ignore overflow Use MIPS addu, addui, subu instructions
Other languages (e.g., Ada, Fortran)require raising an exception Use MIPS add, addi, sub instructions On overflow, invoke exception handler
Save PC in exception program counter (EPC)register
J ump to predefined handler address
mfc0 (move from coprocessor reg) instruction canretrieve EPC value, to return after corrective action
7/28/2019 CSE2304_Lecture08_chp03(3)
6/25
Next: Mult iplication 6
Arithmetic for Multimedia
Graphics and media processing operateson vectors of 8-bit and 16-bit data
Use 64-bit adder, with partitioned carry chain
Operate on 88-bit, 416-bit, or 232-bit vectors
SIMD (single-instruction, multiple-data)
Saturating operations
On overflow, result is largest representable
value c.f. 2s-complement modulo arithmetic
E.g., clipping in audio, saturation in video
7/28/2019 CSE2304_Lecture08_chp03(3)
7/25Next: Multip lication Hardware 7
Multiplication
Start with long-multiplication approach
1000 1001
100000000000
10001001000
Length of product isthe sum of operandlengths
multiplicand
multiplier
product
3.3Multiplication
7/28/2019 CSE2304_Lecture08_chp03(3)
8/25
Next: One Example 8
Multiplication Hardware
Initially 0
7/28/2019 CSE2304_Lecture08_chp03(3)
9/25
Multiplication Example
4-bit multiplication: 01112 x 01102 8-bit registers for multiplicand and product
Multiplicand is shifted to left by 1 bit each time
4-bit register for multiplier, shifted to right by 1 bit each time
Shift is done after addition
Step Multiplier Multiplicand Product
Start 0110 0000 0111 0000 0000
1 0011 0000 1110 +0000 0000=0000 0000
2 0001 0001 1100 +0000 1110
=0000 1110
3 0000 0011 1000 +0001 1100=0010 1010
4 0000 0111 0000 +0000 0000=0010 1010
Next: Optimized Multipl ier 9
7/28/2019 CSE2304_Lecture08_chp03(3)
10/25
Next: Example 10
Optimized Multiplier
Perform steps in parallel: add/shift
One cycle per partial-product addition
Thats ok, if frequency of multiplications is low
7/28/2019 CSE2304_Lecture08_chp03(3)
11/25
Optimized Multiplier Example
4-bit multiplication: 01112
x 01102
4-bit register for multiplicand
No shift
8-bit register for product
Only the higher half of the product is added withmultiplicand
Only the higher half is replaced by the sum
After addition, all bits are shifted to right by 1 bit
The carry is shifted in from the left end
Multiplier is stored in the lower half of the productinitially
Next: Example (cont .) 11
7/28/2019 CSE2304_Lecture08_chp03(3)
12/25
Example (cont.)
Step Multiplicand Addition Product
Start 0111 0000 0110
1 0111 0000+0000
=00000
00000 0110
>> 1 = 0000 0011
2 0111 0000+0111
=00111
00111 0011
>> 1 = 0011 1001
3 0111 0011+0111
=01010
01010 1001
>> 1 = 0101 0100
4 0111 0101+0000
=00101
00101 0100
>> 1 = 0010 1010
Next: Faster Mult iplier 12
7/28/2019 CSE2304_Lecture08_chp03(3)
13/25
Next: MIPS Multiplication 13
Faster Multiplier
Uses multiple adders Cost/performance tradeoff
Can be pipelined
Several multiplication performed in parallel
7/28/2019 CSE2304_Lecture08_chp03(3)
14/25
7/28/2019 CSE2304_Lecture08_chp03(3)
15/25
Next: Steps in Divis ion 15
Division
Check for 0 divisor
Long division approach If divisor dividend bits
1 bit in quotient, subtract
Otherwise 0 bit in quotient, bring down next
dividend bit
10011000 1001010
-1000101011010-1000
10
n-bit operands yield n-bitquotient and remainder
quotient
dividend
remainder
divisor
3.4Division
7/28/2019 CSE2304_Lecture08_chp03(3)
16/25
Steps in Division
Check for 0 divisor
Long division approach
As shown in the previous slide
Restoring division
Do the subtract, and if remaindergoes < 0, add divisor back
Signed division
Divide using absolute values
Adjust sign of quotient and remainderas required
Next: Another look 16
7/28/2019 CSE2304_Lecture08_chp03(3)
17/25
Another look
>> 1 / step Remainder Quotient
0: 0000100000000000 00000000010010101: 0000010000000000 0000000001001010 02: 0000001000000000 0000000001001010 003: 0000000100000000 0000000001001010 0004: 0000000010000000 0000000001001010 0000
5: 0000000001000000 0000000001001010 00001-00000000010000000000000001000000 0000000000001010 00001
6: 0000000000100000 0000000000001010 0000107: 0000000000010000 0000000000001010 00001008: 0000000000001000 0000000000001010 00001001
-00000000000010000000000000001000 0000000000000010
Next: Division Hardware 17
7/28/2019 CSE2304_Lecture08_chp03(3)
18/25
Next: Example 18
Division Hardware
Initially dividend
Initially divisorin left half
7/28/2019 CSE2304_Lecture08_chp03(3)
19/25
Example of 4-bit Division 4-bit division: 01112 / 00102
The divisor register is shifted to right by 1 bitbefore subtraction The remainder register is updated if it is greater than the divisor
Subtract, and restore if necessary
The quotient register is shifted to left
Step Quotient Divisor Remainder
Start 0000 0010 0000 0000 0111
1 0000 0001 0000 0000 0111
2 0000 0000 1000 0000 0111
3 0000 0000 0100 0000 0111- 0000 0100
=0000 0011
4 0001 0000 0010 0000 0011- 0000 0010
=0000 0001
5 0011 0000 0010 Done
Next: 6-bit Example 19
7/28/2019 CSE2304_Lecture08_chp03(3)
20/25
Example of 6-bit Division
6-bit division: 1101112 / 0100102
Step Quotient Divisor Remainder
Start 00 0000 0100 1000 0000 0000 0011 0111
1 00 0000 0010 0100 0000 0000 0011 0111
2 00 0000 0001 0010 0000 0000 0011 0111
3 00 0000 0000 1001 0000 0000 0011 01114 00 0000 0000 0100 1000 0000 0011 0111
5 00 0000 0000 0010 0100 0000 0011 0111- 0000 0010 0100
=0000 0001 0011
6 00 0001 0000 0001 0010 0000 0001 0011- 0000 0001 0010
=0000 0000 0001
7 00 0011 0000 0000 1001 DONE
Next: Optimized Divider 20
7/28/2019 CSE2304_Lecture08_chp03(3)
21/25
Next: 4-bit Example 21
Optimized Divider
One cycle per partial-remainder subtraction Looks a lot like a multiplier!
Same hardware can be used for both
7/28/2019 CSE2304_Lecture08_chp03(3)
22/25
Example of Optimized Divider 4-bit division: 01112 / 00102
The divisor register has 4 bits and does not change
Always 00102
The remainder register has 8 bits (0-extended dividend)
Shift to left by 1 bit in each iteration
Only the higher half (red bits) participates in subtraction
New quotient bit is shifted in from the right end
In the end, the higher half is the remainder and the lower half is the quotient
Step After shi ft left Remainder after each step
Start 0000 0111
1 0000 111? 0000 1110
2 0001 110? 0001 1100
3 0011 100? 0011 1000- 0010 0000
=0001 1001
4 0011 001? 0011 0000- 0010 0000
=0001 0011
Next: 6-bit Example 22
Positive after -00102?
7/28/2019 CSE2304_Lecture08_chp03(3)
23/25
6-bit division: 1101112 / 0100102
The divisor register has 6 bits and does not change Always 0100102
Step After shi ft left Remainder after each step
Start 0000 0011 01111 0000 0110 111? 0000 0110 1110
2 0000 1101 110? 0000 1101 1100
3 0001 1011 100? 0001 1011 1000
4 0011 0111 000? 0011 0111 0000
5 0110 1110 000? 0010 0110 0001
6 0100 1100 001? 0000 0100 0011
12-bit register
Remainder Quotient
Next: Faster Divis ion 23
7/28/2019 CSE2304_Lecture08_chp03(3)
24/25
Next: MIPS Divis ion 24
Faster Division
Cant use parallel hardware as in multiplier Subtraction is conditional on sign of remainder
Faster dividers (e.g. SRT devision)generate multiple quotient bits per step
Still require multiple steps
7/28/2019 CSE2304_Lecture08_chp03(3)
25/25
25
MIPS Division
Use HI/LO registers for result
HI: 32-bit remainder
LO: 32-bit quotient
Instructions
div rs, rt / divu rs, rt
No overflow or divide-by-0 checking Software must perform checks if required
Use mfhi, mflo to access result