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8/18/2019 Ind Assignment - compiler

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MITS

C A C

D. A H • S -/6 • FTMK, UTM

A

INSTRUCTIONS

(i). This task is an individual work

(ii). Students are required to submit the answer (either handwritten or typed)

(iii). Students are required to submit the assignment on st of April 6, before

pm.

Question

A computer system has a cache with the size of 6 blocks. Consider the following re-

peating sequence of addresses in hexadecimal.

8 C 8 C 8 8 88 8C 8 C 8 C 8 C

If Least Recently Used (LRU) algorithm is used as th replacement algorithm, nd the

number of misses for each cache organization given the above sequence of addresses:

. direct mapped organization with block size = word

. fully associative organization with block size = words

. two-way set associative organization with block size = words

. direct mapped cache organization with block size = words


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Assignment MITS

Question

Consider the following parameters for a virtual memory system:

Virtual Memory Address Space Phyical DRAM installed Virtual Page Size

250 bytes GB KB

. Calculate the number of bits for the physical address

. Find the maximum number of virtual pages in the system

. Find the number of physical pages for the system

. Calculate the number of bits for the virtual and physical page numbers

. Find the number of page table entries in the system page table.

Question

Given a -bit operating system, -KB pages and GB of RAM:

. Find the size of the virtual address and the physical address.

. Given the initial TLB for the above virtual memory system, nd the virtual address

for the following address:

xA8, xDAD, xA8

Virtual Page Frame Page Valid Bit

6

Dr. Aslinda Hassan


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Assignment MITS

Question

Consider the following code fragment:

Loop: ld R1 , 0 ( R2 ) # l oa d R1 f ro m a dd re ss 0+ R2

da dd i R1 , R1 , 1 # R 1= R1 + 1

sd R1 , 0 ( R2 ) # s to re R1 at a dd re ss 0+ R2

da dd i R2 , R2 , 4 # R 2= R2 + 4

d su b R4 , R3 , R2 # R 4= R3 - R 2

6 bnez R 4 , L oo p # b ra nc h to L oo p if R4 ! =0

. Data hazards are caused by data dependences in the code. List all of the data

dependences in the code above. Record the register, source instruction, and des-

tination instruction; for example, there is a data dependency for register R fromthe LD to the DADDI.

. Show the timing of this instruction sequence for the -stage RISC pipeline without

any forwarding or bypassing hardware. However, it is assumed that a register read

and a write in the same clock cycle "forwards" through the register le, as shown

in gure from Lecture- notes (Slide ). If all memory references take cycle, nd

the number of clock cycles needed for this loop to be executed

Use a pipeline timing chart as shown in Slide of Lecture . Assume that the

branch is handled by ushing the pipeline. (Note: Remember to include any stallthat occurs during the execution of the above code fragment in the pipeline timing

chart)

. Show the timing of this instruction sequence for the -stage RISC pipeline with full

forwarding and bypassing hardware. If all memory references take cycle, nd

the number of clock cycles needed for this loop to be executed. Assume that the

branch is handled by ushing the pipeline.

Dr. Aslinda Hassan