January 2011 Doc ID 18432 Rev 1 1/15
15
STD96N3LLH6N-channel 30 V, 0.0037 Ω, 80 A, DPAK
STripFET™ VI DeepGATE™ Power MOSFET
Features
■ RDS(on) * Qg industry benchmark
■ Extremely low on-resistance RDS(on)■ High avalanche ruggedness
■ Low gate drive power losses
Application■ Switching applications
– Automotive
DescriptionThis product is an N-channel Power MOSFET that utilizes the 6th generation of design rules of ST’s proprietary STripFET™ technology, with a new gate structure. The resulting Power MOSFET exhibits the lowest RDS(on) in all packages.
Figure 1. Internal schematic diagram
Type VDSS RDS(on) max ID
STD96N3LLH6 30 V 0.0042 Ω 80 A
DPAK
1
3
AM01474v1
D (TAB or 2)
G(1)
S(3)
Table 1. Device summary
Order codes Marking Package Packaging
STD96N3LLH6 96N3LLH6 DPAK Tape and reel
www.st.com
http://www.st.com
Contents STD96N3LLH6
2/15 Doc ID 18432 Rev 1
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STD96N3LLH6 Electrical ratings
Doc ID 18432 Rev 1 3/15
1 Electrical ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
VDS Drain-source voltage (VGS = 0) 30 V
VGS Gate-source voltage ± 20 V
ID (1)
1. Limited by wire bonding.
Drain current (continuous) at TC = 25 °C 80 A
ID Drain current (continuous) at TC = 100 °C 61 A
IDM (2)
2. Pulse width limited by safe operating area.
Drain current (pulsed) 320 A
PTOT Total dissipation at TC = 25 °C 70 W
Derating factor 0.47 W/°C
EAS (3)
3. Starting Tj = 25°C, IAV = 55 A, L = 0.1 mH
Single pulse avalanche energy 150 mJ
Tstg Storage temperature -55 to 175 °C
Tj Max. operating junction temperature 175 °C
Table 3. Thermal data
Symbol Parameter Value Unit
Rthj-case Thermal resistance junction-case max 2.14 °C/W
Rthj-amb Thermal resistance junction-ambient max 100 °C/W
Rthj-pcb(1)
1. When mounted on FR-4 board of 1 inch2, 2 oz Cu.
Thermal resistance junction-pcb max 35 °C/W
Tl Maximum lead temperature for soldering purpose 275 °C
Electrical characteristics STD96N3LLH6
4/15 Doc ID 18432 Rev 1
2 Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 4. Static
Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSSDrain-source breakdown Voltage
ID = 250 µA, VGS= 0 30 V
IDSSZero gate voltage drain current (VGS = 0)
VDS = 30 V
VDS = 30 V, Tc = 125 °C
1
10
µA
µA
IGSSGate body leakage current
(VDS = 0)VGS = ± 20 V ±100 nA
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 1 2.5 V
RDS(on)Static drain-source on resistance
VGS = 10 V, ID = 40 A 0.0037 0.0042 Ω
VGS = 5.5 V, ID = 40 A 0.0055 0.007 Ω
Table 5. Dynamic
Symbol Parameter Test conditions Min Typ. Max. Unit
CissCossCrss
Input capacitance
Output capacitance
Reverse transfer capacitance
VDS = 25 V, f=1 MHz,
VGS = 0-
2200
400280
-
pF
pFpF
QgQgsQgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 15 V, ID = 80 A
VGS = 4.5 V
Figure 13-
20
8.2
7.5
-
nC
nC
nC
Qgs1
Qgs2
Pre Vth gate-to-source charge
Post Vth gate-to-source charge
VDD = 15 V, ID = 80 A
Figure 18-
3.4
6.2-
nC
nC
RG Gate input resistance
f = 1 MHz gate biasBias = 0 test signal
level = 20 mV
open drain
- 1 - Ω
STD96N3LLH6 Electrical characteristics
Doc ID 18432 Rev 1 5/15
Table 6. Switching on/off (inductive load)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on)tr
Turn-on delay time
Rise time
VDD = 15 V, ID = 40 A,
RG = 4.7 Ω, VGS = 5 VFigure 12
-19
91-
ns
ns
td(off)tf
Turn-off delay time
Fall time
VDD = 15 V, ID = 40 A, RG = 4.7 Ω, VGS = 5 VFigure 12
-24.5
23.4-
ns
ns
Table 7. Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
ISDISDM
(1)
1. Pulse width limited by safe operating area
Source-drain current
Source-drain current (pulsed)-
80
320
A
A
VSD(2)
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Forward on voltage ISD = 40 A, VGS = 0 - 1.1 V
trrQrr
IRRM
Reverse recovery time
Reverse recovery chargeReverse recovery current
ISD = 80 A, di/dt = 100 A/µs,
VDD = 24 V
Figure 14
-
28.6
22.81.6
ns
nCA
Electrical characteristics STD96N3LLH6
6/15 Doc ID 18432 Rev 1
2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance
Figure 4. Output characteristics Figure 5. Transfer characteristics
Figure 6. Normalized BVDSS vs temperature Figure 7. Static drain source on resistance
ID
100
10
1
0.10.1 1 VDS(V)10
(A)
Opera
tion i
n this
area
is
Limite
d by m
ax R
DS(on
)
100µs
1ms
10msTj=175°CTc=25°C
Sinlgepulse
AM03376v1
10-5
10-4
10-3 10
-210
-1tp(s)
10-2
10-1
K
0.2
0.05
0.02
0.01
0.1
Zth=k Rthj-cδ=tp/τ
tp
τSingle pulse
δ=0.5
280dpc
ID
150
100
50
00 4 VDS(V)
(A)
2
200
250
VGS=10V
3V
4V
5V
6V7V300
AM03379v1ID
150
100
50
00 4 VGS(V)
(A)
2
200
250
VDS=2V
300
86
AM03380v1
BVDSS
-55 -5 TJ(°C)
(norm)
-30 7020 45 950.90
0.95
1.00
1.05
120 145
@250µA
AM03381v1RDS(on)
3
2
1
00 20 ID(A)
(mΩ)
10 30
4
5
6
7 VGS=10V
40
AM03382v1
STD96N3LLH6 Electrical characteristics
Doc ID 18432 Rev 1 7/15
Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations
Figure 10. Normalized gate threshold voltage vs temperature
Figure 11. Normalized on resistance vs temperature
VGS
6
4
2
00 10 Qg(nC)
(V)
40
8
20 30
10
VDD=15V
ID=80A
50
12
AM03378v1 C
1000
1005 15 VDS(V)
(pF)
10 20
Ciss
Coss
Crss
20
AM03377v1
VGS(th)
0.8
0.6
0.2
0-55 -5 TJ(°C)
(norm)
-30
1.0
7020 45 95 120 145
0.4
1.2@250µA
AM03383v1 RDS(on)
1.6
1.4
1.0
0.6-55 20 TJ(°C)
(norm)
-5 9545 70 145120-30
0.8
1.2
1.8 VGS=10VID=40A
AM03384v1
Test circuits STD96N3LLH6
8/15 Doc ID 18432 Rev 1
3 Test circuits
Figure 12. Switching times test circuit for resistive load
Figure 13. Gate charge test circuit
Figure 14. Test circuit for inductive load switching and diode recovery times
Figure 15. Unclamped inductive load test circuit
Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform
AM01468v1
VGS
PW
VD
RG
RL
D.U.T.
2200
µF3.3µF
VDD
AM01469v1
VDD
47kΩ 1kΩ
47kΩ
2.7kΩ
1kΩ
12V
Vi=20V=VGMAX2200µF
PW
IG=CONST100Ω
100nF
D.U.T.
VG
AM01470v1
AD
D.U.T.
SB
G
25 Ω
A A
BB
RG
G
FASTDIODE
D
S
L=100µH
µF3.3 1000
µF VDD
AM01471v1
Vi
Pw
VD
ID
D.U.T.
L
2200µF
3.3µF VDD
AM01472v1
V(BR)DSS
VDDVDD
VD
IDM
ID
AM01473v1
VDS
ton
tdon tdoff
toff
tftr
90%
10%
10%
0
0
90%
90%
10%
VGS
STD96N3LLH6 Test circuits
Doc ID 18432 Rev 1 9/15
Figure 18. Gate charge waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd
Package mechanical data STD96N3LLH6
10/15 Doc ID 18432 Rev 1
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
Table 8. DPAK (TO-252) mechanical data
Dim.mm
Min. Typ. Max.
A 2.20 2.40
A1 0.90 1.10
A2 0.03 0.23
b 0.64 0.90
b4 5.20 5.40
c 0.45 0.60
c2 0.48 0.60
D 6.00 6.20
D1 5.10
E 6.40 6.60
E1 4.70
e 2.28
e1 4.40 4.60
H 9.35 10.10
L 1
L1 2.80
L2 0.80
L4 0.60 1
R 0.20
V2 0° 8°
STD96N3LLH6 Package mechanical data
Doc ID 18432 Rev 1 11/15
Figure 19. DPAK (TO-252) drawing
0068772_G
Packaging mechanical data STD96N3LLH6
12/15 Doc ID 18432 Rev 1
5 Packaging mechanical data
Figure 20. DPAK footprint(a)
Table 9. DPAK (TO-252) tape and reel mechanical data
Tape Reel
Dim.mm
Dim.mm
Min. Max. Min. Max.
A0 6.8 7 A 330
B0 10.4 10.6 B 1.5
B1 12.1 C 12.8 13.2
D 1.5 1.6 D 20.2
D1 1.5 G 16.4 18.4
E 1.65 1.85 N 50
F 7.4 7.6 T 22.4
K0 2.55 2.75
P0 3.9 4.1 Base qty. 2500
P1 7.9 8.1 Bulk qty. 2500
P2 1.9 2.1
R 40
T 0.25 0.35
W 15.7 16.3
a. All dimension are in millimeters
6.7
1.6
1.6
2.3
2.3
6.7 1.8 3
AM08850v1
STD96N3LLH6 Packaging mechanical data
Doc ID 18432 Rev 1 13/15
Figure 21. Tape for DPAK (TO-252)
Figure 22. Reel for DPAK (TO-252)
P1A0 D1
P0
F
W
E
D
B0K0
T
User direction of feed
P2
10 pitches cumulativetolerance on tape +/- 0.2 mm
User direction of feed
R
Bending radius
B1
For machine ref. onlyincluding draft andradii concentric around B0
AM08852v1
Top covertape
A
D
B
Full radius G measured at hub
C
N
REEL DIMENSIONS
40mm min.
Access hole
At sl ot location
T
Tape slot in core fortape start 25 mm min.width
AM08851v2
Revision history STD96N3LLH6
14/15 Doc ID 18432 Rev 1
6 Revision history
Table 10. Document revision history
Date Revision Changes
27-Jan-2011 1 First release.
STD96N3LLH6
Doc ID 18432 Rev 1 15/15
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Figure 1. Internal schematic diagramTable 1. Device summary1 Electrical ratingsTable 2. Absolute maximum ratingsTable 3. Thermal data
2 Electrical characteristicsTable 4. StaticTable 5. DynamicTable 6. Switching on/off (inductive load)Table 7. Source drain diode2.1 Electrical characteristics (curves)Figure 2. Safe operating areaFigure 3. Thermal impedanceFigure 4. Output characteristicsFigure 5. Transfer characteristicsFigure 6. Normalized BVDSS vs temperatureFigure 7. Static drain source on resistanceFigure 8. Gate charge vs gate-source voltageFigure 9. Capacitance variationsFigure 10. Normalized gate threshold voltage vs temperatureFigure 11. Normalized on resistance vs temperature
3 Test circuitsFigure 12. Switching times test circuit for resistive loadFigure 13. Gate charge test circuitFigure 14. Test circuit for inductive load switching and diode recovery timesFigure 15. Unclamped inductive load test circuitFigure 16. Unclamped inductive waveformFigure 17. Switching time waveformFigure 18. Gate charge waveform
4 Package mechanical dataTable 8. DPAK (TO-252) mechanical dataFigure 19. DPAK (TO-252) drawing
5 Packaging mechanical dataTable 9. DPAK (TO-252) tape and reel mechanical dataFigure 20. DPAK footprintFigure 21. Tape for DPAK (TO-252)Figure 22. Reel for DPAK (TO-252)
6 Revision historyTable 10. Document revision history