23-Sep-05 EM 6021 Advance VLSI Design
Perancangan IC Digital
dengan VHDL
Dr. Trio Adiono
Waris Santosa
•VHDL-2
23-Sep-05 EM 6021 Advance VLSI Design
Outline
• Pendahuluan
• Pemodelan Behavioral dan Struktural
• Multiplexer
• Decoder
• Encoder
• Code Converter
• Comparator
23-Sep-05 EM 6021 Advance VLSI Design
1 Pendahuluan
Suatu Rancangan dapat
modelkan secara
Hirarki.
Model Hirarki dilakukan
berdasar pada struktur
VHDL yang sama untuk
masing-masing bagian
hirarki, yang tersusun
oleh :
– Entity
– Architecture
– Configuration
TOP Design
A B C
D
E
23-Sep-05 EM 6021 Advance VLSI Design
2 Pemodelan Behavioral dan Struktural
Pemodelan Behavioral
• dilakukan denganmendeskripsikanrancangan dalam fungsidan kinerjanya.
• Rancangan dikodekanseperti suatu balck box
• Kode VHDL dituliskansedemikian rupasehinggamembangkitkan sinyaloutput tertentu untuksinyal–sinyal input tertentu.
Contoh:
Entity and2 ISport (a,b : IN bit;
c : OUT bit);end and2;
architecture and2_behave of and2 isbegin
c <= a and b;end and2_behave;
23-Sep-05 EM 6021 Advance VLSI Design
2.1 Pemodelan Struktural
Pemodelan Struktural• Model disusun dengan
komponen-komponen.
• semua jenis komponenyang digunakan dalamrancangan dideklarasikankemudian dilakukukaninterkoneksi semuakomponen yang digunakandalam rancangan.
Contoh:
Model Fulladder pada skema berikut disusundengan 2 komponen halfadder dan 1 OR-gate.
23-Sep-05 EM 6021 Advance VLSI Design
2.1.1 Deklarasi Komponen
• Deklarasi komponendilakukan di bagiandeklarasi padaarchitecture
• Port List komponentidak menggantikandeklarasi hubungansinyal.
Contoh:entity FULLADDER is
port (A,B, CARRY_IN: in bit;
SUM, CARRY: out bit);
end FULLADDER;
architecture STRUCT of FULLADDER is
signal W_SUM, W_CARRY1, W_CARRY2 : bit;
component HALFADDER
port (A, B : in bit;
SUM, CARRY : out bit);
end component;
component ORGATE
port (A, B : in bit;
RES : out bit);
end component;
Begin
…………..;
23-Sep-05 EM 6021 Advance VLSI Design
2.1.2 Pemasangan Komponen : Cara-1
• Sebanyak sesuaikebutuhan model.
• Pemasangan dilakukandalam bagian definisipada architecture (setelah 'begin')
• Seperti penempatansocket pada PCB
• Interkoneksi dilakukandengan port map
• Sinyal-sinyal wire:
– Default : sesuaidengan posisinya.
Contoh:architecture STRUCT of FULLADDER is
component HALFADDERport (A, B : in bit;
SUM, CARRY : out bit);
end component;
component ORGATEport (A, B : in bit;
RES : out bit);
end component;
signal W_SUM, W_CARRY1, W_CARRY2: bit;
beginMODULE1: HALFADDER
port map( A, B, W_SUM, W_CARRY1);
MODULE2: HALFADDERport map ( W_SUM, CARRY_IN,
SUM, W_CARRY2 );
MODULE3: ORGATEport map (W_CARRY2, W_CARRY1, CARRY);
end STRUCT;
23-Sep-05 EM 6021 Advance VLSI Design
2.1.3 Pemasangan Komponen : Cara-2Contohentity FULLADDER is
port (A,B, CARRY_IN: in bit;SUM, CARRY: out bit);
end FULLADDER;
architecture STRUCT of FULLADDER is
component HALFADDER
port (A, B : in bit;SUM, CARRY : out bit);
end component;………………….
signal W_SUM, W_CARRY1, W_CARRY2 : bit;
Begin
MODULE1: HALFADDERport map ( A => A,
SUM => W_SUM,
B => B,CARRY => W_CARRY1 );
. . .end STRUCT;
• Interkoneksi dilakukandengan simbol “=>”.
• Hubungan padapenyebutan:
– Bagian kiri:
"formal"
(nama port dari
deklarasi
component)
– Bagian Kanan:
"aktual"
(dari sinyal-sinyal
architecture)
• Urutannya Bebas
23-Sep-05 EM 6021 Advance VLSI Design
2.1.3 Pemodelan Struktural : Contoh
Contoh:
Skematik berikut akan dikodekan dalam VHDL struktural
23-Sep-05 EM 6021 Advance VLSI Design
2.1.4 Pemodelan Struktural: Contoh
Library yang digunakan
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY structural_code_ent IS
PORT ( inA : IN std_logic;
inB : IN std_logic;
inC : IN std_logic;
inD : IN std_logic;
outE : OUT std_logic);
END structural_code_ent;
ARCHITECTURE structural_code_arch OF
structural_code_ent IS
COMPONENT AND_gate_ent
PORT (AND_input1 : IN std_logic;
AND_input2 : IN std_logic;
AND_output : OUT std_logic);
END COMPONENT;……………………………
Entity
Arsitektur
Deklarasi komponen
AND_gate_ent
(model AND_gate_end
sudah dituliskan terlebih
dulu)
23-Sep-05 EM 6021 Advance VLSI Design
2.1.5 Pemodelan Struktural: Contoh……………………………
COMPONENT OR_gate_ent
PORT (OR_input1 : IN std_logic;
OR_input2 : IN std_logic;
OR_output : OUT std_logic);
END COMPONENT;
COMPONENT NAND_gate_ent
PORT (NAND_input1 : IN std_logic;
NAND_input2 : IN std_logic;
NAND_output : OUT std_logic);
END COMPONENT;
SIGNAL signal1, signal2 : std_logic;
BEGIN
logic_AND: AND_gate_ent
PORT MAP (inA, inB, signal1);
logic_OR : OR_gate_ent
PORT MAP (signal1, inC, signal2);
logic_NAND: NAND_gate_ent
PORT MAP (signal2,inD, outE);
END structural_code_arch;
……………………………
Deklarasi komponen
OR_gate_ent
Deklarasi komponen
NAND_gate_ent
Interkoneksi komponen
dengan PORT MAP
23-Sep-05 EM 6021 Advance VLSI Design
2.1.5 Pemodelan Struktural: Contoh
……………………………
CONFIGURATION structural_code_config OF structural_code_ent IS
FOR structural_code_arch
FOR logic_AND: AND_gate_ent
USE ENTITY
WORK.AND_gate_ent(AND_gate_arch);
END FOR;
FOR logic_OR: OR_gate_ent
USE ENTITY
WORK.OR_gate_ent(OR_gate_arch);
END FOR;
FOR logic_NAND: NAND_gate_ent
USE ENTITY
WORK.NAND_gate_ent(NAND_gate_arch);
END FOR;
END FOR;
END structural_code_config;
Konfigurasi
Konfigurasi
AND_gate_ent
Konfigurasi
OR_gate_ent
Konfigurasi
NAND_gate_ent
23-Sep-05 EM 6021 Advance VLSI Design
Tugas Cepat
……………………………
BEGIN
logic_AND: AND_gate_ent
PORT MAP (inA, inB, signal1);
logic_OR : OR_gate_ent
PORT MAP (signal1, inC, signal2);
logic_NAND: NAND_gate_ent
PORT MAP (signal2,inD, outE);
END structural_code_arch;
……………………………
Gantilah coding VHDL pemasangan komponen
pada contoh yang telah disampaikan dengan
coding VHDL pemasangan komponen cara-2,
yaitu menggunakan simbol “=>” pada port map.
23-Sep-05 EM 6021 Advance VLSI Design
3. Pemodelan Logika Kombinasional
Pada pemodelan combinational
logic murni, perlu
menghindari combinational
feedback loop.
Secara umum, model yang
menggunakan feedback loop
tersebut dapat disintesis,
tetapi hardware tidak dapat
berfungsi.
Contoh:
architecture EXAMPLE ofFEEDBACK is
signal B,X : integer range 0 to 99;
beginprocess (X, B)begin
X <= X + B;end process;
. . .end EXAMPLE;
23-Sep-05 EM 6021 Advance VLSI Design
3.1 Pengaruh Gaya Coding VHDL
• Implementasi
Langsung
Disintesis akan
membentuk 2
adder
• Manual
Resource
Sharing
Disintesis akan
membentuk 1
adder
Contoh 1:EXP1 : process (SEL, A, B,C)beginif SEL = `1` thenZ <= A + B;
elseZ <= A + C;
end if;end process EXP1
Contoh 2:EXP2 : process (SEL,A,B,C)variable TMP : bit;
beginif SEL = `1` thenTMP := B;
elseTMP := C;
end if;Z <= A + TMP;
end process EXP2;
23-Sep-05 EM 6021 Advance VLSI Design
Alternative Coding
Contoh 3:CB <= B when sel=‘1’ else
C;
Z <= A + CB;
23-Sep-05 EM 6021 Advance VLSI Design
3.2 Optimisasi Penulisan Source Code
Suatu operasi dapat dituliskan secara sangat efisien untuk
sintesis.
Contoh 1:OUT1 <= IN1+IN2+IN3+IN4+
IN5+IN6
Contoh 2:OUT2<=((IN1+IN2)+(IN3+IN4))
+ (IN5+IN6)
23-Sep-05 EM 6021 Advance VLSI Design
3.3 Struktur IF dan Struktur CASE
Penulisan deskripsi yang berbeda akan memberikan hasil sintesis
yang berbeda.
Contoh 1:· · ·if (IN > 17) then
OUT <= A ;elsif (IN < 17) then
OUT <= B ;else
OUT <= C ;end if ;· · ·
Contoh 2:· · ·case IN is
when 0 to 16 =>OUT <= B ;
when 17 =>OUT <= C ;
when others =>OUT <= A ;
end case ;· · ·
23-Sep-05 EM 6021 Advance VLSI Design
3.3 Implementasi Bus Data
Untuk mengimplementasikan sistem bus internal yang tepat
harus dipastikan bahwa hanya satu sinyal driver yang
aktif sementara sinyal driver yang lainnya di-set pada
high impedance ‘Z’., atau satu driver bernilai ‘1’ dan yang
lainnya ‘0’, tergantung teknologi yang digunakan.
Contoh 1:entity TRISTATE is
port(DATA1,DATA2 : in std_ulogic;
EN1, EN2 : in std_ulogic;
DATA_BUS : out std_logic );
end TRISTATE;
23-Sep-05 EM 6021 Advance VLSI Design
3.3 Implementasi Bus Data (lanjutan)
Contoh RTL1 dengan IF:architecture RTL1 of TRISTATE isbegin
process (DATA1, EN1)begin
if EN1 = '1' thenDATA_BUS <= DATA1;
elseDATA_BUS <= 'Z';
end if;end process;
process (DATA2, EN2)begin
if EN2 = '1' thenDATA_BUS <= DATA2;
elseDATA_BUS <= 'Z';
end if;end process;
end RTL1;
Contoh RTL2 dengan WHEN:
architecture RTL2 of TRISTATE isbegin
DATA_BUS <= DATA1 when EN1 = '1' elseDATA2 when EN2 = '1' else 'Z';
end RTL2;
23-Sep-05 EM 6021 Advance VLSI Design
3.4 Permasalahan dg Struktur Bus Internal
Bus dengan driver Tristate
• Delay Propagasi yang
berbeda-beda.
• Controller bus harus
memastikan paling tidak satu
driver aktif pada bus
• Tergantung teknologi yang
digunakan
Untuk menghindari permasalahan ini maka digunakan
Multiplexer
23-Sep-05 EM 6021 Advance VLSI Design
3.5 Struktur Bus yang Aman & Portable
Multiplexer menggantikan driver tristate mengeliminasi
internal bus.
23-Sep-05 EM 6021 Advance VLSI Design
3.6 Rangkaian Multiplexer
Multiplexer
w0
w1
w2
w3
s0
s1
f
W311
W201
W110
W000
fS2S1
Contoh:
LIBRARY ieee;USE ieee.std_logic_1164.all
ENTITY mux4to1 ISPORT ( w0,w1,w2,w3 : IN std_logic;
s : IN std_logic_vector(1 downto 0);
f : OUT std_logic);END mux4to1 ;
ARCHITECTURE RTL of mux4to1 IS BEGIN
f <= w0 when s="00" else
w1 when s="01" else
w2 when s="10" else
w3 ;
END RTL;
23-Sep-05 EM 6021 Advance VLSI Design
3.7 Rangkaian DekoderDecoder
w0
w1
y0
en
y1
y2
y3
0
0
0
1
0
y1
0
0
0
0
1
y0
00xx0
1
1
0
0
w1
1
0
1
0
w2
101
011
001
001
y3y2En
Contoh:LIBRARY ieee;USE ieee.std_logic_1164.all
ENTITY dec2to4 ISPORT ( w : IN std_logic_vector(1
downto 0);en: IN std_logic;y : OUT std_logic_vector(3
downto 0));END dec2to4 ;
ARCHITECTURE RTL of mux4to1 IS SIGNAL enw : std_logic_vector(2
downto 0);BEGIN
enw <= en&w;
y <= “1000” when enw=“100" else
“0100” when enw=“101" else
“0010” when enw=“110" else
“0001” when enw=“111" else
“0000”;
END RTL;
23-Sep-05 EM 6021 Advance VLSI Design
3.8 Rangkaian EncoderEncoder
w0
w1
y0
y1
w2
w3
1
0
0
0
w3
1
0
1
0
y0
1
1
0
0
y1
0
0
1
0
w1
0
0
0
1
w0
0
1
0
0
w2
Contoh:
LIBRARY ieee;USE ieee.std_logic_1164.all
ENTITY enc4to2 ISPORT ( w : IN std_logic_vector(3
downto 0);y : OUT std_logic_vector(1
downto 0));END enc4to2;
ARCHITECTURE Behavior of enc4to2 IS BEGIN
y <= “11” when w(3)=‘1’ else
“10” when w(2)=‘1’ else
“01” when w(1)=‘1’ else
“00”;
END Behavior;
23-Sep-05 EM 6021 Advance VLSI Design
3.9 Rangkaian Code Converter
Code Converter
BCD to 7-Segment
10011111100
11001100010
11011011010
11111010110
00001111110
11111110001
1
1
0
1
d
0
1
0
1
e
1
0
0
1
f
1
1
1
1
b
1
0
1
1
c
1
0
0
0
w3
1
1
0
0
g
1
1
0
1
a
0
1
0
0
w1
1
0
1
0
w0
0
0
0
0
w2
w0
w1
a
b
c
dw2
w3e
f
g
23-Sep-05 EM 6021 Advance VLSI Design
3.9 Rangkaian Code Converter (cont’d)
Contoh:LIBRARY ieee;USE ieee.std_logic_1164.allENTITY seg7 IS
PORT (bcd : IN std_logic_vector(3 downto 0);leds: OUT std_logic_vector(7 downto 0));
END seg7 ;
ARCHITECTURE Behavior of seg7 IS BEGINPROCESS (bcd)BEGIN
CASE bcd IS --abcdefgWHEN “0000”=> leds<= “1111110;WHEN “0001”=> leds<= “0110000;WHEN “0010”=> leds<= “1101101;WHEN “0011”=> leds<= “1111001;WHEN “0100”=> leds<= “0110011;WHEN “0101”=> leds<= “1011011;WHEN “0110”=> leds<= “1011111;WHEN “0111”=> leds<= “1110000;WHEN “1000”=> leds<= “1111111;WHEN “1001”=> leds<= “1111011;
END Behavior;
Code Converter
BCD to 7-Segment
w0
w1
a
b
c
dw2
w3e
f
g
23-Sep-05 EM 6021 Advance VLSI Design
3.10 Rangkaian Comparator
ComparatorContoh:
LIBRARY IEEE;USE IEEE.std_logic_1164.all;USE IEEE.std_logic_unsigned.all;
ENTITY comp is
port ( A,B : in std_logic_vector(3 downto 0);
grt,equ,lss : out std_logic);
END comp;
ARCHITECTURE comp_behave of comp isBEGIN
equ <= '1' when A = B else '0';grt <= '1' when A > B else '0';lss <= ‘1' when A < B else’0';
END comp_behave;
A
B
grt
equ
lss
4
4
23-Sep-05 EM 6021 Advance VLSI Design
3.11 Rangkaian ADDER
23-Sep-05 EM 6021 Advance VLSI Design
3.11 Rangkaian ADDER (cont’d)
library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_signed.all;
Use ieee.std_logic_unsigned.all;
entity adder is
port(cin : outstd_logic;
a, b: instd_logic_vector (7 downto 0);
sum : outstd_logic_vector (7 downto 0);
cout: outstd_logic);
end adder;
architecture adder_bhvof adder is
signal rslt: std_logic_vector(8 downto 0);
begin
rslt<= ('0' & a) + ('0' & b);
sum <=rslt(7downto0);
cout<=rslt(8);
end adder_bhv;
Library standard
Entity
Arsitektur
Behaviour
23-Sep-05 EM 6021 Advance VLSI Design
3.11 Rangkaian ADDER (cont’d)
entity add_tb isend add_tb;
architecture add_tb_struc of add_tb iscomponent adderport(a, b : in std_logic_vector (7downto0);
sum : out std_logic_vector (7downto0);cout: out std_logic);
end component;
signal a, b, sum:std_logic_vector(7downto0);Signal cout : std_logic;
beginadd : adder
port map( a => a, b => b, sum => sum,cout => cout );
Entity Testbench
Deklarasi DUT
sebagai komponen
23-Sep-05 EM 6021 Advance VLSI Design
3.11 Rangkaian ADDER (cont’d)run_gen: blockBegin
ProcessBegin
a <= CONV_STD_LOGIC_VECTOR(0,8);-- “00000000”
b <= CONV_STD_LOGIC_VECTOR(0,8);wait for 100 ns;a <= CONV_STD_LOGIC_VECTOR(1,8);b <= CONV_STD_LOGIC_VECTOR(2,8);wait for 200 ns;a <= CONV_STD_LOGIC_VECTOR(3,8);b <= CONV_STD_LOGIC_VECTOR(4,8);wait for 300 ns;a <= CONV_STD_LOGIC_VECTOR(5,8);b <= CONV_STD_LOGIC_VECTOR(6,8);wait for 40000 ns;
end process;end block;
end add_tb_struc;configuration test_conf of add_tb is
for add_tb_strucend for;
end test_conf;
Entity Testbench
Deklarasi DUT
sebagai komponen
23-Sep-05 EM 6021 Advance VLSI Design
Example of 4bits Full Adder-- Example of a four bit adder
library ieee;
use ieee.std_logic_1164.all;
-- definition of a full adder
entity FULLADDER is
port (a, b, c: in std_logic;
sum, carry: out std_logic);
end FULLADDER;
architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
end fulladder_behav;
-- 4-bit adder
library ieee;
use ieee.std_logic_1164.all;
entity FOURBITADD is
port (a, b: in std_logic_vector(3 downto 0);
Cin : in std_logic;
sum: out std_logic_vector (3 downto 0);
Cout, V: out std_logic);
end FOURBITADD;
architecture fouradder_structure of FOURBITADD is
signal c: std_logic_vector (4 downto 0);
component FULLADDER
port(a, b, c: in std_logic;
sum, carry: out std_logic);
end component;
begin
FA0: FULLADDER
port map (a(0), b(0), Cin, sum(0), c(1));
FA1: FULLADDER
port map (a(1), b(1), C(1), sum(1), c(2));
FA2: FULLADDER
port map (a(2), b(2), C(2), sum(2), c(3));
FA3: FULLADDER
port map (a(3), b(3), C(3), sum(3), c(4));
V <= c(3) xor c(4);
Cout <= c(4);
end fouradder_structure;
23-Sep-05 EM 6021 Advance VLSI Design
SELESAI